WO2001017145A1

WO2001017145A1 - Methods and apparatus for simultaneously interfacing multiple isdn differing isdn networks

Info

Publication number: WO2001017145A1
Application number: PCT/US2000/024002
Authority: WO
Inventors: Hann J. Shyu
Original assignee: Ezenia!
Priority date: 1999-08-31
Filing date: 2000-08-31
Publication date: 2001-03-08
Also published as: AU7340800A

Abstract

The invention provides an interface apparatus including a first interface device (18) exchanges data with a first ISDN network operating at a first clock rate, a second interface device (20) concurrently exchanges data with a second ISDN network operating at a second clock signal, wherein the rates of the first and second clock signals are not substantially identical but two clock signals are locked to a common clock source, and a system bus (26) for coupling the first interface device (18) and second interface device (20) and exchanging information therewith in accordance with a reference clock.

Description

METHODS AND APPARATUS FOR SIMULTANEOUSLY INTERFACING MULTIPLE ISDN DD7FERING ISDN NETWORKS

Background of the Invention

The present invention is directed to ISDN communications and, particularly, to interface apparatus, and methods of operation thereof, supporting access to multiple ISDN networks, e.g., Tl and El networks.

Network interface cards, or NICs, provide an interface between ISDN lines and host processing equipmen such as, personal computers, videoconferencing equipment, telephony equipment, and the like. NICs receive data over the ISDN lines from other nodes (e.g., other teleconference participants), reformat it, and send it to the host, e.g., via a serial bus as an MVIP bus or an HI 00 bus. Likewise, NICs accept data from the host, repackage the data, and transmit it to the ISDN line for transfer to other network nodes.

ISDN lines typically comprise multiple bearer (or B) channels and a single data (or D) channel. The B channels carry video and audio signals. The D channel carries call information necessary for call administration. So-called "primary" ISDN service, which is used mainly by large businesses, typically provides twenty-three B channels and is clocked at 1.544 million bits per second or Mbps. (Under some circumstances, the D channel can be used as an auxiliary B channel, raising the count to twenty-four). ISDN and other interface apparatus used with these lines are referred to as Tl -compatible.

The European standard for primary ISDN service is substantially different At the physical level, it supports thirty B channels (thirty one, under some circumstances) and is clocked at 2.048 Mbps. The European standard also differs at the signaling and protocol levels. Interface apparatus used with European services are referred to as El -compatible.

Incompatibility between the Tl and El standards creates a number of problems. At the outset are added costs of manufacturing, distributing and marketing NICs. Most NICs available in the marketplace are either Tl compatible or El compatible. In order to achieve market share, manufacturers must make, market and distribute two versions of each of its boards: one for use in Europe; one for use in the U.S. and elsewhere.

The incompatibility also greatly complicates establishing ISDN connections in emerging markets supporting both Tl and El standards. At present, ISDN service providers would have to accommodate this via switching equipment to reformat the signals to a common protocol.

In view of the foregoing, an object of this invention is to provide NIC apparatus and methods that support simultaneous communications on networks, such as Tl and El, operating at data transmission rates.

A related object is to provide such apparatus and methods that permits multichannel ISDN communications, e.g., bonding or inverse multiplexing, using different ISDN networks.

A related object of the invention is to provide such apparatus and methods that operate robustly, yet, can be implemented at minimal cost and with minimal power consumption.

Summary of the Invention

The aforementioned objects are attained by the invention which provides, in one aspect, NICs or other apparatus capable of simultaneously interfacing multiple ISDN networks that operate at different clock rates. The apparatus permits a single NIC or other node, for example, to simultaneously carry on communications over Tl and El netwoiks while using a common timing base for data transfers over both.

The apparatus includes a first interface device, such as a Tl/El transceiver chip, that exchanges data with an ISDN network operating at a first clock rate. This can be, for example, an El ISDN network operating at the standard rate of 2.044 MHz. A second interface device concurrently exchanges data with a second ISDN network operating at a different rate, e.g., an Tl ISDN network operating at 1.544 MHZ.

The first and second interface devices drive data onto the respective networks in accord with respective clock signals. Though the frequency of those clock signals differ (i.e., in accord with the speeds of the respective networks), they are locked to a common clock. This insures that the clock signals stay within relative synchronism, given differences in their speeds, and will tend not to "run away" from one another.

Further aspects of the invention provide apparatus as described above in which the common clock is the receive clock signal of one of the ISDN networks. Thus, depending on which interface device is assigned the role of "master," the common clock can be the receive clock signal of the Tl ISDN network or the El ISDN network. Of course, if the apparatus provides an interface to another network, its receive clock signal can be used instead. Though not explicitly transmitted on ISDN networks, those skilled in the art will appreciate that receive clock signals are implicit in received data transmissions.

An ISDN interface apparatus as described above can utilize clocking circuitry to generate a reference clock signal from the aforementioned receive clock signal, i.e., the ISDN clock received by the master interface device. Indeed, this clocking circuitry can be an integral part of the interface device, e.g., in the manner of the so-called clock rate adapter circuitry of the Conexant Bt8370 tranceivers.

Additional clocking circuitry can be used to generate the clock signal (i.e., the transmit clock signal) that the "slave" interface device uses to drive data to its respective ISDN network. As above, that clocking circuitry can be an integral part to the interface device itself.

Still further aspects of the invention provide interface apparatus as described above in which the reference clock signal governs the timing of transfers on a system bus internal to the apparatus. Thus, for example, that signal is used to clock transfers between the interface devices and a communications processor, switch or other device within the apparatus.

Yet still further aspects of the invention provide methods of interlacing multiple ISDN networks paralleling the operations described above.

Brief Description of the Drawings

A more complete understanding of the invention may be attained by reference to the drawings, in which:

Fig. 1 depicts a NIC or other ISDN interface apparatus in accord with the invention;

Fig. 2 depicts an arrangement of transceivers and a multiplexing device in an interface apparatus according to the invention;

Fig. 3 depicts a routing of clock signals between transceivers in a configuration of an apparatus according to invention for interfacing like ISDN networks; and

Fig.4 depicts a routing of clock signals between transceivers in a configuration of an apparatus according to invention for interfacing differing ISDN networks.

Detailed Description of the Illustrated Embodiment

Fig. 1 depicts an interface apparatus 10, according to one practice of the invention, that simultaneously interfaces with multiple ISDN lines 12, 14, 16. These lines can all be Tl lines, all El lines or a combination of both Tl and El lines. Though only three ISDN lines are shown in the drawing (and only two discussed below), it will be appreciated that the teachings herein can be applied to any number ISDN lines, two or higher. Moreover, those teachings can be applied to interfacing ISDN lines operating in accord with standards other than Tl and El. Still further, those teachings are applicable in to interfacing telephony lines and networks other than ISDN, particularly, where it is necessary or desirable to drive transmissions on those multiple lines in accord with a common clock source.

The apparatus 10 includes multiple transceivers 18, 20, 22, each capable receiving data from a respective one of lines 12, 14, 16 and for driving data thereto in accord with the protocol required for that line. In the illustrated embodiment, the transceivers are Bt8370 single chip transceivers of the type available from Conexant Systems, Inc. ("Conexant"). Other transceivers capable of interfacing Tl and or El ISDN lines may be used.

A multiplexing device 24 is used to route clock signals among the transceivers 18, 20, 22, as discussed in further detail below, so as to permit transmissions on lines 12, 14, 16 in accord with a common clocking source.

The multiplexing device 24 can also transfer data and control signals between the transceivers 18, 20, 22 and a system bus 26, to which other elements of the interface apparatus 10 are connected. In the illustrated embodiment, those elements include cross-point switch that routes control and data signals between the transceivers, a communications processor 30 and a host device 32, all of which are constructed and operated in the conventional manner known in the art. In alternate embodiments, system bus 26 is coupled to other elements of the interface apparatus 10, in addition to or in lieu of elements 28 and 30. Illustrated cross-point switch comprises any conventional device of this nature of the type known in the art. One such device is the Flexible MVIP Interface Circuit (FMIC), which is intended for transferring data to the host 32 over a conventional MVIP bus 34. Where necessary or desired, e.g., to provide multidrop support, the multiplexing device 24 can include time base correction circuitry of the type described in copending, commonly assigned United States Patent AppUcation Serial No. 09/328,547, filed June 9, 1999, for METHOD AND APPARATUS FOR TRANSMITTING DATA BETWEEN A TIME-DIVISION MULTIPLEXED BUS AND PLURAL ISDN LINES, the teachings of which are incorporated herein by reference.

In alternate embodiments, the multiplexing device 24 can provide the switehing/routing function itself, e.g., in the manner of time-variant multiplexors described in copending, commonly assigned United States Patent Application Serial No.09/313,500, filed May 17, 1999, for METHODS AND APPARATUS FOR ROUTING DATA WπΗIN, AND EFFECTING SERIAL DATA TRANSFERS WITH, AN ISDN COMMUNICATIONS INTERFACE, the teachings of which are incorporated herein by reference.

Illustrated communications processor 30 comprises a Motorola® MC68MH360 microprocessor, although other types of processors may be used instead. The processor 30 facilitates call administration in the conventional manner known in the art It can also oversee inverse multiplexing ("bonding") as described in copending, commonly assigned United States

Patent Application Serial No. 09/330,578, filed June 11, 1999, for INVERSE MULTIPLEXING and corresponding application PCT/US99/13282 SYSTEM FOR ISDN COMMUNICATIONS,^ teachings of which are incorporated herein by reference. Moreover, it can be utilized to provide parallel transfers to the host in the manner of copending, commonly assigned United States Patent Application Serial No. 09/240,528, filed

January 29, 1999, for METHOD AND APPARATUS FOR EFFECTING PARALLEL DATA

TRANSFERS BETWEEN A NETWORK INTERFACE CARD AND A HOST, the teachings of which are also incorporated herein by reference.

Illustrated host 30 represents a personal computer, video conferencing equipment or other apparatus to which the apparatus 10 is coupled and for which it serves as an ISDN interface. A general understanding of the functions, structure and operation of interface apparatus 10 can be attained by reference to the aforementioned copending, commonly assigned appUcations, the teachings of which are incorporated by reference. Discussed below are the functions, structure, operation and cooperation of multiplexing device 24 and transceivers 18, 20, 22 with regard to the routing of clock signals among the transceivers and with regard to transmissions on lines 12, 14, 16 in accord with a common clocking source.

Fig. 2 depicts transceivers 18, 20 and multiplexing device 24 in greater detail. With respect to device 24, only shown are those aspects pertaining to the routing of clock signals among the transceivers and the transmission on lines 12, 14 in accord with a common clocking source. For simpUcity, only two transceivers 18, 20 are depicted. The teachings with respect thereto are appUcable to embodiments incorporating three or more transceivers, as weU.

Illustrated transceivers 18, 20 comprise the aforementioned Bt8370 single chip transceivers, which are commercially available from Conexant Other chips from that suppUer's Bt8370/8375 product family may be used, as may competing products from other suppUers. The use and operation of the iUustrated Bt8370 transceivers is described in Document N8370DSD, entitled "Bt8370/8375/8376 - Fully Integrated Tl/El Framer and Line Interface," available from Conexant, the teachings of which are incorporated herein by reference.

Transceivers 18, 20 transfer data between their respective analog ISDN lines 12, 14 and the digital system bus 26. Receive data received by the transceivers from other nodes via the respective ISDN lines 12, 14 are applied to bus 26 via the iUustrated DATAO (data output) pins. In the iUustrated embodiment, that receive data is appUed to system bus 26 in accord clock signals on the RSB TSB pins (representing tied RSBCKI and TSBCKI pins of the Bt8370/8375 product family). Receive clock signals, representing the timing of receive data signal transitions on the ISDN lines, are output via the RCKO (receive clock output) pins.

Transmit data to be sent to other nodes via the ISDN lines 12, 14 are appUed to the DATAI pins of the respective transceivers. That data is received from the system bus 26 in accord with clock signals on the RSB/TSB pins. Transmit data is appUed to the respective ISDN lines 12, 14 in accord with clock signals appUed to the TCKI pins of the respective transceivers.

In addition to transferring receive data and transmit data between the ISDN lines 12, 14 and the system bus 26, each transceiver 18, 20 of the aforementioned Bt8370/8375 product family includes programmable clock rate adapter circuitry, which is capable of generating an output clock signal (CLADO) that is locked to any of several input clock signals, including an ISDN receive clock signal (RXCLK) and an input clock signal (CLADI). The operation and internal architecture of the Bt8370/8375 product farmly is more particularly described in Section 2.6 ("Clock Rate Adapter") of aforementioned Document N8370DSD, which is filed as attachment herewith.

Transceivers having circuitry functionaUy similar to the Conexant clock rate adapter may be used in place the iUustrated Bt8370 transceivers. Alternatively, transceivers without such circuitry may be used in connection with separate clocking circuitry (not shown) providing similar funcuonakty.

IUustrated multiplexing device 24 comprises a pluraUty of multiplexors 24a, 24b, 24c, 24d. These are configured by processor 30 to route the receive clock signals (RCKO) and/or clock rate adapter output signals (CLADO) signals as described below. By configuring the transceivers appropriately, as also described below, the clocking of transmit data appUed by the transceivers 18, 20 to the ISDN lines 12, 14 can be locked to a common clock source — regardless of whether the lines are of the same ISDN type (e.g., regardless of whether the lines 12, 14 are both Tl lines or whether one is a Tl line and the other is an El line).

Multiplexor device 24 can be implemented via a field programmable gate array ("FPGA"), although it can be implemented in an appUcation-specific integrated circuit ("ASIC"), or other logic device, as weU.

The common clock source in the iUustrated embodiment is the receive clock signal of the transceiver designated as the master, e.g., transceiver 18 in Figs. 3 and 4. Those skiUed in the art wUl appreciate that another clock signal could be used as the common clock source, e.g., so long as the resulting transmit clock signals otherwise meet applicable ISDN standards.

Fig. 3 iUustrates the routing of clock signals between the ISDN transceivers 18, 20 in a configuration for interfacing two similar networks. In the iUustration, both ISDN lines 12, 14 are Tl lines, though they could likewise both be El lines, or both lines of another ISDN standard.

Referring to that drawing, the timing of receive data by transceivers 18, 20 is controUed by the receive clock signals of their respective ISDN lines 12, 14.

The timing of transmit data sent by transceivers 18, 20 to the lines 12, 14 is governed by receive clock signal of ISDN line 12. To this end, multiplexor 24c is configured to route the receive clock signal (RCKO) of the master transceiver 18 to the transmit clock signal input (TCKI) of the slave transceiver 20, which uses that signal to drive data on line 14. The master 18, itself, can be configured to generate its transmit clock signal directly from the receive clock signal received on line 12. Preferably, however, multiplexors 24b and 24c route the receive clock signal (RCKO) generated by master 18 back to that transceiver's own transmit clock signal input (TCKT), which drive the timing of transmit data on line 12.

The routing of the master transceiver's RCKO signal in this regard is shown by thick lines in Fig. 3. A similar configuration, albeit "reversed," is used if transceiver 20 is the master and transceiver 18 is the slave.

In the iUustrated embodiment, the timing of data exchanges between transceivers 18, 20 and system bus 26 is governed by the clock rate adapter output (CLADO) of the master transceiver 18, which multiplexor 24a routes to the RSB/TSB inputs of both transceivers 18, 20. In a preferably embodiment, the clock rate adapter of transceiver 18 is configured to generate a 4.096 MHz locked to the receive clock signal of line 12. Other rates and reference sources can be used, as weU. Fig. 4 iUustrates the routing of clock signals between the ISDN transceivers 18, 20 in a configuration for interfacing two dissimilar networks, i.e., Tl and El networks, transmissions on which utilize different respective timings . In the illustration, master transceiver 18 is connected to El ISDN line 12, whUe slave transceiver 20 is connected to Tl ISDN line 14. Of course, other arrangements of master and slave can be used, as can other assignments of the ISDN lines (e.g., transceiver 20 can be assigned the status of master, whether coupled to an El or Tl line).

As above, the timing of receive data by transceivers 18, 20 is controlled by the receive clock signals of their respective ISDN lines 12, 14. Likewise, timing of data exchanges between transceivers 18, 20 and system bus 26 is governed by the clock rate adapter output (CLADO) of the master transceiver 18, whose 4.096 MHZ output, referred to elsewhere herein as a "reference" clock signal, is routed by multiplexors 24b - 24d to the RSB TSB pins of both transceivers 18, 20.

The timing of transmit data sent by transceivers 18, 20 to the lines 12, 14 is governed by receive clock signal of ISDN line 12, however, not as directly as above. SpecificaUy, multiplexor 24a routes the 4.096 MHZ CLADO output of transceiver 18 (which is locked by that transceiver's clock rate adapter to the receive clock signal on line 14) to the CLADI input of slave transceiver 20. That transceiver's clock rate adapter is, in turn, configured to generate an output (CLADO) that is locked to its CLADI input and, thereby, to the CLADO output of master transceiver 18 and the receive clock signal on line 12.

Multiplexor 24c routes the CLADO output of slave transceiver 20 back to that transceiver's own TCKI input, thereby, effectively locking the transmit clock signal on line 14 to the receive clock signal on line 12. As further shown in Fig. 4, multiplexor 24b is configured to route the receive clock signal (RCKO) of the master transceiver 18 to the transmit clock signal input (TCKI) of the slave transceiver 20, which uses that signal to drive data on line 14. A consequence of this configuration is that transmit clock signals on lines 12 and 14 are locked to the same clocking source (to wit, the receive clock signal on line 12), even though lines 12 and 14 are of different types (Tl vs. El) and, therefore, operate at different rates. The routing of clock signals in the above-described configuration is reflected by thick lines in Fig. 4. A similar configuration, albeit "reversed," is used if transceiver 20 is the master and transceiver 18 is the slave.

Described above is an ISDN apparatus 10 and method of operation meeting the desire objects. Those skiUed in the art wiU appreciate that the embodiment shown and discussed here is merely an example of the invention and that other apparatus and methods incorporating changes therein faU within the scope of the invention. By way of non-limiting example, it wiU be appreciated that the reference clock signal of rates other than 4.096 MHz may be used. By way of further non-limiting example, it wiU be appreciated that multiplexor device 24 may be hardwired or implemented in other manners that permit apparatus 10 to drive differing ISDN lines, albeit using a common clocking source as a basis of transmit clock signals.

h view thereof, what I claim is:

Claims

1. An ISDN network interface apparatus, comprising

a first interface device coupled to a first ISDN network, the first interface transmitting data to the first ISDN network in accord with a first clock signal,

a second interface device coupled to a second ISDN network, the second interface transmitting data to die second ISDN network in accord with a second clock signal,

wherein rates of the first and second clock signals are not substantiaUy identical, but wherein the first and second clock signals are locked to a common clock source.

2. An apparatus according to claim 1 , wherein the first ISDN network is a member of a group consisting of an Tl ISDN network and an El ISDN network, and wherein the second ISDN network is another member of that group.

3. An apparatus according to claim 2, wherein the first and second devices are T 1 E 1 transceiver devices.

4. An apparatus according to claim 1 , wherein the common clock source is a receive clock signal received by the first interface device from the first ISDN network.

5. An apparatus according to claim 4, comprising

first clocking circuitry, coupled to the first ISDN network, that generates a reference clock signal from the receive clock signal, and

second clocking circuitry, coupled to the first clocking circuitry and to the second interface device, that generates the second clock signal locked to die reference clock signal.

6. An apparatus according to claim 5, wherein any of the first clocking circuitry is integral to the first interface device, and

the second clocking circuitry is integral to the second interface device.

7. An apparatus according to claim 5, comprising

a system bus,

the first interface device, the second interface device and at least one other device,

the first interface device, the second interface device and the other device being coupled to the system bus and exchanging information therewith in accord with the reference clock.

8. An ISDN network interface apparatus, comprising

a first interlace device coupled to a first ISDN network, the first interface device exchanging data with the first ISDN network in accord with a first clock signal received from the first ISDN network,

the first interface device including first clocking circuitry responsive to the first clock signal to generate a reference clock signal,

a second interface device coupled to the first interface device and to a second ISDN network, the second interface transmitting data to the second ISDN network in accord with a second clock signal,

the second interface device including second clocking circuitry responsive to the reference clock signal to generate the second clock signal locked to the reference clock signal and, thereby, locked to a first clock.

9. An apparatus according to claim 8, comprising

a system bus,

10. An apparatus according to claim 9, wherein the other device is any of a communications processor and a switching device.

11. An apparatus according to claim 9, wherein the first ISDN network is a member of a group consisting of an Tl ISDN network and an El ISDN network, and wherein the second ISDN network is another member of that group.

12. An apparatus according to claim 11, wherein the first and second devices are Tl/El interface chips.

13. A method of interfacing to multiple ISDN networks, comprising the steps of

transmitting data to a first ISDN network in accord with a first clock signal,

transmitting data to a second ISDN network in accord with a second clock signal,

14. A method according to claim 13, wherein the first ISDN network is a member of a group consisting of an Tl ISDN network and an El ISDN network, and wherein the second ISDN network is another member of that group.

15. A method according to claim 14, comprising the steps of transmitting data with the first and second ISDN networks with respective Tl/El transceiver devices.

16. A method according to claim 13, wherein the common clock source is a receive clock signal received from the first ISDN network.

17. A method according to claim 16, comprising the steps of

receiving the receive clock signal from the first ISDN network,

generating a reference clock signal from the receive clock signal, and

generating the second clock signal locked to the reference clock signal.

18. A method of interfacing multiple ISDN networks with an ISDN network device of the type having

a first interface device coupled to a first ISDN network, the first interface device exchanging data with the first ISDN network in accord with a first clock signal received from the first ISDN network,

the method comprising the steps of generating a reference clock signal that is locked to the first clock signal,

generating the second clock signal locked to the reference clock signal and, thereby, locked to a first clock.

19. A method according to claim 18, including the steps of

generating the reference clock signal with the first interface device,

generating the second clock signal with the second interface device.

20. A method according to claim 19, wherein the ISDN network device is of the type having

a system bus,

the method comprising the step of

exchanging information between each of the first interface device, the second interface device and the other device in accord with the reference clock.

21. A method according to claim 20, wherein the other device is any of a communications processor and a switching device.

22. A method according to claim 20, wherein the first ISDN network is a member of a group consisting of an Tl ISDN network and an El ISDN network, and wherein the second ISDN network is another member of that group.

23. A method according to claim 22, wherein the first and second devices are Tl/El interface chips.

24. An ISDN network interface apparatus, comprising

a first interface device coupled to any of a Tl ISDN network and an El ISDN network, the first interface device transmitting data on that network in accord with a first clock signal,

a second interface device coupled to any of a Tl ISDN network and an El ISDN network, the first interface device transmitting data on that network in accord with a second clock signal,

clocking circuitry that generates the first and second clock signals locked to a common clock source, regardless of whether the first and second interface devices are coupled to like networks.

25. An apparatus according to claim 24, wherein the common clock source is a receive clock signal received by the first interface device from the ISDN network to which it is coupled.

26. An apparatus according to claim 25, comprising

second clocking circuitry, coupled to the first clocking circuitry and to the second interface device, that generates the second clock signal locked to the reference clock signal.

27. An apparatus according to claim 26, wherein any of

the first clocking circuitry is integral to the first interface device, and the second clocking circuitry is integral to the second interface device.

28. An apparatus according to claim 27, comprising

a system bus,

29. A method of operating an ISDN network interface apparatus having

a first interface device that can be coupled to an ISDN network and that transmits data on that network in accord with a first clock signal,

a second interface device that can be coupled to an ISDN network and that transmits data on that network in accord with a second clock signal,

the method comprising

coupling the first interface device to any of a Tl ISDN network and an El ISDN network

coupling the second interface device to any of a Tl ISDN network and an El ISDN network,

generating the first and second clock signals locked to a common clock source, regardless of whether the first and second interface devices are coupled to like networks.

30. A method according to claim 29, wherein the common clock source is a receive clock signal received by the first interface device from the ISDN network to which it is coupled.

31. A method according to claim 30, comprising

generating a reference clock signal from the receive clock signal, and

generating the second clock signal from, and locked to, the reference clock signal.

32. A method according to claim 31 , comprising

generating the reference clock signal with circuitry that is integral to the first interface device, and

generating the second clock signal with circuitry that is integral to the second interface device.

33. A method according to claim 32, comprising

a system bus,

34. A method according to claim 33, wherein the ISDN network device is of the type having

a system bus, the first interface device, the second interface device and at least one other device,

the method comprising the step of