WO2001011538A2

WO2001011538A2 - Discrete computer system

Info

Publication number: WO2001011538A2
Application number: PCT/US2000/040580
Authority: WO
Inventors: Preeth Kumar Patil
Original assignee: Preeth Kumar Patil
Priority date: 1999-08-09
Filing date: 2000-08-07
Publication date: 2001-02-15
Also published as: AU7757200A; WO2001011538A3

Abstract

A multi-level discrete computer system (100) comprised of a central processing unit, CPU, (105) for processing multi-level discrete signals (mits), memory means (110) for storing multi-level mits of data, input means (115) for receiving mit data from external devices and forwarding said mit data to said central processing unit, output means (120) for receiving mit data from said central processing unit and forwarding said mit data to external devices, and bus lines carrying mit data for operatively connecting said central processing unit with said memory means, input means, and output means. The CPU includes an arithmetic logic unit (ALU) including logic gates, a register unit (150), and a control unit (155) for manipulating mits of data. The system also includes a level converter for converting mit data signals of a first base level to mit data signals of a second base level.

Description

TITLE OF THE INVENTION Discrete Computer System

CROSS-REFERENCE TO RELATED APPLICATIONS This application is related to and claims the benefit of the commonly owned U.S. Provisional Patent Application 60/147,857 filed August 9, 1999 and entitled "Discrete Computer System.

FIELD OF THE INVENTION

The present invention relates generally to a multilevel discrete computer system.

BACKGROUND OF THE INVENTION An analog computer uses a signal that is a continuous function of time. Typically, in analog computers, a voltage is processed and a new voltage with no distinct level is created. The voltages represent input and output signals to and from the computer. Most computers are binary digital, thus, analog signals are conditioned and converted to binary digital signals. Converted binary digital signals are processed before being converted back into analog signals for use in audio, video, and other human interface functions. Binary digital computers represent data using two discrete levels, namely, 0 and 1. The 0s and Is are typically referred to as bits of data or just bits. By using a combination of 0 or 1 bits to create a string of bits, numbers greater than one can be represented. Eight (8) bits strung together are called a byte. Most computers use multiples of bits to represent data and addresses. Computers, as of this writing, typically range from 16 bit to 128 bit machines. In data communications, efficient, high speed transmission of data has been a challenge. Digital signals are passed through a shift register and one bit of data at a time is sent onto a transmission line creating a stream of data passing over a network. The speed of a transmission line is measured in bits per second (bps) . To increase the speed or bandwidth of a network, many innovations have addressed the bit-stream. Some methods of getting more data on a transmission line include using gray scales, discrete levels, or an analog signal.

Networks are migrating from electrical based to light based (e.g., fiber optic) networks. Light can have multiple colors and each color or color strength can be represented as a distinct level of a multi-level discrete signal.

There is a constant need to store ever-larger amounts of data. With advancements in technology, disk speed has been increased making media storing magnets smaller. Data can be stored on very small magnets as different strengths and retrieved as analog signals. Typically, a signal is converted from a binary signal to an analog signal. The analog signal is then written to disk as a variable strength magnetic field. The signal when retrieved is converted using an analog-to-digital signal converter and passed to the retrieving binary device.

Most audio and video signals, though analog, may be represented as multi-level discrete signals. This is desirable since multi-level discrete signals can carry more data than an analog or binary digital signal. Most transducer signals tend to be analog signals. Signal to noise ratio and attenuation factors reduce the precision of these signals. Due to imprecision inherent in all analog signals they are treated as discrete signals. Sample and hold circuits further reduce the precision of analog signals. It is thus desirable to convert analog transducer signals into multi-level discrete signals thereby aiding in their transmission with relatively little loss of data due to attenuation or noise.

Thus, it has been shown that use of multi-level discrete signals is advantageous over binary digital or analog signals since more data can be represented in a multi-level discrete signal greatly increasing usable bandwidth. Currently, however, while there is multi-level data storage and data transmission capability, there is no multi-level processing capability. Multi-level data signals (mits) are converted to binary digital signals (bits) in order to be manipulated by a typical computer processor. What is needed is a multi-level discrete computer system that can manipulate and operate on mits without having to convert the mits to bits . Such a computer system would provide enhanced computing power, speed, and efficiency.

SUMMARY OF THE INVENTION

A multi-level discrete computer system according to the present invention is comprised of a central processing unit (CPU) for processing multi-level discrete signals (mits) , memory means for storing multi-level mits of data, input means for receiving input data from external devices, output means for forwarding output data to external devices, and bus lines for operatively connecting the central processing unit with the memory means, input means, and output means. The CPU includes an arithmetic logic unit (ALU) and associated logic gates operating on mits of data, a register unit operating on mits of data, and a control unit manipulating mits of data. The system also includes a level converter for converting mit data signals of a first base level to mit data signals of a second base level.

Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE FIGURES

FIGURE 1 illustrates a multi-level discrete computer system block diagram.

FIGURE 2 illustrates a level holder circuit for holding a multi-level discrete signal. FIGURE 3 illustrates a discrete decoder circuit for decoding a multi-level discrete signal.

FIGURE 4 illustrates a discrete decoder circuit used to implement a InCycler.

FIGURE 5 illustrates a switch circuit used to implement a InCycler.

FIGURE 6 illustrates a counter for a multi-level discrete computer system.

FIGURE 7 illustrates a level converter circuit diagram. FIGURE 8 illustrates a shift register for a multilevel discrete computer system.

FIGURE 9 illustrates a multi-level adder. FIGURE 10 illustrates a multi-level memory scheme for a multi-level discrete computer system.

DETAILED DISCLOSURE OF THE INVENTION A multi-level discrete computer according to the present invention processes a multi-level discrete signal. A multi-level discrete signal is a signal comprised of mits of data as opposed to bits of data. A multi-level discrete computer is comprised of similar elements as a binary digital computer, namely, a central processing unit (CPU), memory, and peripheral I/O devices. The main difference between a multi-level discrete computer and a binary digital computer is that a multi-level discrete computer operates directly on a multi-level discrete signal without having to convert such a signal into a binary digital signal. A binary digital computer, in contrast, operates on a binary digital signal only. The CPU and peripheral devices of a multi-level discrete computer system need not be operating at the same discrete base level. If the signals are of different base levels a level converter is employed to harmonize data operations. The present invention is described with respect to a multi-level discrete voltage signal. Signals other than voltage including, but not limited to, chemical reactions, light based frequency signals, radio frequency signals, or electro-magnetic signals, may be used or substituted without departing from the spirit or scope of the present invention.

Whereas, a binary digital computer operates on bits of data, a multi-level discrete computer operates on mits of data. "jnit" is a shorthand notation referring to a multi-level discrete signal comprised of a multi-level integer of data. The number of mits used by the data bus of a discrete computer system is deemed its word length.

A multi-level CPU is comprised of an arithmetic logic unit (ALU), registers, and a control unit. The ALU is comprised of a number of arithmetic and logic gates. Each of the arithmetic logic units has a unique address and is controlled by the control unit. ALU gates include adders, subtractors, multipliers, dividers and comparators. Additional gates for squares, square roots, etc. may also be included in the ALU. Data from two registers can be added, subtracted, multiplied, divided, compared, etc. using multi-level discrete data signals as input.

Each operation is controlled by a unique instruction that is part of an instruction set. The difference in the instruction set for a binary digital computer system and a multi-level discrete computer system is the use of mits and mit gates (as opposed to bits and bit gates) and the algorithms needed to implement a discrete computer system.

A multi-level discrete computer control unit is comprised of a clock that pulses at a defined frequency and a program counter. A program counter is a counter that increments to the next instruction after it the current instruction is executed. The program counter points to an instruction currently loaded into the instruction set. The instruction is decoded and executed using the necessary mit gates. The result is stored in a register specified by the instruction.

Voltage signals used in electrical devices typically range from 0 to 5 volts. Thus, any number between 0 and 5 can represent a voltage. A multi-level discrete computer uses discrete levels. For example, 0,1,2,3 are four (4) distinct levels recognized by a discrete computer system of base four (4) . Voltages between these integers are corrected to the nearest discrete level.

A multi-level discrete computer system operates on a base number of distinct levels . Any change in the multi- level discrete signal (mit) base to another maximum discrete level base requires a level converter. Thus, to convert a multi level discrete broadband signal to a binary digital signal and then back to a different maximum level discrete signal requires a level converter. For example, a discrete signal received on a broadband network is converted into a binary digital signal then converted to a different base (maximum level - base 2) signal. The CPU in a multi-level discrete computer, system memory, and system bus operate at these discrete levels. Multi-level data is represented as a string of multi-level mits called mytes. The maximum number of levels (the base) can vary from device to device. A typical binary digital computer uses a binary notation for data processing. A multi-level discrete computer utilizes more than two levels to process data. A binary notation is the lowest form of discrete system. The bit or binary integer notation of all numbers in a digital computer is used to process data. Eight (8) bits strung together is called a byte. The maximum value that can be represented in a byte using the decimal system is 2**8 - 1 = 255. As the number of bits increases the largest integer value that can be represented also increases. In a digital device, 0 is interpreted as no voltage and 1 as the existence of voltage, usually 5 volts. Digital signals are carried on a wire that can carry either a 0 or a 1. Depending on the bit size of the computer (e.g., lβbit, 32 bit, etc.), an equivalent number of wires are used to carry all the signals from one device to another. The wires are referred to as a bus.

Number systems are the basis on which computations are performed. Numbers may be represented in a decimal system where 10 distinct digits are used and repeated as a ring. The base of the decimal number system is 10. The numbers in a binary system are 0 or 1; i.e. two numbers are used to represent all the numbers in the number systems. The base (M) of a number system is the number of distinct digits (0,1,2,3 ...) used in the number system. When a number reaches M-l distinct digits it rings around as shown in the table below which illustrates a 2-mit base four (4) number system.

The maximum number that can be represented in a ring of n mits with a base M is Mⁿ - 1. In a 3-mit decimal (base 10) system the maximum number that can be represented is IO³ - 1 = 999. Similarly, in an 8-bit binary system, the maximum number that can be represented is 2⁸ - 1 = 255. The first mit in a word (string of mits) for a discrete system is typically a sign bit. Two (2) distinct symbols are required to represent either positive (+) or negative (-) . In a binary digital system only two distinct symbols are available, 0 and 1. Thus, the first bit in a binary digital word can only represent one of two values. In a mit, however, more than two values may be used. In a base four (4) system, four values may be used for the first mit, namely, 0,1,2, or 3. Thus, 0 can represent floating point positive, 1 can represent floating point negative, 2 can represent integer positive, and 3 can represent integer negative. The first mit can be used to represent additional features as well if the base of the number system being used is greater than four (4). For the English language, a discrete computer system needs to represent at minimum twenty-six (26) characters (upper and lower case) and 10 digits. The ASCII alphanumeric character set, which includes the aforesaid twenty-six characters and ten digits, totals 128 characters in all. In a base 4 discrete system, four (4) mits are all that is needed to represent up to 256 characters as opposed to eight (8) bits. Increasing the number of mits to a myte (8 mits) allows one to represent up to 65,536 characters, enough for the kanji (Japanese character set) and other complex character sets. To achieve the same in a binary system would require a significantly increased number of bits.

The elements of a discrete computer system are similar to the elements of a binary digital computer system. The main difference between the two types of computer systems is the way they represent and handle data, namely, bits in a binary digital computer and mits in a multi-level discrete computer. While the names and functions of the common computer elements remains the same the way each element goes about achieving its function is somewhat different in a discrete computer system as compared to a binary digital computer system.

Referring now to FIGURE 1, the elements that comprise a discrete computer system 100 are illustrated. These elements include a central processing unit (CPU) 105, memory means 110, input means 115, and output means 120. The input 115 and output 120 means are connected to various peripheral devices such as a keyboard 125, a mouse 130, a monitor 135, and a printer 140. Other devices like modems, digital video devices, external media storage devices, etc... may also be connected to the discrete computer 100 via the input 115 or output means 120.

Memory means 110 include, but are not limited to, RAM, ROM, and disk storage. RAM memory is volatile and stores data and programs temporarily during processing. ROM is non-volatile and is used to store system programs such as BIOS (Basic Input/Output System) .

CPU 105 is comprised of an arithmetic logic unit (ALU) 145, a register unit 150, and a control unit 155. CPU 105 essentially addresses a memory location, obtains (fetches) a program instruction stored there, and carries out the instruction. The fetch and execute process is repeated until all of the instructions for a given program have been executed. Data to and from CPU 105 is carried across various bus lines. An address bus 160, data bus 165, and control bus 170 are shown and carry data pertaining to their unique function to and from CPU 105 as required.

Address bus 160 is a one way outbound link over which CPU 105 sends an address code to a memory device. The size of address bus 160 (also referred to as the width) is determined by the number of mits it can handle. The more mits the bus can handle the more memory locations can be accessed. For instance, a base four (4) mit system using a sixteen (16) mit word length can access approximately

4,295,000,000 (4.295 billion) memory locations. Contrast this with a sixteen (16) bit word length binary bus that can access only 65,536 memory locations.

Data bus 165 is a two way link on which data or instruction codes are transferred into CPU 105 or on which the result of an operation or computation is sent out from CPU 105. The number of mits data bus 165 can handle depends on the CPU's mit handling capability. Control bus 170 is used by CPU 105 to coordinate its operations and to communicate with external devices. ALU 145 performs arithmetic operations such as addition and subtraction as well as logic operations such as AND and OR. Register unit 150 temporarily stores data generated during the execution of a program (set of instructions) in one or more of a plurality of registers that comprise the unit. Control unit 155 provides timing and control signals for getting data into and out of CPU 105, performs programmed instructions, and performs other operations .

A number of mits are used to make the word length of a discrete computer. The arithmetic and logic operations are carried out on each individual mit collectively. Several "mit" operations (as opposed to "myte" operations) are described below.

Level Detector

A level detector or mit comparator gate has two inputs and one output. One of the inputs is a constant voltage, if the second input voltage is the same the level detector returns an output of 0, otherwise its output is 1. U.S. Pat. No. 5,872,468, incorporated herein by reference, teaches level detector circuitry and techniques.

Inverter

An inverter takes a one mit input and converts it into a one mit output according to the following table. A base four (4) system is used for illustrative purposes.

Buffers

Buffers are circuits that hold a voltage at an input level for a single clock cycle. A voltage is accepted and output at the clock signal. The table below illustrates buffer data results.

Compara tor A comparator has two inputs and one output. The two input signals are compared and an output signal is represented as shown in the table below. If the inputs are equal to one another then the output is set to "0". If input 1 is less than input 2 then the output is set to "1". Lastly, if input 1 is greater than input 2 then the output is set to "2".

Single input - InCycler

A single input - lncycler gate has one input voltage and one output voltage. Based on 'n' , the voltage is incremented by one in a cyclic fashion. Data for an n=l lncycler is shown in the table below.

Dual Input - 2 Cycler

A dual input 2cycler receives two input voltages and has one output . An input voltage increments or decrements a number of levels based on the other input voltage. When the M-1 level is reached the next increment is cycled with a 0, and subsequent increments are thus cycled. The following table illustrates a Dual Input - 2Cycler.

Noncycler

A noncycler gate receives two inputs, incrementing one input signal by the number of levels of the second input signal only until the M-1 (base - 1) level of the discrete computer system is attained. After that the signal holds at the M-1 level instead of cycling.

Level holder - mul ti-level flip-flop - la tch

FIGURE 2 illustrates the concept of a flip-flop. When a discrete input voltage and a clock pulse are applied to a flip-flop circuit the flip-flop will set the output to the input level, even after the input is removed. This output remains until a new input voltage is applied. This is also referred to as a latch . A flip-flop circuit or latch receives an input signal and a clock signal to a switch 205. The output of switch 205 is fed to a pair of buffers 210A, 210B. Buffers 210A, 210B each have their output fed back as input to the other buffer. When an input voltage is applied to the flip-flop circuit, it holds at that voltage for one clock cycle and provides that voltage as input to the other buffer. This results in a register of one mit capacity. A series of flip-flop circuits can be used to form registers and shift registers .

Switch

A switch circuit either allows a signal to pass through a circuit or not pass based on an input control signal. One input switch control signal is binary and the other input switch signal is a multi-level mit. The output signal is also a multi-level mit when the switch is turned on. When the switch is turned off there is no output or it has 0 signal. The table below illustrates the results.

Ma trix swi tch

A matrix switch is comprised of a list of expected values where the outputs are hard wired based on the inputs. The subscripts for X_ab and Y_a range from (0,0) to (M-1, M-1) where M is the base of the system being used. The table below is one example of a base four (4) configuration.

Adder

An adder can be implemented as a matrix switch or as a 2cycler. A comparator or matrix switch can be used to obtain carry information. The following is a matrix adder that shows addition in a base four (4) discrete system.

A 2cycler may be used to implement a mit adder. The carry function can be the combination of a noncycler and a comparator to compare the voltage to 3 (i.e., the M-1 level). Anything greater will be a carry function. There are many ways obvious to those ordinarily skilled in the art that an adder can be implemented using the gates above .

Sujbtractor

A subtractor can be implemented as a matrix switch, or using the gates above. A subtractor using M' s complement (where M is the base of the discrete computer system) is shown in the table below.

Using 4's complement subtraction becomes simple addition as shown in the following table.

Multiplier

A multiplier has two mit inputs. The outputs are a carry and the result. Multipliers may be implemented using matrix switches. The following table is an example.

Divider

A divider is a 2 input gate in which the outputs are comprised of a remainder and a quotient. Two additional inputs referred to as "before borrow" and "after borrow" may also be implemented. One output condition is a division by zero error handling output. The table below illustrates an example of a divider.

Decoder

A decoder input is a set of mits. A decoder's function is to detect a particular input code (mits) and indicate the presence of the code on the output as a 0 or 1 on a line specified. A three input circuit diagram of a decoder is shown in FIGURE 3.

When voltage divider (R1,R11) provide base bias to transistor Tl, the transistor is turned on. This causes the voltage at the collector to go to zero (off) . When the transistor is turned off the voltage at the collector is at Vcc. A truth table of this bit inverter is as follows :

Referring now to stage 1 of FIGURE 3, the circuit uses 3 transistors (T1,T2,T3) as switches. Tl, R21, Rll and RI act as a first switch block, T2, R22, R12 and RI act as a second switch block, and T3, T23, R13 and RI as a third switch block. When the input is 0 voltage (level 0) the switch blocks with Tl, T2 and T3 are all off making the outputs (II, 12, 13) from the switch blocks go to Vcc.

When the input is at 1.5v, T3 is turned on since voltage divider circuit (R1,R13) is designed to provide enough base bias to T3 when the voltage is 1.5v or higher. Voltage divider (R1,R12) provide base bias to T2 and can be turned on when the voltage is 3v. Voltage divider (R1,R11) provide base bias to Tl when the input is 4.5v. When the input is 3v, T3 and T2 are turned on. When the input is 4.5v all three switch blocks are turned on and the voltage goes to zero for II, 12, and 13.

STAGE 1 TRUTH TABLE

Referring now to stage 2 of FIGURE 3, transistors T4, T5 and T6 form three more switch blocks. STAGE 2 TRUTH TABLE

STAGE 1 & 2 TRUTH TABLE TOGETHER

A decoder can be modified as shown in the circuit of FIGURE 4 to form a InCycler. This circuit has 4 bias voltages VI, V2,V3, and V4. Depending on the input voltage the transistors are triggered similar to the decoder. The table below illustrates.

A InCycler can also be realized using switches (mit gate), along with a decoder. The outputs are connected to four different voltages as shown in FIGURE 5, resulting in a HCycler for the example below where:

• VI bias voltage (e.g. level 2 or 3v)

• V2 bias voltage (e.g. level 1 or 1.5v)

• V3 bias voltage (e.g. level 0 or Ov) • V4 bias voltage (e.g. level 3 or 4.5v)

The truth table for a HCycler is as follows:

An Encoder functions essentially as an inverse decoder. An encoder accepts inputs from a decoder output and converts the decoder output into an n base mit signal. Decoder and encoder combinations are useful in any number of applications including, but not limited to, audio and video signals.

Mul tiplexer A multiplexer is a data selector that route multiple input mit data across a single output line based on the selection input. The selection inputs switch the input signals on the output line.

Selection input

Mit MUX

Inputs , .,, , Output

Demultiplexer

A demultiplexer takes the input from a single line and selection input (s) and converts it into n mit output. A demultiplexer is the inverse of an multiplexer.

AND Ga te

An AND gate has two mit inputs, II and 12. The inputs are level converted, using an appropriate level converter, from a base n signal to a binary signal. The output of the level converter is connected to a combination of binary AND gates. The output of the binary AND gates is then converted from binary to a base n signal . The same can be achieved using a matrix switch by mathematically arriving at the output of the mit AND gate.

The table below is an example of a base 4 2-mit input AND gate. Inputs II and 12 are converted into binary format using an Base 4 to binary level converter. The outputs of the two level converters (Bil, Bi2, Bi3, and Bi4) are connected to two binary AND gates. AND gate 1 has the inputs Bil and Bi3, while Bi2 and Bi4 are inputs for AND gate 2. The output of the binary AND gates are Bol and Bo2. Bol and Bo2 are connected to a binary to base 4 level converter to get output 0.

NOT Ga te A NOT gate has one input and one output. The input is level converted to a binary signal and inverted using a binary NOT gate. The output is converted back to base n it signal . The output is exactly same as an mit inverter .

OR Ga te

An OR gate has two mit inputs, II and 12. The inputs are level converted, using an appropriate level converter, from a base n to binary signal. The output of a decoder is connected to a combination of binary OR gates. The output is converted from the binary signal to a base n signal.

The same can be achieved using a matrix switch by mathematically arriving at the output of the mit OR gate. The table below is an example of a base 4 2-mit input OR gate. Inputs II and 12 are converted into a binary format using an base 4 to binary level converter. The outputs of the two level converters (Bil, Bi2, Bi3, and Bi4) are connected to two binary OR gates. OR gate 1 has the inputs Bil and Bi3, while Bi2 and Bi4 are inputs for OR gate 2. The output of the binary OR gates are Bol and Bo2 which are connected to a binary to base 4 level converter to obtain output 0.

In general, most any logic gate can be implemented by first converting mit data to binary data using an appropriate level converter. Next, the binary data is applied to binary logic gates and the output of the binary logic gates is then converted back to mit data again using an appropriate level converter.

The foregoing gate descriptions have been illustrated using mit inputs. These gates may be used in parallel to form gates that perform "myte" logic functions. Some examples are illustrated below. n Myte Decoder

A 2 - 16 base 4 discrete decoder logic table is shown below.

A decoder has many applications in a discrete computer system ranging from a matrix switch to address switches for memory.

n Myte Counter

A counter has a clock signal as its input and is illustrated in FIGURE 6. One, two, and three mit counters are illustrated in FIGURE 6. An output voltage increments to the next level with each clock pulse. Like a cyclic counter, the voltage increments to the next level at each clock cycle. When the M-1 level of the clock is reached of an M base discrete system, the counter starts from the zero level and the higher significant mit is incremented until the most significant mit has reached the M-1 level. The counter then resets and starts from zero again. The counter includes a data bus for setting the counter at a particular count and starting incrementing from that count .

n Myte Level converter

A level converter changes the base of a multi-level discrete signal from one level to another. FIGURE 7 illustrates a level converter for converting from a base 4 mit system to a binary system.

Each mit in a base 4 system represents 2 bits of a binary system as illustrated in the table below.

From the decoder of FIGURE 3, the outputs are

If a bias voltage of 5v (a "1" in the binary system) is connected to OUT 3 and OUT 1, which will be bit 0, and bit 1 is turned on using a switch when either OUT 1 or OUT 2 are on. Consider this as a block with 1 mit base 4 input and 2 bit binary output. These blocks can be strung in parallel to convert a multi-myte base 4 system to a multi byte binary system.

The switches 702A, 702B, 702C, 702D are all connected to a single bias (Vcc) since it is a conversion to a binary system. Variations of FIGURE 7 can be used to level convert bases of other systems.

For a base 4 system to be converted to a base 8 system, three mits of input from a base 4 system are converted to two mits of output in a base 8 system. This is mathematically proved by the following:

• 4³ -1 = 63 (maximum number represented using a base 4,

3-mit system) • 8² -1 = 63 (maximum number represented using a base 8,

2-mit system)

Thus, 1*4 mits of a base 4 system represent 1 mit of a base 8 system. This can be repeated multiple times to convert more than 3 mits of base 4 to base 8. Alternatively, a level converter can also be realized by using a InCycler for the destination base system. The output of the input base system is first decoded, then fed to a switch based cycler.

n Myte Register

A register is a series of flip-flops in which the input and output data are parallel. A register is used to store data and is a type of memory device. The storage capacity of a register is in mits.

n Myte Shift Register

A shift register, illustrated in FIGURE 8, allows the movement of data from one stage to another stage upon the application of a clock pulse. There are three types of shift registers, serial in /serial out, parallel in /serial out, and serial in / parallel out. Shift registers can be cyclic or noncyclic depending on the serial output connected to the serial input. The shift of the registers can be left or right. In a shift register, with every clock cycle, the level of the previous level-holder is copied or set in the level-holder. For example, the sequence below demonstrates two cycles of a left to right cyclic shift register. The values shown are arbitrary.

| 2 | 2 | 4 | 3 | l | 2 | 0 1 | start

| l | 2 | 2 | 4 | 3 | l | 2 | 0 | 1^st clock cycle

0 1 | 2 2 4 3 | 1 | 2 | 2^nd clock cycle

If an output is connected to the rightmost mit, then the signal on a single output line for every cycle represents the mits from the shift register serially. If the individual registers are loaded in parallel, and output in serial, it is called a parallel in / serial out shift register.

Consider a shift register that is not cyclic, that is, the input of the first level-holder is connected to an input line. The input line has a signal that is serially output from another serial out shift register. The clocks of both registers need to be synchronized. When this serial signal is presented during each clock cycle the register reads the serial input. If this is done eight times in the above example, the whole shift register becomes full. This can be output in parallel called a serial in / parallel out shift register or output serially as a serial in / serial out register. A parallel in / parallel out shift register is a normal register. The shift can be left to right or right to left. FIGURE 8 shows the number "10231301" (left side signal) input in a left to right shift register. It takes 8 cycles to completely load the register. The serial output after 8 clock cycles is "10231301" (right side signal) . The parallel output is during a single clock cycle and is still the same number "10231301" (lower side signal) .

n Myte Adder An example of an 4-mit adder { myte) is shown in FIGURE 9. Input mits A3,A2,A1,A0 are added to mits B3,B2,B1,B0 respectively yielding outputs D3,D2,D1,D0 and carry outputs C3,C2,C1,C0. This ripple adder takes the carry of the previous stage and adds it with the next as input. A look ahead carry can also be implemented using mit gates .

n Myte Subtractor

An n-myte subtractor is similar to an adder. A number of subtractors are linked in parallel to subtract a number represented by n-mytes with another n-myte number where the output is an n-myte number. Instead of a carry, a borrow is used. An M-1 compliment adder can be used for subtractions in parallel.

n Myte Mul tiplier

A plurality of multipliers can be linked in parallel. A carry is added to the output of next stage. Look ahead carries can make n-myte multipliers faster and more efficient if the multiplier is implemented using matrix switches linked in parallel.

n Myte Divider

A plurality of dividers can be linked together as per the "Chinese Remainder Theorem". This type of implementation can be substituted using matrix switches in parallel. n Myte Logic Ga tes

Logic gates include, but are not limited to, AND, OR, NOT gates. These binary gates can be implemented using a level converter output after the operation and converted back. Another other option is to compare these mathematically .

Multi-level memory is arranged as in a binary digital computer system. Data is stored in a group of memory cells similar to registers. The discrete computer system' s word length determines the number of cells that are addressed together to form a word. A number of words of memory that can be independently addressed is called an array of memory. A decoder is used to decode the multi- level addresses and activate a word of memory. A write instruction/operation loads the data contained at a specified address onto the data bus and when the address is selected the data is set or written in the word. In a read operation, an address is provided over the address bus and decoded. The individual memory word is selected and the memory contents (in mits) are loaded onto the data bus. The capacity of the memory is proportionate to the number of words in the memory array. Using binary memory in a vertical stack, as illustrated in FIGURE 10, is one method of implementing multi-level discrete memory for a discrete computer system. The stacked word length uses the same number of memory cells needed to represent data when the same word is converted to binary and stored in a binary digital computer. Multi-level memories can use phase transitions of quantum physics to store the memory as DRAMs.

A bus connects the CPU with various I/O devices and memory devices associated with the computer system. An address bus is used to address memory that will be accessed by the CPU. A data bus provides data to and from the CPU to other I/O devices and memory. In a binary digital computer system, a bus is comprised of the same number of wires as the bit size of the computer. The number of bits in the address bus are equal to the number of address bus wires (lines or connections) . In a discrete computer the bus size is equal to the number of mits of the data bus of the discrete computer system. Bus speed is greatly enhanced, however, using mits as compared to bits .

A bus can be a single optic fiber or any other high speed line. A single fiber optic line can carry mits of data on the bus to the CPU, the I/O devices, or memory. At the end device, bus data can be converted into parallel lines (mits) and used accordingly. The base level of a bus need not be the same base level as other devices on the line. A level converter can be used to convert bus mits of different bases into the base level utilized by an end device.

A network is comprised of two or more computers communicating over a network communication channel. The communication channel can be a wire line, fiber optic, or electromagnetic (e.g., RF wireless). Data can be transferred on the line using analog, binary digital, or discrete formats. The analog signal is the oldest form, used in telephony for instance. A digital circuit using a digital shift register converts an I/O bus signal from a parallel to a serial signal. This signal is received at a receiver and converted back to a parallel signal and used by the computer appropriately. An electrical communication line is comprised of two wires to carry the signal. A fiber optic channel is comprised of a single fiber optic cable. In a discrete network, fiber optic cables are most commonly used today since fiber optic cables have multiple levels with which to carry data. Fiber optic cables can carry data at significantly higher speeds than traditional wire cables.

In a fiber optic cable or for RF signal transmission, the discrete levels are not voltage levels. Rather, they are different frequencies for a clock cycle period. Each frequency represents a different level of the discrete signal. 128 to 1000 level channels can easily be constructed by using frequencies to represent the levels of a discrete signal.

The base level of a discrete computer system is a design choice. An even numbered base level allows a level converter to map existing binary digital computer system data to a multi-level discrete system fairly easily. An odd numbered base discrete computer system can be useful, but a more complex level converter will be required to convert from a binary format to multi-level odd base discrete system.

To further illustrate the present invention, an example in the form of a simple computer program is presented. The simple program adds the contents of two registers and stores the result in a third register. First, the program is described in terms of a binary digital computer. Then, the program is described in terms of a base four (4) discrete computer system. Lastly, the program is described in terms of a base eight (8) discrete computer system. The purpose of describing the same program in each form is to illustrate the differences between binary digital computer systems and multi-level discrete computer systems. To recap, the main elements of a processor (CPU) include a clock for providing a predefined frequency of pulses to a CPU. The CPU then synchronizes all of its activities on one of the edges of the clock signal. Another element is a program counter which is a register that increments its contents to the next instruction. The increment is either to go to the next instruction or is changed by a branch instruction to go elsewhere to find the next instruction. A program counter feeds the instruction register. An instruction register contains the next instruction to be executed in the processor. The next instruction is fetched from the computer' s main memory unit .

A decoder unit decodes or translates machine language instructions into simple switch inputs. The arithmetic logic unit (ALU) and the registers interpret the decoded instruction (e.g., move contents of register A to register B) . The instruction is merely a number that is decoded into three switch inputs, one for register A, one for register B and the third for the connection.

A control unit essentially controls each step in the instruction. Based on instructions from the decoder unit, the control unit creates control signals to switch different parts of the arithmetic logic unit (ALU) and the registers. The clock synchronizes the control signals. At each clock cycle a set of arithmetic logic units and registers are switched on or off. Critical is when to switch, how to switch, what to switch, and what to do with the result, all of which are predefined steps. The steps are wired in the control unit and include, for instance, read from memory, write to memory, read from register, etc. These steps are combined to form more complex instruction sets in CISC machines. In RISC (reduced instruction sets) machines, the instructions are merely read, write, etc.

The ALU is the last stage of processing in the CPU. The ALU performs commands such as add, subtract, multiply, and divide, etc. The ALU also knows reads logic commands such as OR, AND, comparison, or NOT, etc. Control signals from the control unit command the ALU with respect to which unit operates on which set of inputs and where output data is to be stored. Registers are used to complete an instruction.

Registers are temporary storage areas for data that are used by the ALU to complete instructions the control unit has requested. Data is received from a data register, from main memory, or from the control unit and is stored in special locations within the registers. Registers are used to obtain data required by an instruction so that the units of the ALU can be switched in the particular sequence of the instruction.

A Bus Unit is the means by which instructions flow in and out of the microprocessor from the computer's main memory or I/O devices. The bus unit is comprised of an address, data, and control bus. An address bus is used by the CPU to address each memory unit. A data bus is used to pull and push the contents from and to the memory units addressed by the address bus. A control bus switches memory to read or write mode as per the CPU based on the instruction.

The following is a simple program to add the contents of two (2) registers and store the result in a third register. It is written for a binary digital computer system. Address Mnemonic Instruction

0000 0000 start

0000 0100 move contents of address 1001 0000 to accumulator register

0000 1000 move contents of address 1100 0000 to register B

0000 1100 add register B and register A and store results in register A

0001 0000 move results from register A to address 1111 0000

0001 0011 end

When the program is started, the address 0000 0000 is loaded into the program counter and its contents are stored in the instruction register. The instruction is loaded from memory location 0000 0000 by putting the address 0000 0000 onto the address bus. The control bus is switched to read mode. The memory unit switches the memory at address 0000 0000. The contents at address 0000 0000 are now on the data bus. The instruction register is also switched onto the data bus and the register latches to the contents of the data bus.

In the next cycle the instruction register and memory are disconnected from the data bus. The instruction register sends the data to a decoder unit, the correct decoded binary code is then sent to the control unit. The next instruction is loaded to the instruction register, the decoder detects the instruction and sends the decoder output to the control unit. Register A is connected to the data bus to receive data and the address 1001 0000 is loaded onto the address bus. During the next clock cycle the memory detects the address and loads the contents of address 1001 0000 on the data bus. During the next cycle, register A holds the contents of address 1001 0000. The data and address buses are then disconnected from the registers.

The next instruction is then loaded into the instruction register. The same process continues but the contents of address 1100 0000 is stored in register B. During the next instruction the control unit switches register A and register B to be the inputs of an adder gate in the ALU and the output is connected to register A. During the first clock cycle the contents of registers A and B are placed on the input lines of the adder. The next three cycles permit the adder to add the contents of registers A and B and place the result on the output of the adder. The output data is then placed on the Adder output as a switch and a latch holds the output until register A reads the data and holds it. The connections between the adder and the registers are then disabled.

The next instruction moves the results from register A to the desired memory location, by first loading the contents of register A on the data bus and then loading the address on the address bus. The control bus is then switched to write mode. The memory detects it and places the results in memory location 1111 0000.

During the end instruction, the program counter is released. The main operating system (0/S) program takes control and looks for the next program or waits in a loop until the next program is executed.

The simple program to add the contents of two (2) registers and store the result in a third register is now described for base four (4) multi-level discrete computer system.

When the program is started, the address 0000 (base 4) is loaded into the program counter and its contents are stored in the instruction register. The instruction is loaded from memory location 0000 by putting the address 0000 onto the address bus. The control bus is switched to read mode. The memory unit switches the memory at address 0000. The contents at address 0000 are now on the data bus. The instruction register is also switched onto the data bus and the register latches to the contents of the data bus .

In the next cycle the instruction register and memory are disconnected from the data bus. The instruction register sends the data to a decoder unit, the correct decoded binary code is then sent to the control unit. This instruction, in binary, takes 4 bytes of memory. In a base four (4) system, half the size is required. Therefore, the address is incremented by two rather than four.

The next instruction is loaded to the instruction register, the decoder detects the instruction and sends the decoder output to the control unit. Register A is connected to the data bus to receive data and the address 2100 is loaded onto the address bus. During the next clock cycle the memory detects the address and loads the contents of address 2100 on the data bus. During the next cycle, register A holds the contents of address 2100. The data and address buses are then disconnected from the registers.

The next instruction is then loaded into the instruction register. The same process continues but the contents of address 3000 is stored in register B.

During the next instruction the control unit switches register A and register B to be the inputs of an adder gate in the ALU and the output is connected to register A. During the first clock cycle the contents of registers A and B are placed on the input lines of the adder. The next three cycles permit the adder to add the contents of registers A and B and place the result on the output of the adder. The output data is then placed on the Adder output as a switch and a latch holds the output until register A reads the data and holds it. The connections between the adder and the registers are then disabled.

The next instruction moves the results from register A to the desired memory location, by first loading the contents of register A on the data bus and then loading the address on the address bus. The control bus is then switched to write mode. The memory detects it and places the results in memory location 3300.

During the end instruction, the program counter is released. The main operating system (O/S) program takes control and looks for the next program or waits in a loop until the next program is executed.

Lastly, the simple program to add the contents of two (2) registers and store the result in a third register is written for a base eight (8) multi-level discrete computer system.

When the program is started, the address 000 (base 8) is loaded into the program counter and its contents are stored in the instruction register. The instruction is loaded from memory location 000 by putting the address 000 onto the address bus. The control bus is switched to read mode. The memory unit switches the memory at address 000. The contents at address 000 are now on the data bus. The instruction register is also switched onto the data bus and the register latches to the contents of the data bus. This instruction, in binary, takes 4 bytes of memory. In a base eight (8) system, half the size is required. Therefore, the address is incremented by two rather than eight.

In the next cycle the instruction register and memory are disconnected from the data bus. The instruction register sends the data to a decoder unit, the correct decoded binary code is then sent to the control unit. The next instruction is loaded to the instruction register, the decoder detects the instruction and sends the decoder output to the control unit. Register A is connected to the data bus to receive data and the address 220 is loaded onto the address bus. During the next clock cycle the memory detects the address and loads the contents of address 220 on the data bus. During the next cycle, register A holds the contents of address 220. The data and address buses are then disconnected from the registers.

The next instruction is then loaded into the instruction register. The same process continues but the contents of address 300 is stored in register B.

The next instruction moves the results from register A to the desired memory location, by first loading the contents of register A on the data bus and then loading the address on the address bus. The control bus is then switched to write mode. The memory detects it and places the results in memory location 360.

The foregoing example of adding the contents of two registers and storing the result in a third register is a simple one. However, those of ordinary skill in the art could readily and easily extend the foregoing using the full range of ALU functionality described herein to create much more complex multi-level discrete computer system programs regardless of the base system. Multiple central processing units can be operatively connected to perform parallel processing of mit data to substantially increase computing power, speed, and efficiency. Parallel computers use more than one CPU to process the instructions. The CPU's can be connected in the form of a symmetric multi-processor (SMP) configuration architecture or massively parallel processing (MPP) combinations. The CPU's of the discrete computer system of the present invention can be connected to share buses, memory or other resources in order to achieve higher throughput than a single CPU.

In the following claims, any means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims

CLAIMS :

1. A multi-level discrete computer system comprising: a processing unit for processing mits of data; memory means for storing mits of data; input means for receiving mits of data from external devices and forwarding said mits of data to said central processing unit; output means for receiving mits of data from said central processing unit and forwarding said mits of data to external devices; and bus lines carrying mits of data among said central processing unit, memory means, input means, and output means .

2. The system of claim 1 wherein said central processing unit is comprised of: an arithmetic logic unit including logic gates for manipulating mits of data; a register unit for manipulating mits of data; and a control unit for manipulating mits of data.

3. The system of claim 1 further comprising: a level converter operatively connected to said central processing unit for converting mits of data of a first base level to mits of data of a second base level.

4. The system of claim 1 wherein multiple processing units are operatively connected to perform parallel processing.

A processing unit capable of processing mits of data comprising : an arithmetic logic unit including logic gates for manipulating mits of data; a register unit for manipulating mits of data; and a control unit for manipulating mits of data.

6. The processing unit of claim 5 further comprising: a level converter for converting mits of data of a first base level to mits of data of a second base level.

7. The processing unit of claim 5 wherein said mits of data are represented as voltage signals.

8. The processing unit of claim 5 wherein said mits of data are represented as light based frequency signals.

9. The processing unit of claim 5 wherein said mits of data are of a base n number system where n is an integer greater than 2.

10. The processing unit of claim 5 wherein said arithmetic logic unit includes a level detector gate.

11. The processing unit of claim 5 wherein said arithmetic logic unit includes a flip-flop gate.

12. The processing unit of claim 5 wherein said arithmetic logic unit includes an inverter gate.

13. The processing unit of claim 5 wherein said arithmetic logic unit includes a buffer gate.

14. The processing unit of claim 5 wherein said arithmetic logic unit includes a comparator gate.

15. The processing unit of claim 5 wherein said arithmetic logic unit includes a single mit input lncycler gate.

16. The processing unit of claim 5 wherein said arithmetic logic unit includes a dual mit input 2ncycler gate.

17. The processing unit of claim 5 wherein said arithmetic logic unit includes a noncycler gate.

18. The processing unit of claim 5 wherein said arithmetic logic unit includes a switch gate.

19. The processing unit of claim 5 wherein said arithmetic logic unit includes a matrix switch gate.

20. The processing unit of claim 5 wherein said arithmetic logic unit includes a mit adder gate.

21. The processing unit of claim 5 wherein said arithmetic logic unit includes a myte adder gate.

22. The processing unit of claim 5 wherein said arithmetic logic unit includes a mit subtractor gate.

23. The processing unit of claim 5 wherein said arithmetic logic unit includes a mit multiplier gate.

24. The processing unit of claim 5 wherein said arithmetic logic unit includes a mit divider gate.

25. The processing unit of claim 5 wherein said arithmetic logic unit includes a mit decoder gate.

26. The processing unit of claim 5 wherein said arithmetic logic unit includes an n myte counter gate.

27. The processing unit of claim 5 wherein said arithmetic logic unit includes an n myte shift register.

28. The processing unit of claim 5 wherein said arithmetic logic unit includes boolean logic gates.

29. A processing unit capable of processing mits of data comprising: means for receiving mits of data; means for processing mits of data; and means for outputting mits of data.