Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
  • H03M13/618—Shortening and extension of codes
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/13—Linear codes
  • H03M13/17—Burst error correction, e.g. error trapping, Fire codes
  • H03M13/175—Error trapping or Fire codes

Definitions

• the present invention relates to the field of error correction in numerical transmissions and in particular to a method and an apparatus for more efficient error correction with shortened Fire codes. This is particularly useful in control channels for GSM cellular telephony.
• Conventional high speed data communication systems commonly use cyclic error detection codes to detect and correct data received with transmission errors. These errors can be caused by the number of transmission disturbance types such as evanescence, channel noise, interference et cetera.
• One class of particularly well known cyclic codes used is known by the code name 'Fire' . These codes can be advantageously used for correction of transmission channel error bursts .
• An error burst is a long sequence of mistaken symbols included between the first and last mistaken bits in the transmitted word.
• a coded word or sequence r(x) received can be expressed as the sum of the correct sequence transmitted c(x) and the mistaken bit configuration e(x).
• r(x) can be considered a single polynomial, a single syndrome can be calculated therefrom by scrolling the received word in one direction and the errors can be corrected by scrolling the received word in the opposite direction. Correction is based on the consideration that with a certain number of cyclic scrolls of the word received it is possible to isolate the error burst in the n final bits of the syndrome.
• shortened Fire codes were introduced.
• the control channels are subject to dual coding, internal with rate convolution code (456, 228) and external with shortened Fire code (224,184).
• Decoding the shortened Fire code is effective for correcting an error burst less than or equal to 12 bits long. But this is not always sufficient.
• the general purpose of the present invention is to remedy the above mentioned shortcomings by making available a method and an apparatus for decoding numerical signals codified with Fire codes which would allow correction within a given block of even two error sequences to return the output errors to an acceptable value even with high interference on the transmission channel.
• a memory (218) memorizing a predetermined number of syndromes S generable in an error bust having pattern P of length k and position X within the signal, a calculation unit (211) receiving at input the received signal r(x) and calculating the corresponding syndrome S(x) , and
• a comparison unit (213) which verifies the status of the calculated syndrome bits and on the basis thereof emits towards a calculation and correction unit (217) a no error signal, main error burst presence, secondary burst error presence, with the calculation and correction unit (217) seeking among the syndromes memorized in the memory (218) the sequence of the first n bits of the syndrome S(x) and, if it finds it, correcting the secondary burst on the basis of the relative position X of the error and of the pattern P associated in the table and then correcting the primary burst.
• FIG 1 is a flowchart of the prior art error correction method with Fire code
• FIG 2 is a flowchart of the error correction method with Fire code provided in accordance with the innovative principles of the present invention
• FIG 3 is a more detailed flowchart of a part of the chart of FIG 2, - FIG 4 shows diagrammatically the possible relative position of two error bursts,
• FIG 5 shows a correlation table in accordance with the present invention
• FIG 6 shows a block diagram of an apparatus applying the method in accordance with the present invention.
• the shortened Fire code (224,184) employed in normal GSM transmissions is able to correct a single error burst (i.e. a sequence included between the first and last mistaken bits in a code word) at most 12 bits long.
• the Fire code is also able to detect but not correct the presence of error bursts longer than 12 bits.
• FIG 1 shows a flow diagram for error correction in accordance with the prior art.
• the 40 bit syndrome is made up of zeroes only is verified in 12. If it is, there are no errors in the received sequence and the correction procedure terminates correctly in 13. If on the contrary not all the 40 bits of the syndrome are zero it means that there are errors in the received sequence. In this latter case it is verified in 14 whether at least the first 28 bits of the syndrome are zero (i.e. the received signal contains at most 12 mistakes) which is the indispensable condition for application of the standard correction procedure with shortened Fire code. If the first 28 bits are zero, the errors (which are shown in the 12 not zero bits) are correctable by applying the standard correction method in block 16, a method well known to those skilled in the art and therefore not further described herein, to have the correct sequence at the output 17. If the first 28 bits of the syndrome are not all zeroes block 25 calculates the rotated syndrome to verify
• FIG 2 shows a flowchart similar to the one in FIG 1 but providing the method in accordance with the present invention.
• the method in accordance with the present invention is similar to the known standard method. Indeed, as may be seen in FIG 2, once the 224 bit sequence constituting the code word is received, the syndrome is calculated in block 111 and it is verified whether it is made up of zeroes only. If so, there are no errors in the received sequence and the correction procedure terminates normally in 113. If not all 40 bits of the syndrome are zero it is verified (block 114) whether at least the first 28 bits of the syndrome are zero, which is the indispensable condition for application of the normal correction procedure (block 116) and obtain therewith the correct sequence in the outlet 117.
• extended correction in accordance with the present invention also permits correcting a second burst of shorter length which we shall call secondary burst.
• short lengths is meant a length k shorter than the length of the primary burst.
• the extended correction block 118 receives in A the mistaken sequence (which can contain two error bursts: a primary and a secondary) and renders in B the sequence with the correct secondary burst error so that the primary burst error can be corrected by block 116.
• Block 118 also has an output C which is reached when an expected secondary burst proves to be outside the coded word, i.e. when the error sequence is not the one expected and therefore it is necessary to go on to the following syndrome rotation to then go back over the algorithm starting from the comparison 114.
• FIG 3 shows in greater detail operation of the extended correction block 118 in accordance with the present invention. Operation of this block is based on the consideration that for sufficiently small secondary error bursts of length k the number of possible syndromes because of this 'secondary' error is sufficiently small to enable advance calculation and memorization of all the possible syndromes associated with the respective error patterns and positions so as to be able to perform an exhaustive search among these possible secondary burst syndromes to check whether the sequence of the first 28 not zero bits of the syndrome calculated on the received sequence is found among the first 28 bits of one of the syndromes corresponding to the secondary burst of at most k bits .
• the syndrome is found in the table (look-up table) 120, we go on (block 122) to correction of the secondary burst on the basis of the pattern and the relative position of the error (associated in the table with the syndrome) and then the syndrome (block 124) is also corrected so as to reach point B with a new syndrome which has its first 28 bits zero. This permits correcting the primary burst error in 116 and coming out in 117 with the correct word.
• the syndromes generated by the sequence of k mistaken bits are thus (432-2k) (2 k -l) and the complexity in the calculation thereof depends accordingly on 2 k ;k is to be selected according to the memory available in the receiver for table memorization.
• Naturally k can be increased by increasing the performance of the hardware used.
• FIG 5 shows diagrammatically the structure of table 120.
• n s is the number of possible syndromes generable from a sequence of k mistaken bits.
• the first column of the table are memorized all the possible syndromes S, in the second column is memorized the associated error pattern P of k bits for each of these, and in the third column is memorized the associated position X of the error.
• the table it suffices to consider all the possible positions and error patterns and calculate the relative syndrome for each combination. For convenience and speed of search, in the table it is advantageous to memorize the syndromes ordered on the basis of their first 28 bits.
• correction of the syndrome is performed in block 124 by merely adding the present syndrome (at point A) to the syndrome of the table.
• the result of the sum is a new syndrome with the first 28 bits zero (since by definition the table syndrome was the one associated with the error which had produced the first 28 not zero bits in the syndrome which had been calculated on the signal and possibly rotated) . Since at outlet B of block 118 the syndrome certainly has the first 28 bits zero, it is possible to return downstream from the control block 114 to avoid a useless verification.
• FIG 5 shows a block diagram of a receiving apparatus employing the method of the present invention.
• This apparatus receives the sequence r(x) which is memorized in the memory block 210.
• a calculating block 211 for the syndrome calculates the syndrome S(x) and memorizes it in memory block 212.
• a comparison block 213 verifies whether all the first 40 bits or only the first 28 bits are zero and emits corresponding signals 214, 215 and 216 indicating respectively whether no correction is required (first 40 bits zero), correction of a secondary burst is required (first 28 bits other than zero) or whether correction of the primary burst (first 28 bits zero) is required.
• the calculating unit 217 (which memorizes the look-up table of the possible syndromes in the memory 218) performs the required corrections and if necessary recycles the syndrome until the correct signal g(x) is obtained at output.
• DSP Digital Signal Processor

Landscapes

• Physics & Mathematics (AREA)
• Probability & Statistics with Applications (AREA)
• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Error Detection And Correction (AREA)
• Detection And Prevention Of Errors In Transmission (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (2)

Family

ID=11383463

Family Applications (1)

Country Status (5)

Families Citing this family (4)

Citations (3)

• 1999
  • 1999-07-30 IT IT1999MI001711A patent/IT1313315B1/it active
• 2000
  • 2000-07-28 CN CN00813570.3A patent/CN1399815A/zh active Pending
  • 2000-07-28 AU AU62782/00A patent/AU6278200A/en not_active Abandoned
  • 2000-07-28 EP EP00949416A patent/EP1254519A2/en not_active Withdrawn
  • 2000-07-28 WO PCT/EP2000/007308 patent/WO2001010040A2/en not_active Application Discontinuation

Patent Citations (3)

Also Published As

Similar Documents

Legal Events