WO2001006769A1 - Spurious frequencies attenuation for a dc reference voltage - Google Patents
Spurious frequencies attenuation for a dc reference voltage Download PDFInfo
- Publication number
- WO2001006769A1 WO2001006769A1 PCT/US2000/019257 US0019257W WO0106769A1 WO 2001006769 A1 WO2001006769 A1 WO 2001006769A1 US 0019257 W US0019257 W US 0019257W WO 0106769 A1 WO0106769 A1 WO 0106769A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- capacitor
- luminance
- coupled
- analog
- gain control
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
- H04N21/4263—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners
- H04N21/42638—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners involving a hybrid front-end, e.g. analog and digital tuners
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/52—Automatic gain control
Definitions
- the present invention relates to decoders in televisions for decoding received analog audio and video signals or transmissions and, more particularly, to an automatic gain control circuit for a decoder in a television for decoding received analog audio and video signals or transmissions.
- Televisions and other similar devices must now be able to receive, decode, and process analog and digital audio and video signals or transmissions. Because of the complexity of modern televisions caused by digital television signals and related processing, and analog television signal processing, many of the capabilities and functions thereof are performed by specialized digital integrated circuits (ICs). Advantageously, it is also preferable to manipulate/process the television signal in the digital domain regardless of whether the original received television signal is analog or digital.
- ICs digital integrated circuits
- decoders and digitizers aid in the processing of the digital and analog television signals.
- One type of IC that is used in televisions for processing analog television signals is a video decoder.
- the video decoder IC After processing of the analog television signal the video decoder IC generally digitizes the component signals for further processing. However, during processing of the analog signal, it is necessary to provide luminance signal DC restoration.
- the H P81 1 7 Video Decoder is one type of video decoder that accepts incoming analog NTSC or PAL television signals, processes the analog television signal, digitizes the signals, and then processes/manipulates the digital signals.
- the HMP 81 1 7 is particularly designed to decode baseband composite or S-video NTSC and PAL signals. Other functions are also supported.
- analog signal processing includes the restoration of a luminance signal (luminance signal restoration).
- luminance signal restoration is a necessary step of television signal processing.
- a luminance control terminal or pin (LCAP) is furnished to provide a voltage to offset the sync tip of the luminance circuitry to a lower reference of an internal A/D converter. It is recommended by the manufacturer of the HMP81 1 7 to couple a single storage capacitor of a given value to the LCAP pin. Such is typical of video decoders for analog signals.
- the present invention comprises an automatic gain control network or circuit for luminance signal restoration in an analog television signal video decoder.
- the video decoder is preferably an integrated circuit (IC) that receives the analog video television signal or transmission.
- the present invention comprises a television apparatus that includes processing circuitry adapted to receive an analog television signal, a video decoder coupled to the processing circuitry and adapted to process the analog television signal, the video decoder adapted to provide luminance signal restoration and configured with a luminance voltage offset reference terminal adapted to aid in the luminance signal restoration, and an automatic gain control network coupled to the luminance voltage offset terminal.
- the present invention comprises an automatic gain control network for luminance restoration circuitry in a television apparatus, wherein the television is adapted to receive analog television signals, and includes processing circuitry and a video decoder for the analog television signals, the video decoder having a luminance restoration terminal in communication with the luminance restoration circuitry.
- the automatic gain control network for the luminance restoration circuitry includes, a first circuit branch, a second circuit branch, and a third circuit branch. The first, second, and third branches being situated in parallel.
- the present invention comprises an automatic gain control network for a television apparatus, wherein the television apparatus is adapted to receive analog television signals, has a signal decoding integrated circuit, with the signal decoding integrated circuit having luminance signal restoration capabilities and a luminance voltage offset terminal.
- the automatic gain control network includes a first circuit branch configured to attenuate a first frequency, a second circuit branch configured to attenuate a second frequency, and a third circuit branch configured to attenuate a third frequency.
- Fig. 1 is a block diagram of an exemplary system in which the present invention is utilized
- Fig. 2 is a diagram of an exemplary television apparatus circuit as used in the system of Fig. 1 incorporating the principles of the present invention.
- Fig. 3 is a diagram of an exemplary automatic gain control circuit as used in the television apparatus circuit of Fig. 2.
- FIG. 1 there is shown a block diagram of a system, generally designated 1 0, which may utilize the present invention.
- the system 1 0 includes a television apparatus that may or may not include a monitor or other similar display device (collectively "television apparatus") generally designated 1 2.
- the television apparatus 1 2 is adapted through appropriate circuitry, software, and/or other components to decode and process digitally modulated analog audio and video television signals or transmissions ("digital television signals") from a Direct Broadcast Satellite (DBS) system 1 8 as received via a link or line 20.
- DBS Direct Broadcast Satellite
- Such signals may be digitally modulated using the QPSK (Quadrature Phase Shift Keying) format.
- the television apparatus 1 2 is also adapted through appropriate circuitry, software, and/or other components to decode and process digital television signals from terrestrial Digital Television (DTV) antenna 1 4 as received via a link or line 1 6, such as ATSC DTV.
- DTV Digital Television
- Such signals may be digitally modulated using VSB (Vestigal SideBand).
- the television apparatus 1 2 is also adapted through appropriate circuitry, software, and/or other components, to process analog audio and video television signals ("analog television signals") from a terrestrial analog antenna 22 as received via a link or line 24, as well as analog television signals from a CATV system 26 via a link or line 28. Such processing typically includes digitizing the video and/or audio signals through appropriate circuitry, software, and/or other components. Digital television signals from the CATV system 26 are also decoded and processed as indicated above. It should be appreciated that the television apparatus 1 2 is adapted to receive and process analog and/or digital television signals from sources other than that shown.
- the television apparatus 1 2 may be a model DTC 1 00, from Thomson Consumer Electronics, Inc. of Indianapolis, Indiana.
- the television apparatus 1 2 typically includes appropriate circuitry, software, and other components to support/provide a display, an integral control system, a user-interface and on-screen display (OSD) functionality.
- OSD on-screen display
- the television apparatus 1 2 may take other forms and have additional capabilities and/or functionality other than those shown and/or discussed through appropriate circuitry, software, and/or other components.
- Fig. 2 there is shown a block diagram of at least some of the various components of the DTC 100 television apparatus 1 2.
- the DTC 1 00 television apparatus 1 2 is adapted through appropriate circuitry, software, and/or other components, to receive and process digital television signals and analog television signals.
- the various blocks and interconnections depicted in Fig. 2 are exemplary of a television capable utilizing analog and digital television signals. Thus, variations in the interconnections and components may vary.
- the television apparatus 1 2 includes a DSS tuner/IF converter 30 that is adapted to receive a digital television signal (audio, video, and VBI/other) via line 20, allows tuning to the various channels of the digital television signal, converts the digital television signal into an Intermediate Frequency (IF), and sends the IF digital television signal (here shown as QPSK modulated) to a DSS link 32.
- the DSS link 32 demodulates the IF digital television signal and forwards the resulting digital television signal to a link multiplexer (MUX) 34.
- the link MUX 34 selectively sends the digital television signal to an ARM transport 36.
- the ARM transport 36 extracts a digital audio signal that is sent to an MPEG/AC-3 audio decoder 38.
- the audio decoder 38 decodes the digital audio signal, and sends the decoded digital audio signal to a digital to analog (D/A) converter 44.
- the D/A converter 44 sends the resulting analog audio signal to an audio processor 46 which send the process analog audio signal to audio amps 48 that are connected to audio speakers.
- the ARM transport 36 also extracts a digital video signal that is sent to the decoder 50.
- the decoder 50 provides necessary MPEG circuitry and/or software to decode the digital video signal.
- the decoded digital video signal is sent to a digital to analog (D/A) converter and filter 52 to provide an analog television signal for further processing before being forwarded to the display.
- D/A digital to analog
- the television apparatus 1 2 also includes a High Definition (HD)/NTSC tuner/IF converter and splitter 40 that receives an HD digital television signal (audio, video, and VBI/other) from the terrestrial digital antenna 1 4 via line 1 6, allows tuning to the various channels of the HD digital television signal, converts the HD digital television signal into an Intermediate Frequency (IF), and sends the HD IF digital television signal (here shown as VSB modulated) to an HDTV link 42.
- the HDTV link 42 demodulates the HD IF digital television signal and forwards the resulting digital signal to a link multiplexer (MUX) 34.
- the link MUX 34 selectively sends the digital signal to an ARM transport 36.
- the ARM transport 36 extracts a digital audio signal that is sent to an MPEG/AC-3 audio decoder 38.
- the audio decoder 38 decodes the digital audio signal, and sends the decoded digital audio signal to a digital to analog (D/A) converter 44.
- the D/A converter 44 sends the resulting analog audio signal to an audio processor 46 which send the process analog audio signal to audio amps 48 that are connected to audio speakers.
- the ARM transport 36 also extracts a digital video signal that is sent to the decoder 50.
- the decoder 50 provides necessary MPEG circuitry and/or software to decode the digital video signal.
- the decoded digital video signal is sent to a digital to analog (D/A) converter and filter 52 to provide an analog television signal for further processing before being forwarded to the display.
- the High Definition (HD)/NTSC tuner/IF converter and splitter 40 also receives digital television signals from the digital cable source 26 via line 28 and processes them in the same manner as for the terrestrial digital television signals. Additionally, the High Definition (HD)/NTSC tuner/IF converter and splitter 40 provides PIP (Picture-ln-Picture) capabilities. The High Definition (HD)/NTSC tuner/IF converter and splitter 40 also receives analog (NTSC) television signals from the terrestrial analog antenna 22 via line 24 and from the analog cable source 26 via line 28. The analog television signal is tuned by the tuner to a channel of the television signal and provides an IF analog television signal to an NTSC video switcher 56. The NTSC video switcher 56 provides the analog television signal to an initial comb filter/PIP and Chroma decoder 58 after which the analog television signal is sent to an NTSC YUV A/D converter 66 before being sent to the decoder 50.
- the television signal decoding integrated circuit (IC) or chip 50 performs combing, picture-in-picture (PIP), chroma decoding and digitizing, MPEG video decoding, NTSC and PAL video upconversion, OSD, and other functions.
- PIP picture-in-picture
- Such a decoding IC may be an HMP81 1 7 Video Decoder from Intersil Corporation of Palm Bay, Florida (formally Harris Semiconductor of Harris Corporation of Melbourne Florida), the Harris Semiconductor Data Sheet of January 1 999, File Number 4643, of which is specifically incorporated herein by reference.
- the decoding IC 50 is shown in a simplified block form.
- the decoding IC 50 also performs luminance signal DC restoration for the incoming analog television signal.
- the data sheet for the decoding IC 50 indicates that a storage capacitor should be attached to the LCAP (Luminance CAPacitor) pin 76 for providing luminance signal DC restoration.
- the value of the capacitor is stated to be 0.1 ⁇ F, and should be connected between the LCAP pin 76 and an AGND (Analog GrouND) pin (not shown).
- an automatic gain control (AGC) network or circuit 60 is connected to the LCAP pin 76 and ground.
- the LCAP voltage offsets a sync tip to the lower reference of an A/D converter (not shown) of the decoder 50.
- the AGC network 60 improves the quality of the resulting picture of the television apparatus 1 2 over a single storage capacitor by filtering out unwanted noise and oscillations.
- the AGC network 60 is a branched, parallel network having a node 62 and a common ground 64.
- a first leg or branch 70 situated between the node 62 and the ground 64, includes a capacitor C1 for filtering out first frequencies of noise and/or oscillations.
- the capacitor C1 may have a value of 820pF.
- a second leg or branch 80 situated between the node 62 and the ground 64 and parallel to the first leg 70, includes a resistor R1 in series with a capacitor C2.
- the second leg 70 filters out second frequencies of noise and/or oscillations.
- the resistor R1 may have a value of 750 ⁇ , while the capacitor C2 may have a value of 6.8 ⁇ F.
- the AGC 60 includes a third leg or branch 90 situated between the node 62 and the ground 64 and parallel to the first and second legs 70 and 80.
- the third leg 90 filters out third frequencies of noise and/or oscillations, and may have a value of 0.27 ⁇ F.
- capacitor and resistor values may deviate from those stated above, depending on the desired filtering characteristics of the AGC network 60.
- networks other than the branched network 60 shown in Fig. 3 may be used.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001511088A JP2003505944A (en) | 1999-07-16 | 2000-07-14 | Spurious frequency attenuation for DC reference voltage |
AU62146/00A AU6214600A (en) | 1999-07-16 | 2000-07-14 | Spurious frequencies attenuation for a dc reference voltage |
EP00948676A EP1197070A1 (en) | 1999-07-16 | 2000-07-14 | Spurious frequencies attenuation for a dc reference voltage |
KR1020027000285A KR20020035095A (en) | 1999-07-16 | 2000-07-14 | Spurious frequencies attenuation for a dc reference voltage |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14442699P | 1999-07-16 | 1999-07-16 | |
US60/144,426 | 1999-07-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001006769A1 true WO2001006769A1 (en) | 2001-01-25 |
WO2001006769A9 WO2001006769A9 (en) | 2002-09-06 |
Family
ID=22508552
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/019257 WO2001006769A1 (en) | 1999-07-16 | 2000-07-14 | Spurious frequencies attenuation for a dc reference voltage |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1197070A1 (en) |
JP (1) | JP2003505944A (en) |
KR (1) | KR20020035095A (en) |
CN (1) | CN1361976A (en) |
AU (1) | AU6214600A (en) |
WO (1) | WO2001006769A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5531348A (en) * | 1978-08-28 | 1980-03-05 | Toshiba Corp | Automatic frequency control circuit |
US5036292A (en) * | 1990-02-16 | 1991-07-30 | Audio Research Corporation | Decoupled electrolytic capacitor |
JPH0897641A (en) * | 1994-09-27 | 1996-04-12 | Fujitsu Ltd | High frequency module |
-
2000
- 2000-07-14 JP JP2001511088A patent/JP2003505944A/en not_active Withdrawn
- 2000-07-14 KR KR1020027000285A patent/KR20020035095A/en not_active Application Discontinuation
- 2000-07-14 AU AU62146/00A patent/AU6214600A/en not_active Abandoned
- 2000-07-14 WO PCT/US2000/019257 patent/WO2001006769A1/en not_active Application Discontinuation
- 2000-07-14 EP EP00948676A patent/EP1197070A1/en not_active Ceased
- 2000-07-14 CN CN00810403A patent/CN1361976A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5531348A (en) * | 1978-08-28 | 1980-03-05 | Toshiba Corp | Automatic frequency control circuit |
US5036292A (en) * | 1990-02-16 | 1991-07-30 | Audio Research Corporation | Decoupled electrolytic capacitor |
JPH0897641A (en) * | 1994-09-27 | 1996-04-12 | Fujitsu Ltd | High frequency module |
Non-Patent Citations (2)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 004, no. 063 (E - 010) 13 May 1980 (1980-05-13) * |
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 08 30 August 1996 (1996-08-30) * |
Also Published As
Publication number | Publication date |
---|---|
KR20020035095A (en) | 2002-05-09 |
WO2001006769A9 (en) | 2002-09-06 |
JP2003505944A (en) | 2003-02-12 |
CN1361976A (en) | 2002-07-31 |
EP1197070A1 (en) | 2002-04-17 |
AU6214600A (en) | 2001-02-05 |
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