WO2001006704A2 - Processeur de paquets - Google Patents

Processeur de paquets Download PDF

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Publication number
WO2001006704A2
WO2001006704A2 PCT/IL2000/000391 IL0000391W WO0106704A2 WO 2001006704 A2 WO2001006704 A2 WO 2001006704A2 IL 0000391 W IL0000391 W IL 0000391W WO 0106704 A2 WO0106704 A2 WO 0106704A2
Authority
WO
WIPO (PCT)
Prior art keywords
packet processor
data
bus
processor according
data stream
Prior art date
Application number
PCT/IL2000/000391
Other languages
English (en)
Other versions
WO2001006704A3 (fr
Inventor
Yuval Ben-Ze'ev
Joseph Lifshitz
Ran Kahn
Yeshayahu Mor
Original Assignee
Brightcom Technologies Ltd.
Coresma Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from IL13079699A external-priority patent/IL130796A/xx
Application filed by Brightcom Technologies Ltd., Coresma Ltd. filed Critical Brightcom Technologies Ltd.
Priority to AU55624/00A priority Critical patent/AU5562400A/en
Publication of WO2001006704A2 publication Critical patent/WO2001006704A2/fr
Publication of WO2001006704A3 publication Critical patent/WO2001006704A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/2801—Broadband local area networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements

Definitions

  • the invention generally relates to broadband communication systems for
  • the invention relates to a
  • modems are also used for conveying data over other types of mediums, for
  • Wireless and/or broad band are examples, over TV cables, or satellite links.
  • Wireless and/or broad band are examples, over TV cables, or satellite links.
  • modems are used, for example, in mobile communications, e.g., for
  • any modem comprises two main sections.
  • modulator-demodulator section is a mixed signal section for interfacing
  • the modem and the medium of transfer, for example, a telephone
  • modulator-demodulator the term “modulator-demodulator” is used, it should be understood to refer
  • modem the above-indicated section of the whole apparatus
  • modem apparatus commonly called modem
  • the second section of any modem is digital, generally referred to as the
  • the MAC module operates in the
  • the purpose of the MAC module is to manage
  • section of the modem and a host, in which the higher level layers are implemented, is generally located external to the modem casing, and vice
  • the MAC module is the heart of any modem.
  • the MAC module receives a
  • sequence of data stream from a host creates packets of data that are then
  • modems may need for assuring a reliable communication, i.e., for enabling
  • Access Control handles error correction, regulates the data flow, handles the
  • CMTS Code Modem Termination System
  • the MAC module should comply with
  • processor if such exists, takes control only at the packet level or IP
  • This configuration is rigid, and cannot be changed or
  • EP 789,468 discloses an adapter for wireless networks which provides for
  • adapter is suitable for lower end wireless LAN, and not for high data rate
  • modems such cable TV or satellite modems.
  • Processor for communications applications particularly for modems, which is capable of handling a high rate of data and performing the
  • the Packet Processor is
  • the Packet Processor is used as a MAC module for modem, an object of the
  • VLSI Integration Integration
  • the Packet Processor of the invention achieves these and other objects by
  • the present invention relates to a Packet Processor for a communication
  • each packet mainly comprises a header and a payload section
  • a receiving part comprising: (a) A receiving PHY interface by which a
  • receiving Tubular Bus conveying the data, while processed, in the direction
  • a transmitting part comprising:
  • processing units on the second Tubular Bus for providing a temporary
  • the first and second host interfaces are fabricated within a same
  • the module comprises two processing units in the receiving part
  • the processing unit closer to the demodulator handles the
  • CRC detecting and correcting errors
  • the processing unit closer to the host mainly handles the tasks of
  • the processing unit closer to the transmitting part
  • the host mainly handles the tasks of timing, controlling allocation, and
  • the processing unit closer to the modem mainly handles the task creation of the main CRC
  • each processing unit comprises a processor and a co-processor
  • the packet processor of the invention also has a connection to an
  • memory unit is made by a processing unit of the Packet Processor, via the
  • the Packet Processor also has a connection to one or more
  • One of said external devices is a storage unit, containing
  • the Packet Processor further comprises an External Bus
  • the communication is made by a processing unit of the packet
  • the Packet Processor further comprises a debugging unit for
  • the Packet Processor further comprises a DMA (Direct Memory
  • control unit for enabling internal transfer of data blocks between
  • the Packet Processor of the invention can be fabricated in a VLSI form.
  • the Packet Processor of the invention further comprises a Serial
  • Interface preferably programmable, for carrying out communication of the
  • ICU Interrupt Central Unit
  • the Packet Processor of the invention is particularly useful in modems, for example
  • a modem for TV cables For example, a modem for TV cables.
  • a particular use of the packet processor is
  • each processing unit can send one or more macro-instruction,
  • a macro instruction may be provided, for example, to a FIFO,
  • the second FIFO downstream the receiving bus further has an
  • said address filter which is used for comparing a
  • operations may be made based on said comparison, for example, an ignoring
  • each of the said processing units is a RISC processor. More
  • each processing unit is of the ARC type processor.
  • - Fig. 1 is a scheme showing the input/output buses of the packet
  • - Fig. 2 is a more expanded scheme of Fig. 1, showing the input/output
  • FIG. 3 shows a basic structure of a packet processor, according to one
  • - Fig. 4 shows a structure of a packet processor, according to another
  • FIG. 5 shows a structure of one processing unit in the packet processor of
  • FIG. 6 shows a structure of a packet processor, according to still another
  • Fig. 7 shows a structure of one processing unit in the packet processor of
  • the Packet Processor comprises a plurality of
  • processing units in which tasks are distributed in an efficient way, thereby
  • modems for example, modems for TV cables. Such modems are now
  • MCNS Multimedia
  • DVB Digital Video Broadcast
  • DAVIC Digital Audio Video
  • IEEE802.14 IEEE's Cable TV MAC and physical Protocol
  • FIG. 1 illustrates a basic structure of the Packet Processor, according to
  • the Packet Processor 1 is a Field
  • FPPA Programmable Processors Array
  • the processor array 2 includes plurality of processors, their associated
  • a host interface 3 connects the Packet Processor to a host.
  • the host is
  • a general purpose interface 7 connects the Packet Processor with
  • components such as, for example, a keyboard, a debugging processor, a
  • the General Purpose Bus 7 is a relatively slow
  • the External Bus Interface 4 connects the plurality of processing units of
  • the main memory unit is external to the main memory unit
  • each processing unit comprises an internal
  • Instruction Cache (Icache) containing a portion of the code needed for its
  • the PHY (physical) interface 6 connects the Packet Processor with the
  • a data stream is conveyed from the Packet Processor to the modulator for
  • the PHY interface 6 is generally a programmable state
  • FIG. 2 depicts in more detail the environment of a Packet Processor
  • Numeral 2 indicates the Packet Processor.
  • the PHY bus 16 connects the Packet Processor with the
  • modulator-demodulator section 10 of the modem generally a transceiver
  • the External bus 14 connects the
  • Processor 2 communicates with the host 21 via the host interface 3 and the
  • Bus 13 can be, for example, PCI, Internet, USB, Fire Wire, etc.
  • the modulator-demodulator unit of the modem The modulator-demodulator 10
  • the modulator-demodulator 10 receives the modulated data
  • the data is typically
  • CMTS Compact Modem Termination System
  • the processed data is transferred to the modulator-demodulator section 10 of the modem, which in turn modulates it with a carrier, and transmits the
  • the modulated data is transmitted to the cable network
  • CMTS complementary metal-oxide-semiconductor
  • the Packet Processor 1 comprises mainly
  • the receiving part (hereinafter, this will be referred to as the "receiving part"), and a second
  • Each of the said two parts mainly comprises at least one
  • processing-unit and preferably at least two processing-units.
  • This processing-unit frames the data
  • the receiving processing-unit/s 21 deframes the received data, detects
  • a second bus, the Ring Bus 44, is actually a
  • a diskette e.g., a diskette, a flush memory/EPROM, or a CD ROM to the
  • the Packet Processor 1 further comprises FIFO storage components 60, 61,
  • a control and ti ing unit 65 for timing and synchronizing the operation of the Packet
  • Fig. 4 depicts in even more detail the structure of the Packet Processor
  • transmitting parts 21 and 22 preferably comprise at least two
  • processing-units each. When two or more processing-units are used in each
  • the receiving part comprises a processing- unit- 1
  • the transmitting unit comprises
  • Bus of the Packet Processor of Fig. 4 is 9 data bits, and the width of the
  • Backbone Bus is 32 data bits.
  • the received data is preferably processed in two
  • the first phase done by Processing-unit- 1 51, includes the
  • Processing-unit-2 52 includes the handling
  • the transmitted data is preferably processed in two phases.
  • the first phase done by Processing-unit-3 53, includes the handling of the creation of the
  • the second phase done by processing-unit-4 54 includes the
  • processing-units of the Packet Processor 1 is optional, although preferable,
  • the Packet Processor is programmable, and the code according to the
  • invention is downloaded to the memory from an external source (not
  • Modifications to the code can be made at any time, and such
  • RISC-type Reduced Instruction Set Computer
  • Each processing unit also comprises an internal memory, which
  • SCRAM Scratch PAD RAM Memory
  • a first, input bus 91, to the RISC processing-unit is mainly used for receiving the data flow from a FIFO in the Tubular Bus.
  • a second, input bus 91, to the RISC processing-unit is mainly used for receiving the data flow from a FIFO in the Tubular Bus.
  • bus 93 of the processing-unit is bidirectional, and is used by the RISC
  • processing-unit to gain access to the Backbone Bus 44, in order, for example,
  • Ring Bus 44 peripheral components via the Ring Bus 44 is used, among other purposes,
  • the Packet Processor of the invention also comprises
  • FIFOs is to provide a sequential temporary storage for portions of the data
  • the said FIFOs enable each of the processing-units to
  • Each FIFO of the Packet Processor 1 is basically a RAM block for storing a
  • RAM block size is generally identical, but the RAM block size may differ from one
  • the size of the RAM block in different FIFOs ranges between
  • the FIFO sequentially receives words of data or
  • the macro instructions are
  • FIFO is empty or the processing-unit which should receive it is busy.
  • the Address Filter 82 comprises a
  • next data should be forwarded for a further processing or whether the data
  • An ignoring of data may occur, for example, when the
  • the Packet Processor 1 further comprises a timer 77, which administers the
  • the bus arbiter 79
  • the ICU (Interrupt Central Unit) 80 administers the ICU (Interrupt Central Unit) 80.
  • External Interface block 78 are also included in the Packet Processor of the
  • the module comprises a serial interface, preferably
  • Bus Arbiter 99 is used for arbitrating the usage of the external bus 97,which
  • downloading of the application code by which the module operates from (typically stored in an external storage means such as a diskette, a PROM,
  • the four processing-units 51, 52, 53, and 54 of the Packet Processor have
  • FIG. 5 depicts the structure of a preferred embodiment
  • processing-unit 100 comprises two main components, a RISC processor 101,
  • the processor to have a small silicon area, and to function in very short
  • processor 101 The number of the various tasks that are performed by processor 101
  • the internal memory 109 of the processing unit 100 comprises
  • an instruction cache memory section 110 preferably of the SRAM type, and
  • the internal memory 109 is generally sufficient for the operation of the
  • processing unit are performed by the co-processor 102, with the supervision
  • the co-processor is made via the Auxiliary Bus 105, having a width of
  • the processing unit 100 also comprises a clock unit
  • the Interrupt Control unit 116 which is a part of the ICU 80 of Fig. 4,
  • processing unit are indicated herein as numerals 120 and 121, respectively.
  • FIFOs are, in the case of processing unit 52, FIFO-2 71, and FIFO-3,
  • the RISC processor 101 has several internal registers other than the
  • Fig. 6 shows the structure of a Packet Processor according to a more
  • the Packet Processor of Figs 3, 4, and 5 comprises two main buses, a Tubular Bus 29, and a Backbone Bus 44.
  • the peripheral bus 444 is a memory mapped local bus through which each
  • processor communicates mainly with its associated coprocessor (primarily
  • peripheral buses 444 which are internal buses of the processing units, is to reduce transactions through the
  • the Tubular Bus 242 is preferably a 9-bit bus, and the Backbone Bus 244
  • External Access Bus 245 are preferably buses of 32-bits.
  • the Packet Processor of Fig. 6 comprises, as before, four processing units,
  • the Tubular Bus 243 is
  • demodulator of the modem flows, while being processed, to the host, and
  • the modulator and the demodulator are parts of the
  • Timer 277 provides control and timing signals to
  • the optional Debug Interface Unit is
  • the Interrupt Central Unit 280 The Interrupt Central Unit 280
  • the local host interface bus 299 reduces the load of the Backbone and the
  • the Packet Processor of Fig. 6 optionally further comprises a Serial
  • the Packet Processor of Fig. 6 comprises four processing units, 251,
  • the received data is preferably processed in two phases.
  • the first phase done by Processing-unit- 1 251, includes the processing of
  • Second phase done by Processing-unit-2 252, includes the handling of the
  • transmitted data is preferably processed in two phases.
  • the first phase is a first phase,
  • Processing-unit-3 253, includes the handling of the creation of the
  • the second phase done by processing-unit-4 254 includes the
  • the register file 295 comprises additional external registers for optional use
  • each processing unit may have a specific
  • processing units of the Packet Processor of Fig. 6 mainly comprises a
  • processing unit 251, the processor-1 and its associated co-processor, are indicated as block 361, and the sub-unit controller is indicated as block 261;
  • the processors are preferably
  • RISC type processors as such processors are capable of performing
  • processing unit 251 of the Packet Processor of Fig. 6 is the structure of processing unit 251 of the Packet Processor of Fig. 6 .
  • the processing unit comprises three
  • processor-1 400 main components, a processor-1 400, a coprocessor-1 401, and an internal
  • processor-1 is preferably of a RISC type
  • processor more preferably of the type known as ARC (by ARC cores, Ltd.).
  • Processor 400 receives data from the Tubular Bus 2430, more particularly
  • coprocessor 401 have each access to the tubular bus. While processor 400 performs mainly operations which are related to the logical analysis
  • coprocessor 401 do mainly specific tasks, i.e., carrying out the DES and or
  • the processor 400 communicates data that
  • bus 444 for further processing, or in some cases, when the processor detects
  • processor to perform higher layer tasks that are not directly related to the
  • peripheral bus 444 is is used by processor 400 to communicate mainly with
  • the bus is made through the memory controller 414.
  • the processor further comprises an extra Status Core register 407, and it also
  • auxiliary registers 410 communicates with auxiliary registers 410 via an auxiliary bus 411, which
  • auxiliary registers each contain
  • the memory of the processing unit comprises three
  • MAC media access control
  • controller 414 controls the communication between the processor 400 and
  • the Instruction Fetch Bus 420 is used by
  • the Sub-Unit Controller 290 also regulates
  • invention also comprises an internal interrupt interface 417, for handling interruptions.
  • an internal interrupt interface 417 for handling interruptions.
  • Four hardware interrupt lines are provided from the
  • timing clock 441 provides a timing clock 441 to the processor 400, and optionally also to other
  • the processing unit serves as a timeout
  • DMA Direct Memory Addressing
  • Each channel can enable various of DMA channels.
  • Each channel can be any channel that can enable various of DMA channels.
  • Each channel can be any channel that can enable various of DMA channels.
  • a DMA channel transfer can be initiated by a processor of a processing unit
  • Each channel supports a data chaining using a memory located
  • the DMA channels are divided into three main data transfer
  • the architecture of this invention is
  • the rate of that improvement may be less than is achieved by the
  • the modem may receive data that is actually received
  • the modem has to
  • the Packet Processor of the invention preferably further comprises an address filter 272.
  • address filter according to the invention is located on the Tubular Bus of the
  • the list of addresses contains, for
  • addresses are treated as unicast, i.e. the address filter looks for an exact address
  • Each address can be marked as "invalid”.
  • the structure of the Packet Processor of the invention enables performing
  • module of a modem is a general purpose and programmable, as its code can
  • the Packet Processor also preferably employs the concept of Inband
  • macro-instructions are the in-band commands which are passed between the
  • Macro-instruction and "0" means data).
  • the macro-instructions are used to allow control and "message" passing
  • each data word in the Packet is a
  • the structure of the MI depends on the MI group to which it belongs. Given
  • Table 2 defines the MI group codes: Table 2
  • the performance of the module is best when its tasks are divided between
  • the Venturi Pipe model describes a general data communication system
  • the Venturi Pipe as is known from classical fluid theory, is a variable
  • the dM/dt i.e., the
  • mass flow ratio is naturally kept equal along the pipe, while the same mass
  • Back layers (or group of layers) of information can use a dedicated processor
  • the processing units can be very small and simple, dedicated processors.
  • the Ventury Pipe Model, the Packet Processor of the invention preferably
  • processing unit-1 51 and processing unit-4 53 perform simple tasks on
  • processing unit-2 52 and
  • processing unit-3 54 perform more complicated tasks on larger units of data
  • processor is the ARC RISC microprocessor that can be parametrized in both

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

La présente invention concerne un processeur de paquets destiné à un appareil de communication qui traite des flux de données reçus et transmis constitués de paquets, chaque paquet comprenant principalement une en-tête et une partie charge utile, comprenant: (A) une partie réception, (B) une partie transmission, (C) un bus de squelette qui achemine les données de gestion, les instructions et les adresses entre divers constituants du processeur de paquets ; et (D) des systèmes de synchronisation et de commande permettant d'administrer le fonctionnement du processeur de paquets et plus particulièrement la synchronisation de l'utilisation des intervalles de transmission pour le chemin de transmission.
PCT/IL2000/000391 1999-07-05 2000-07-04 Processeur de paquets WO2001006704A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU55624/00A AU5562400A (en) 1999-07-05 2000-07-04 Packet processor

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
IL13079699A IL130796A (en) 1999-07-05 1999-07-05 Packet processor
IL130796 1999-07-05
US09/598,163 US6687757B1 (en) 1999-07-05 2000-06-21 Packet processor

Publications (2)

Publication Number Publication Date
WO2001006704A2 true WO2001006704A2 (fr) 2001-01-25
WO2001006704A3 WO2001006704A3 (fr) 2001-07-19

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Country Status (2)

Country Link
AU (1) AU5562400A (fr)
WO (1) WO2001006704A2 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001061935A1 (fr) * 2000-02-17 2001-08-23 Conexant Systems, Inc, Modem cable comprenant une commande d'acces au support (mac) programmable
WO2002102026A2 (fr) * 2001-06-12 2002-12-19 Corrent Corporation Procede et systeme pour le traitement a grande vitesse des paquets de protocole de securite ipsec
CN109768934A (zh) * 2018-12-28 2019-05-17 安徽皖兴通信息技术有限公司 一种路由器的纯phy接口板资源管理方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0765061A2 (fr) * 1995-09-22 1997-03-26 Hewlett-Packard Company Modem de transmission de données à grande vitesse

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0765061A2 (fr) * 1995-09-22 1997-03-26 Hewlett-Packard Company Modem de transmission de données à grande vitesse

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GOLDBERG L: "MCNS/DOCSIS MAC CLEARS A PATH FOR THE CABLE-MODEM INVASION" ELECTRONIC DESIGN,US,PENTON PUBLISHING, CLEVELAND, OH, vol. 45, no. 27, 1 December 1997 (1997-12-01), pages 69-70,74,78,80, XP000755759 ISSN: 0013-4872 *
MONTEIRO F ET AL: "A NEW PROCESSOR ARCHITECTURE DEDICATED TO DIGITAL MODEM APPLICATIONS" MONTEREY, CA, MAY 31 - JUNE 3, 1998,NEW YORK, NY: IEEE,US, 31 May 1998 (1998-05-31), pages 494-497, XP000873538 ISBN: 0-7803-4456-1 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001061935A1 (fr) * 2000-02-17 2001-08-23 Conexant Systems, Inc, Modem cable comprenant une commande d'acces au support (mac) programmable
US6816940B2 (en) 2000-02-17 2004-11-09 Conexant Systems, Inc. Cable modem having a programmable media access controller
WO2002102026A2 (fr) * 2001-06-12 2002-12-19 Corrent Corporation Procede et systeme pour le traitement a grande vitesse des paquets de protocole de securite ipsec
US7194766B2 (en) 2001-06-12 2007-03-20 Corrent Corporation Method and system for high-speed processing IPSec security protocol packets
WO2002102026A3 (fr) * 2001-06-12 2007-10-18 Corrent Corp Procede et systeme pour le traitement a grande vitesse des paquets de protocole de securite ipsec
CN109768934A (zh) * 2018-12-28 2019-05-17 安徽皖兴通信息技术有限公司 一种路由器的纯phy接口板资源管理方法
CN109768934B (zh) * 2018-12-28 2020-11-27 安徽皖兴通信息技术有限公司 一种路由器的纯phy接口板资源管理方法

Also Published As

Publication number Publication date
WO2001006704A3 (fr) 2001-07-19
AU5562400A (en) 2001-02-05

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