WO2001001565A1 - Method and apparatus for linearizing an amplifier - Google Patents
Method and apparatus for linearizing an amplifier Download PDFInfo
- Publication number
- WO2001001565A1 WO2001001565A1 PCT/US2000/018101 US0018101W WO0101565A1 WO 2001001565 A1 WO2001001565 A1 WO 2001001565A1 US 0018101 W US0018101 W US 0018101W WO 0101565 A1 WO0101565 A1 WO 0101565A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- difference
- input signal
- amplifier
- phase
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
- H03F1/3229—Modifications of amplifiers to reduce non-linear distortion using feed-forward using a loop for error extraction and another loop for error subtraction
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
- H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
- H03F2201/3221—Predistortion by overamplifying in a feedforward stage the distortion signal to have a combined main signal and "negative" distortion to form the predistorted signal for a further stage. so that after amplification in the further stage only the amplified main signal remains
Definitions
- Feedforward correction of an amplifier will improve the amplifier's linearity, but this type of correction requires a higher power amplifier due to losses inherent with the feedforward correction.
- Feedback correction will improve an amplifier's linearity, but these are usually band width limited.
- a feedforward system in the prior art of interest takes the form of the specifications of U.S. Patent No.5,850,162. In that system, an output amplifier having a non-linear signal response characteristic is linearized by selecting a preceding amplifier in a multi-stage amplifier network and providing feedforward overcorrection to the preceding amplifier to compensate for the non-linear signal response characteristics of the output amplifier.
- an amplifier having non-linear response characteristic can be linearized with a corrected input signal obtained from another amplifier which has been selected as exhibiting similar non-linear characteristics as the amplifier to be corrected. Also, it is contemplated that practicing the invention will result in efficiencies rivaling that of a Class A/B amplifier while yielding linearity that exceeds that of a Class A amplifier with wide bandwidth operation.
- the invention herein may reduce the memory-full and/ or non-memory-full distortions of an amplifier having a non-linear signal characteristic.
- Memory-full distortions refer to time dependent or historic distortions whereas non-memory-full distortions refer to non-time dependent distortions.
- the present invention includes apparatus for linearizing a first amplifying means having a non-linear signal response characteristic to an applied input signal and located between a signal source and a load, characterized in that second amplifying means is selected so as to exhibit a non-linear signal response characteristic to an applied input signal similar to that of said first amplifying means, means for applying a first portion of said input signal obtained from said signal source to said second amplifying means to generate an output signal therefrom, means for determining whether there is any difference between a second portion of said input signal and said output signal and providing a difference signal, means for phase inverting said difference signal to obtain an inverted difference signal, means for combining said inverted difference signal with said second portion of said input signal to obtain a corrected input signal, and means for applying said corrected input signal to said first amplifying means to obtain a corrected output signal.
- the invention also includes a method of linearizing a first amplifying means having a non-linear signal response characteristic to an applied input signal and located between a signal source and a load characterized by the steps of: selecting a second amplifying means that exhibits a non-linear signal response characteristic to an applied input signal similar to that of said first amplifying means; applying a first portion of said input signal obtained from said signal source to said second amplifying means to generate an output signal therefrom; determining whether there is any difference between a second portion of said input signal and said output signal and providing a difference signal; phase inverting said difference signal to obtain an inverted difference signal; combining said inverted difference signal with said second portion of said input signal to obtain a corrected input signal; and applying said corrected input signal to said first amplifying means to obtain a corrected output signal.
- the apparatus and method are provided for linearizing a first amplifier having a non-linear signal response characteristic to an input signal wherein the amplifier is located between a signal source and a load. This is accomplished by selecting a second amplifier that exhibits a non-linear signal response characteristic similar to that of the first amplifier. A first portion of the input signal obtained from the signal source is applied to the second amplifier to generate an output signal. A dete ⁇ nination is made as to whether there is any difference between a second portion of the input signal and the output signal and a difference signal is provide. The difference signal is then phase inverted to obtain an inverted difference signal. This inverted difference signal is combined with the second portion of the input signal to provide a corrected input signal. The corrected input signal is applied to the first amplifier to obtain a corrected output signal therefrom.
- the memory-full and/ or non-memory-full distortions of an output amplifier having a non-linear signal response characteristic to an applied input signal is reduced by providing a corrected input signal which is a memory-full and/ or non-memory- full in an inverse or negative manner.
- This aspect of the invention is accomplished by selecting an amplifier having similar memory-full and/ or non-memory-full distortions as the output amplifier. A portion of the input signal is applied to the selected amplifier, which is a scaled version of the output amplifier, to produce memory-full and/ or non-memory-full distortions. These distortions rmmic the distortions of the output amplifier.
- the output of the selected amplifier contains both the amplified version of the input signal and the memory-fuU and/ or non-memory-full distortions of the input signal.
- a portion of the input signal is subtracted from a portion of the output of the selected amplifier. This difference represents the negative of the memory-full and/ or non-memory-full distortions of the selected amplifier.
- At least a portion of the negative distortions of the selected amplifier are combined with at least a portion of the original input signal.
- the combined input signal, with the negative distortions of the selected amplifier is applied to the output amplifier.
- the resulting output of the output amplifier is essentially distortion free and contains essentially no memory-ful and/ or non-memory-full distortions.
- Fig. 1 is a schematic-block diagram illustration of one embodiment of the present invention
- Fig. 2 is a schematic-block diagram illustration of a second embodiment of the invention herein;
- Fig. 3 is a schematic-block diagram illustration of a third embodiment of the invention herein.
- the invention is directed toward linearizing an output amplifier having a non-linear signal response characteristic.
- the distortions of the amplifier may be memory-full and/ or non-memory-full distortions. These distortions are rninimized by providing a corrected input signal.
- Fig. 1 illustrates a non-linear amplifier 50 located intermediate a signal source SS and a load which may take the form of an antenna A.
- the amplifier 50 may take the form of a power amplifier employed in a radio frequency (RF) broadcasting transmitter.
- RF radio frequency
- the invention has particular application for use in providing linear amplification in a television transmitter. It is to be noted, however, that the invention herein may be applied to other situations wherein linear amplification is required. Such other situations, may, for example, include single-sideband communication transmitters, cellular radio based station transmitters and microwave transmitters.
- the non-linear amplifier 50 normally receives an input signal from the signal source SS and provides an output signal for application to the antenna A.
- This output signal because of the non-linear response characteristics of amplifier 50, will include memory-full and/ or non-memory-full distortions. This is corrected by apparatus and method as described herein below.
- a sampling device 10 samples the input signal from the source SS and supplies a portion of the input signal to a time delay 20 and another portion to a selected non-linear amplifier 60.
- the sampling device itself may be implemented by a zero degree splitter, a directional coupler or other sampling device.
- the outputs of the sampling device 10 are scaled replications of the input signal obtained from the signal source SS.
- one scaled portion is supplied to the time delay 20 whereas a second scaled portion is supplied to the amplifier 60.
- the amplifier 60 is selected such that it exhibits a non-linear response characteristic similar to or that mimics that of the non-linear amplifier 50. Thus, this amplifier 60 exhibits either or both memory-full and non-memory-full distortions and generates an output which is larger than its input.
- the amplifier 60 may be a scaled version of the non-linear amplifier 50. Also, it should be noted that if only memory-full distortions are to be corrected then the selected amplifier 60 need only create memory-full distortions. If only non- memory-full distortions are to be corrected, then amplifier 60 need only create non-memory- full distortions.
- amplifier 60 should exhibit both memory-full and non-memory-full distortions.
- Amplifier 60 may run at a much lower power level than the output amplifier 50. If desired, amplifier 60 could be identical to that of the output amplifier 50.
- the time delay 20 receives a portion of the original input signal from the sampling device 10 and then delays it by a time duration corresponding to the delay caused by amplifier 60 and supplies this time delayed portion to a sampling device 30.
- the time delay can be implemented by a coaxial transmission line, a filter or other suitable time delaying means.
- the time delayed input signal is applied to a sampling device 30 which operates in the same manner as the sampling device 10.
- the sampling device 30 provides a signal for application to summation device 40 and a signal for application to a difference circuit 70.
- the two signals obtained from the sampling device 30 may be at the same or at a reduced level as the input signal to the sampling device 30.
- the sample of the input signal from device 30 and the output of the selected nonlinear amplifier 60 are supplied to the difference circuit 70 which determines the difference between the two inputs and provides an output difference signal having a value representative of the difference of the two inputs.
- the difference output signal is supplied to a 180 degree phase shift circuit 80 which inverts the applied signal.
- the output of the phase shift circuit 80 is the negative of the input to that circuit.
- the output of the phase shift circuit 80 is scaled by a scaling constant K at a scaling circuit 90.
- K is either one, less than one or greater than one. It should be noted that circuits 80 and 90 may be reversed in their order.
- the scaled negative difference signal obtained from circuit 90 is combined with the time delayed portion of the input signal in a summation device 40.
- the summation or corrected input signal is applied to the non-linear amplifier 50.
- the summation device 40 may be implemented in the form of a zero degree hybrid, direction coupler or other surrtming device. Also, the summation device 40 can be implemented in the form of a 180 degree hybrid wherein the phase shift circuit 80 becomes an inherent part of the 180 degree hybrid.
- the negative difference signal which contains the memory-full and/ or non-memory-full distortion replica of the output amplifier, is cancelled.
- the output of the output amplifier is essentially a distortion free replica of the original input signal.
- Fig. 2 illustrates a second embodiment which is similar to that of the embodiment in Fig. 1 and to simplify the description herein like components are identified with like character references. Only the differences between the embodiment of Fig. 1 and that of Fig. 2 will be discussed below.
- the sampling devices 10 and 30, the time delay device 20 and the selected amplifier 60 have gain and phase variations from the ideal and from one unit to the next. To compensate for these variations, a manually adjustable variable attenuator 100 and a manually adjustable variable phase adjuster 110 have been added to the circuit.
- a probe or sampling device 130 is added.
- the variable attenuation device 100 and the variable phase adjuster 110 may be set or adjusted so that the original input signal is fully cancelled and the difference device 70 contains only the memory-full and/ or the non- memory-full distortions created by the selected amplifier 60.
- the summation device 40 and the 180 degree phase device 80 exhibit gain and phase variations from the ideal and from one unit to the next unit.
- a manually adjustable variable attenuation device 90 and a manually adjustable variable phase adjuster 120 have been added.
- the gain constant K device 90 in Fig. 1 has been replaced in Fig. 2 by the variable attenuation device 90.
- the variable attenuation device 90 and the variable phase adjuster 120 have losses not present in the ideal devices. Consequently, a linear amplifier 140 has been added to recover those losses.
- Fig. 3 illustrates a third embodiment which is similar to that illustrated in Fig. 2 and consequently only the differences between the two embodiments are described below.
- the output amplifier 50 may be a single amplifying device or plurality of amplifiers combined in any combining system.
- the selected amplifier 60 need only have similar memory-full and/ or non-memory-full distortions as the total presented by the output amplifier 50.
- This amplifier 50 may be made up of a group of multiple non-linear amplifiers 50A, 50B,...50N wherein N represents the number of such nonlinear amplifiers employed.
- Apparatus and method are provided for linearizing a first amplifier having a nonlinear signal response characteristic to an applied input signal.
- the amplifier is located between a signal source and a load. This is accomplished by selecting a second amplifier that exhibits a non-linear signal response characteristic to an applied input signal similar to that of the first amplifier. A portion of the input signal obtained from the signal source is then applied to the second amplifier to generate an output signal. A determination is made as to whether there is any difference between the input signal and the output signal and a difference signal is provided. The difference signal is phase inverted to obtain an inverted difference signal. This inverted difference signal is combined with the input signal to provide a corrected input signal. The corrected input signal is applied to the first amplifier to obtain a corrected output signal therefrom.
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002378011A CA2378011A1 (en) | 1999-06-30 | 2000-06-30 | Method and apparatus for linearizing an amplifier |
AT00950274T ATE230173T1 (en) | 1999-06-30 | 2000-06-30 | METHOD AND DEVICE FOR LINEARIZING AN AMPLIFIER |
AU63400/00A AU6340000A (en) | 1999-06-30 | 2000-06-30 | Method and apparatus for linearizing an amplifier |
JP2001506129A JP2003503867A (en) | 1999-06-30 | 2000-06-30 | Method and apparatus for linearizing an amplifier |
DE60001071T DE60001071T2 (en) | 1999-06-30 | 2000-06-30 | METHOD AND DEVICE FOR LINEARIZING AN AMPLIFIER |
EP00950274A EP1192710B1 (en) | 1999-06-30 | 2000-06-30 | Method and apparatus for linearizing an amplifier |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/343,340 | 1999-06-30 | ||
US09/343,340 US6242978B1 (en) | 1999-06-30 | 1999-06-30 | Method and apparatus for linearizing an amplifier |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001001565A1 true WO2001001565A1 (en) | 2001-01-04 |
Family
ID=23345718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/018101 WO2001001565A1 (en) | 1999-06-30 | 2000-06-30 | Method and apparatus for linearizing an amplifier |
Country Status (9)
Country | Link |
---|---|
US (2) | US6242978B1 (en) |
EP (1) | EP1192710B1 (en) |
JP (1) | JP2003503867A (en) |
AT (1) | ATE230173T1 (en) |
AU (1) | AU6340000A (en) |
CA (1) | CA2378011A1 (en) |
DE (1) | DE60001071T2 (en) |
TR (1) | TR200200189T2 (en) |
WO (1) | WO2001001565A1 (en) |
Families Citing this family (25)
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US20030058959A1 (en) * | 2001-09-25 | 2003-03-27 | Caly Networks. | Combined digital adaptive pre-distorter and pre-equalizer system for modems in link hopping radio networks |
US6643171B2 (en) * | 2001-11-06 | 2003-11-04 | Winbond Electronics Corporation | High dynamic range recording and playback for multilevel storage using differential sampling |
US7297166B2 (en) | 2003-06-25 | 2007-11-20 | Depuy Products, Inc. | Assembly tool for modular implants and associated method |
US7582092B2 (en) | 2003-06-25 | 2009-09-01 | Depuy Products, Inc. | Assembly tool for modular implants and associated method |
US8998919B2 (en) | 2003-06-25 | 2015-04-07 | DePuy Synthes Products, LLC | Assembly tool for modular implants, kit and associated method |
US7313208B2 (en) * | 2003-11-03 | 2007-12-25 | Zenith Electronics Corporation | Pre-equalization for low-cost DTV translators |
EP1571794B1 (en) * | 2004-03-01 | 2008-04-30 | Sony Deutschland GmbH | Method for inversely transforming a signal with respect to a given transfer function |
DE602004012168D1 (en) * | 2004-12-21 | 2008-04-10 | Ericsson Telefon Ab L M | BANDWIDTH RESTRICTED SIGNAL PROCESSING |
JP2007006436A (en) * | 2005-05-24 | 2007-01-11 | Hitachi Kokusai Electric Inc | Distortion compensating amplifier |
EP1935026A1 (en) | 2005-10-12 | 2008-06-25 | Acco | Insulated gate field-effet transistor having a dummy gate |
US8233562B2 (en) | 2007-09-05 | 2012-07-31 | Comtech Ef Data Corp. | System and method for closed-loop signal distortion |
US8556912B2 (en) | 2007-10-30 | 2013-10-15 | DePuy Synthes Products, LLC | Taper disengagement tool |
US8518050B2 (en) | 2007-10-31 | 2013-08-27 | DePuy Synthes Products, LLC | Modular taper assembly device |
US9240402B2 (en) | 2008-02-13 | 2016-01-19 | Acco Semiconductor, Inc. | Electronic circuits including a MOSFET and a dual-gate JFET |
US7863645B2 (en) * | 2008-02-13 | 2011-01-04 | ACCO Semiconductor Inc. | High breakdown voltage double-gate semiconductor device |
US8928410B2 (en) | 2008-02-13 | 2015-01-06 | Acco Semiconductor, Inc. | Electronic circuits including a MOSFET and a dual-gate JFET |
US7969243B2 (en) | 2009-04-22 | 2011-06-28 | Acco Semiconductor, Inc. | Electronic circuits including a MOSFET and a dual-gate JFET |
JP5105309B2 (en) * | 2008-07-15 | 2012-12-26 | 日本電気株式会社 | Power amplifier, non-linear distortion correction method for power amplifier, and wireless communication apparatus |
US8195118B2 (en) | 2008-07-15 | 2012-06-05 | Linear Signal, Inc. | Apparatus, system, and method for integrated phase shifting and amplitude control of phased array signals |
US7952431B2 (en) * | 2009-08-28 | 2011-05-31 | Acco Semiconductor, Inc. | Linearization circuits and methods for power amplification |
US8872719B2 (en) | 2009-11-09 | 2014-10-28 | Linear Signal, Inc. | Apparatus, system, and method for integrated modular phased array tile configuration |
US8532584B2 (en) | 2010-04-30 | 2013-09-10 | Acco Semiconductor, Inc. | RF switches |
US8533921B2 (en) | 2010-06-15 | 2013-09-17 | DePuy Synthes Products, LLC | Spiral assembly tool |
US9095452B2 (en) | 2010-09-01 | 2015-08-04 | DePuy Synthes Products, Inc. | Disassembly tool |
CN106943216B (en) | 2011-04-06 | 2019-12-31 | 德普伊新特斯产品有限责任公司 | Instrument assembly for implanting revision hip prosthesis |
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US4453133A (en) * | 1982-04-05 | 1984-06-05 | Bell Telephone Laboratories, Incorporated | Active predistorter for linearity compensation |
EP0367458A2 (en) * | 1988-10-31 | 1990-05-09 | AT&T Corp. | A predistortion compensated linear amplifier |
US5621354A (en) * | 1995-10-17 | 1997-04-15 | Motorola, Inc. | Apparatus and method for performing error corrected amplification in a radio frequency system |
US5781069A (en) * | 1996-05-16 | 1998-07-14 | Xemod, Inc. | Pre-post distortion amplifier |
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DE3614785A1 (en) * | 1986-05-02 | 1988-01-21 | Rohde & Schwarz | AUXILIARY SYSTEM FOR EQUALIZING FREQUENCY-DEPENDENT NON-LINEAR SYSTEMS, IN PARTICULAR AMPLIFIERS |
US5258722A (en) * | 1991-12-13 | 1993-11-02 | General Instrument Corporation, Jerrold Comminications | Amplifier circuit with distortion cancellation |
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US6054895A (en) | 1997-08-27 | 2000-04-25 | Harris Corporation | Apparatus and method for pre-distortion correction of a power amplifier stage |
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US6335767B1 (en) * | 1998-06-26 | 2002-01-01 | Harris Corporation | Broadcast transmission system with distributed correction |
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1999
- 1999-06-30 US US09/343,340 patent/US6242978B1/en not_active Expired - Fee Related
-
2000
- 2000-06-19 US US09/596,490 patent/US6751266B1/en not_active Expired - Fee Related
- 2000-06-30 JP JP2001506129A patent/JP2003503867A/en active Pending
- 2000-06-30 WO PCT/US2000/018101 patent/WO2001001565A1/en active IP Right Grant
- 2000-06-30 EP EP00950274A patent/EP1192710B1/en not_active Expired - Lifetime
- 2000-06-30 DE DE60001071T patent/DE60001071T2/en not_active Expired - Fee Related
- 2000-06-30 AT AT00950274T patent/ATE230173T1/en not_active IP Right Cessation
- 2000-06-30 AU AU63400/00A patent/AU6340000A/en not_active Abandoned
- 2000-06-30 TR TR2002/00189T patent/TR200200189T2/en unknown
- 2000-06-30 CA CA002378011A patent/CA2378011A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US4453133A (en) * | 1982-04-05 | 1984-06-05 | Bell Telephone Laboratories, Incorporated | Active predistorter for linearity compensation |
EP0367458A2 (en) * | 1988-10-31 | 1990-05-09 | AT&T Corp. | A predistortion compensated linear amplifier |
US5621354A (en) * | 1995-10-17 | 1997-04-15 | Motorola, Inc. | Apparatus and method for performing error corrected amplification in a radio frequency system |
US5781069A (en) * | 1996-05-16 | 1998-07-14 | Xemod, Inc. | Pre-post distortion amplifier |
Also Published As
Publication number | Publication date |
---|---|
US6242978B1 (en) | 2001-06-05 |
TR200200189T2 (en) | 2002-08-21 |
JP2003503867A (en) | 2003-01-28 |
ATE230173T1 (en) | 2003-01-15 |
CA2378011A1 (en) | 2001-01-04 |
EP1192710A1 (en) | 2002-04-03 |
DE60001071T2 (en) | 2003-10-02 |
US6751266B1 (en) | 2004-06-15 |
DE60001071D1 (en) | 2003-01-30 |
AU6340000A (en) | 2001-01-31 |
EP1192710B1 (en) | 2002-12-18 |
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