WO2000079693A1

WO2000079693A1 - Active hybrid with dynamic impedance matching against different loop conditions and related method

Info

Publication number: WO2000079693A1
Application number: PCT/US2000/040226
Authority: WO
Inventors: Ting Sun
Original assignee: 2Wire, Inc.
Priority date: 1999-06-18
Filing date: 2000-06-15
Publication date: 2000-12-28
Also published as: AU6540400A

Abstract

A system and method are disclosed for matching, or approximating, the impedance of an ADSL modem with the impedance of the associated loop by selectively switching in different impedances to improve or enhance ADSL performance in a variety of loop conditions. Using relays or multiplexers to actively switch in and out different impendance networks, the ADSL modem may select an impedance from a set of impedances (610, 612) that best matches the loop impedance. The different impedances may be switched singly or in combination with other impedances. Lastly, systems and methods are disclosed for using DSP measurement of the ADSL transmitter's (602) echo signal as the basis for determining hybrid impedance matching.

Description

ACTIVE HYBRID WITH DYNAMIC IMPEDANCE MATCHING AGAINST DIFFERENT LOOP CONDITIONS AND RELATED METHOD

By Ting Sun BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates generally to DSL modems and, more particularly, to a DSL modem with impedance matching capability against a variety of loop conditions and impairments.

2. Description of the Background Art

As the Internet continues to become more popular, there is an increasing need for accessing and navigating ("surfing") the Internet at high speed and at low cost. Providing high speed Internet access permits users to send and receive information over the Internet quickly and reduces the time the user must wait to receive requested information. In addition, there is a continuous pressure to lower the cost of accessing the Internet and Internet-related devices.

One method of accessing the Internet is by using Digital Subscriber Line (DSL) technology. Various versions of DSL exist, such as Asymmetric DSL (ADSL), Symmetric DSL (SDSL), Rate Adaptive DSL (RADSL), Very high speed ADSL (VADSL), Consumer DSL (CDSL), etc., and may be collectively referred to as xDSL, or DSL.

ADSL is one version of DSL technology that expands the useable bandwidth of existing copper telephone lines, delivering high-speed data communications at rates up to about 8 Mbps without interrupting normal telephone service, also known as POTS (Plain Old Telephone Service). To achieve this end, ADSL uses frequency-division multiplexing (FDM) technology to carry POTS and ADSL channels all on the same twisted-pair copper telephone line.

ADSL is a point-to-point connection in that an ADSL termination device must be present on each end of the copper circuit. Since ADSL works over copper, it is an appropriate technology for the "local loop," which comprises the copper circuits running from a local telephone switch, or central office, into virtually every home and business. Unfortunately, however, conventional ADSL systems have been problematic for a variety of reasons. One significant limitation of conventional ADSL systems relates to the analog front end (AFE) design of the ADSL modem. In particular, to achieve good data rate transmission it is important to match the impedance of the loop with that built into the hybrid of an ADSL modem. Since the characteristic impedance of the loop frequently varies due to varying loop length, unterminated bridged taps, wire splices from different gauge wire, etc., it is difficult, if not impossible, to match such a varying impedance with a single impedance network.

For example, one conventional ADSL modem analog front end is configured as a 4- wire to 2-wire trans-hybrid design and uses a single impedance network of about 100 ohms. An analog front end using a single impedance substantially matches the loop impedance much of the time, but frequently mismatches the loop's characteristic impedance, especially when unterminated bridge taps and/or wire splices of different gauge occur. Such mismatching of impedance tends to cause poor return loss, increasing noise reflection, and transmit echo signals that affect and impair the primary modem's receive signal. In result, impedance mismatching will degrade FDM ADSL modem performance.

Accordingly, a need exists for an ADSL modem that may efficiently operate under a variety of loop impedances. An additional need exists to provide an ADSL modem analog front end that is relatively inexpensive and that minimizes echo of the transmitter signal and noise reflection at the ADSL modem - loop interface.

SUMMARY The present system overcomes or substantially alleviates prior problems associated with operating a DSL modem in connection with an existing DSL loop. In general, the present system employs an active hybrid with dynamic impedance match capability using the combination of multiple impedance matching networks to enhance or improve DSL performance in different loop conditions. The system switches in and out different impedance networks, in parallel or in series, in conjunction with a digital signal processing (DSP) algorithm to achieve an impedance match, or approximate match, between an active hybrid DSL modem and the associated DSL loop to improve the DSL data transfer between the two under different loop conditions. The switching may be accomplished, for example, by relays (mechanical or solid state), analog switches, or analog multiplexers. The loop conditions may include loop type, loop length, and loop impairment.

Pursuant to one embodiment, an ADSL modem switches in a first impedance, probes the loop, and measures an echo signal associated with the first impedance. Next, the first impedance is switched out and a second impedance is switched in or made active. Then, the ADSL modem probes the loop and measures an echo signal associated with the second impedance. If the echo signal associated with the second impedance is weaker than that associated with the first impedance, the second impedance is made the default impedance. Otherwise, the first impedance is left as the default impedance. This process may then continue for the remainder of the available impedance networks to determine which impedance network best approximates, or yields the weakest echo signal from, the loop impedance.

Alternatively, a predetermined echo threshold defines an acceptable amount of echo signal that can be tolerated and still permit acceptable ADSL performance (data connect rate). The ADSL modem then switches in and tests different impedance networks until identifying an impedance network that yields an echo signal that is less than or equal to the predetermined echo threshold. Under this approach, the ADSL modem may not have to test each of the impedance networks. Instead, the ADSL modem continues to test impedance networks until it identifies an impedance network that yields an impedance that yields less than or equal to the predetermined echo threshold.

According to another embodiment, if none of the impedance networks yields an echo signal that is less than or equal to the threshold echo signal, the process continues to determine which impedance network yields the lowest echo signal. In one configuration, the present system employs relays, analog switches, or analog multiplexers to actively switch in and switch out different impedance networks singly, in combinations, or both. This is done in conjunction with a DSP algorithm for echo signal measurement of the local transmit signal, optimized so that the best matching impedance network can be selected to maximize first-order hybrid rejection. Maximizing the first-order hybrid rejection minimizes the amount of echo signal as well as noise reflection from the transmit path and, thus, improves or enhances ADSL performance.

Advantageously, the different impedances are complex impedances, which have different real and imaginary components to better match the impedance of the loop, which typically will include an impedance characterized by having both real and imaginary components. That is, the different impedances preferably have different real components and different complex components, which may include a capacitance or an inductance.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating an ADSL service network; FIG. 2 is a block diagram of the splitter of FIG. 1;

FIG. 3 is a block diagram illustrating an alternative ADSL service network; FIG. 4 is a block diagram of the ADSL modem illustrated in FIGS. 1 and 3;

FIG. 5 is a block diagram of the ADSL codec illustrated in FIG. 4; FIG. 6 is a block diagram of the Analog Front End (AFE) of FIG. 4; FIG. 7 A illustrates an example of different impedance networks associated with the different impedances shown in FIG. 6; FIG. 7B illustrates another example of different impedances that may be selectively activated to match a loop impedance;

FIG. 8 is a flowchart illustrating one embodiment of a method of the present system;

FIG. 9 is a flowchart illustrating another embodiment of the method of the present system; and

FIG. 10 is a flowchart illustrating yet another embodiment of the method of the present system.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 illustrates an ADSL service network 100 that includes a central office 102 including a Digital Subscriber Line Access Muliplexer (DSLAM) 103 and a home 104 coupled by a loop 106. As shown, the central office 102 includes an ADSL transceiver unit 110 and a loop interface 112. The loop interface 112 includes a high pass filter 114 and a low pass filter 116 to split high frequency ADSL components of the loop signal and the lower frequency POTS (Plain Old Telephone Service) components of the loop signal. In this configuration, the high pass filter 114 passes signals in the ADSL frequency range to the broadband network 120 via the ADSL transceiver 110. Likewise, the low pass filter 116 passes the lower frequency POTS signals to the narrow band network 122 over a PSTN (Public Switched Telephone Network) line.

The home 104 is shown as including a splitter 130, an ADSL modem 132, a computer 134, a telephone, or POTS, network 136, and POTS devices, such as telephones 138. While the ADSL modem 132 is illustrated as being disposed outside of the computer 134, those skilled in the art will appreciate that the ADSL modem 132 could also be positioned inside the computer 134.

The splitter 130 splits the incoming signal into high and low frequency components. As discussed in more detail below with reference to FIG. 2, the splitter 130 routes the high frequency component along line 140 to the ADSL modem 132, which is coupled to a network device, such as a computer 134, by a line 142. Likewise, the splitter 130 routes the low frequency, or POTS, component of the incoming signal to the telephone network 136 along line 144. The telephones 138, as well as other POTS devices (e.g. 56k modems, facsimile machines, etc.), are coupled to the telephone network 136 by lines 148.

Additional details concerning conventional ADSL equipment are found in Standards Project for Interfaces Relating to Carrier to Customer Connection of Asymmetrical Digital Subscriber Line (ADSL) Equipment, T1E1.4/97-007R6, T 1.413 Issue 2, edited by John Bingham and Frank van der Putten, dated September 26, 1997, which is incorporated herein by reference. FIG. 2 illustrates details of the splitter 130 of FIG. 1. As shown, the splitter 130 includes a high pass filter 202 and a low pass filter 204 coupled to the loop 106 via lines 206 and 208 respectively. The high pass filter 202 permits higher frequency signals, such as ADSL signals, to pass from the loop 106 to the ADSL modem 132 (FIG. 1) while preventing the lower frequency POTS signals from entering onto the line 140 and potentially interfering with the operation of the ADSL modem 132. Similarly, the low pass filter 204 permits the lower frequency POTS signals to pass onto the telephone network 136 while preventing higher frequency signals, such as ADSL signals, from entering onto the telephone network 136 and potentially interfering with the operation of POTS devices, such as the telephones 138, coupled thereto. In addition, the low pass filter 204 isolates impedance changes on the telephone network 136 caused by the POTS devices, such as the telephones 138, such that the impedance changes do not affect the performance of the ADSL modem 132.

FIG. 3 illustrates an alternative ADSL network 300. The network 300 differs from that illustrated in FIG. 1 in that it does not include the splitter 130 disposed between the loop 106 and the telephone network 136 or the ADSL modem 132. As such, the loop 106 is directly coupled to the telephone network 136. In contrast with the network 100 shown in FIG. 1, the network 300 includes low pass filters 302 disposed between the telephones 138 and the telephone network 136. The low pass filters 302 generally prevent the higher frequency signals from interfering with operation of the telephone 138 and separate the lower frequency voice band signals from the ADSL spectrum. In addition, the low pass filters 302 isolate impedance changes on the telephone network 136 caused by the POTS devices, such as the telephones 138, such that the impedance changes do not affect the performance of the ADSL modem 132.

FIG. 4 illustrates details of the ADSL modem 132 depicted in FIGS. 1 and 3. As shown, the ADSL modem 132 includes a Digital Signal Processor (DSP) 402, an ADSL coder/decoder (codec) 404, and an Analog Front End (AFE) 406. The AFE 406 is coupled to the line 140, which leads to the loop 106 by a transformer 410. The DSP 402 is illustrated as including a PCI (Peripheral Component Interconnect) bus controller 412, which controls communications between the ADSL modem 132 and the PCI bus 414 of the computer 134 along line 416. Again, those skilled in the art will appreciate that the ADSL modem 132 can be positioned internal or external of the computer 134 and the data peripheral interface between the computer 134 and the associated ADSL modem 132 can be, for example, Universal Serial Bus (USB) or parallel port. First and second control lines 420 and 422 interconnect the AFE 406 and the DSP 402 to enable direct communication therebetween. A central processor (not shown) may alternatively control the AFE 406.

FIG. 5 illustrates details of the ADSL codec 404 depicted in FIG. 4. The ADSL codec 404 includes a digital to analog converter 502 coupled to a reconstruction filter and attenuator 504 for converting the DSP 402 output to an analog signal and reconstructing the same. Additionally, the ADSL codec 404 includes an analog to digital signal converter 506 and a programmable gain amplifier 508 for converting to digital format the signals received by the ADSL codec 404 from the Analog Front End (AFE) 406. Accordingly, in this configuration, the ADSL codec 404 provides A/D and D/A signal conversions between the DSP 402 and the analog front end (AFE) 406.

FIG. 6 illustrates details of the Analog Front End (AFE) 406 of FIG. 4. As shown, the AFE 406 is interposed between the loop 106 and the ADSL codec 404 and includes an ADSL transmitter filter 602, an ADSL line driver with gain stage 604, an ADSL receiver filter 606, and an ADSL high-speed differential receiver 608. The ADSL transmitter filter 602 advantageously comprises a low pass filter and the ADSL receiver filter 606 advantageously comprises a band-pass filter for echo suppression and anti-aliasing. Moreover, the ADSL transmitter 604 has a gain = nl while the ADSL high-speed differential receiver 608 has a gain = n2.

The Analog Front End (AFE) 406 also includes a set of impedance networks 610 comprising impedance networks Zl, Z2, Z3...Zn for selectively and actively changing the hybrid matching impedance of the AFE 406 to more adaptively and closely match, or approximate, the impedance of the loop 106 to improve or enhance ADSL performance. The set of impedance networks 610 are disposed between lines 612 and 614. As discussed in more detail below, relays, analog switches, or analog multiplexors (not shown) selectively switch in, or turn on, the different impedance networks. Networks Zl-Zn are switched in, or turned on, singly or in combinations to more closely match the impedance of the loop 106. In one embodiment, the different impedance networks Zl-Zn are switched in, or turned on, singly or with multiple impedance networks in parallel. The DSP 402 (FIG. 4) may select a particular impedance or combination of impedances based on which impedance or combination of impedances yields the smallest echo signal, based on which impedance or combination of impedances yields an echo signal that is within a predetermined threshold echo tolerance, or both. The DSP 402 controls the switching of impedances Zl - Zn via the control lines 420 and 422.

FIG. 7 A illustrates one embodiment of a set of impedance networks 610 including impedances Zl - Zn, which may be arranged in parallel or in series with each other, each impedance Zl - Zn also having an associated switch 702. In this configuration, the impedances Zl - Zn may be switched on singly or multiple impedances may be switched on by operation of the switches 702. As shown, the impedance networks Zl- Zn may include resistors, inductors, and capacitors. While different numbers of impedances Zl - Zn may be employed, two or three impedances may provide a sufficient number of impedances to substantially match a very high percentage of, if not all, anticipated loop conditions at relatively low cost.

FIG. 7B depicts another set of impedance networks 720. This embodiment includes a resistor 722, a first capacitor 724, a resistor 726, a switch 728, and a second capacitor 730. As shown, the first capacitor 724 and the resistor 726 are arranged in parallel and may be selectively switched in by operation of the switch 728. Hence, this embodiment provides the selection of two different effective impedances, one impedance with the switch 728 open and another impedance with the switch 728 closed. In some applications, two impedances may be sufficient to acceptably match the impedance of the loop 106.

FIG. 8 is a flowchart 800 that depicts operation of one embodiment of the present system. Initially, as shown in block 802, the ADSL modem 132 (FIG. 4) is reset. Next, the ADSL modem 132 is powered up and the DSP 402 is initialized pursuant to block 804. The DSP 402 then sets or assigns one of the impedance networks Zl - Zn, or a combination of impedance networks, to be the default impedance Z₀ pursuant to block 806.

Then, pursuant to block 808, the ADSL modem 132 (FIG. 4) probes the loop 106 and then measures an echo signal E₀ reflected back from the loop 106. One way in which the ADSL modem 132 may probe the loop 106 is by emitting a transmitter tone, or multiple tones, in the ADSL signal band. The reflected echo signal may then be detected by the ADSL receiver filter 606 (FIG. 6) and the DSP 402 (FIG 4). The better the impedance match between the ADSL modem 406 and the loop 106, the weaker, or smaller, the echo signal will be. Conversely, the worse the impedance match between the ADSL modem 406 and the loop 106, the stronger, or larger, the echo signal will be.

After Eo has been determined as described above, Z₀ is turned off, or switched out, and Z_New is turned on, or switched in, so that ZNe is the currently active impedance pursuant to block 810. ZNew is the next impedance to be tested. Then, in a manner similar to block 808, the ADSL modem 132 probes the loop 106 and measures the echo signal associated with ZNew, which is EN_ew, pursuant to block 812.

Once Eo and ENew have been determined, the DSP 402 determines whether E_New is less than E₀ pursuant to block 814. In essence, the DSP 402 is determining whether Z_Ne results in a lower echo signal, and thus a better impedance match, than Z₀. If E^_w is less than E₀, then execution proceeds to block 816 and Z₀ is assigned to be equal to Z_Ne and E₀ is assigned to be equal to E ew so that ZNew is the new default impedance, else execution proceeds to block 812. At block 818, the DSP 402 determines whether all of the available impedances Zl - Zn have been checked. If there are impedances, or combinations of impedances, that have not yet been checked, then execution returns to block 810 so that the next impedance may be checked to determine whether it is a better impedance match than Z₀.

After all of the different impedances and combinations of impedances have been checked pursuant to blocks 810 - 816, the impedance with the best impedance match with the loop 106 will be Z₀. Thus, upon termination at block 820, the optimal impedance match Zop_timized will be equal to or the same as Z₀. A significant advantage of employing the method of the flowchart 800 is that the best available impedance match may be determined by testing each impedance and combination of impedances. However, this method may continue to test additional impedances or combinations of impedances after an acceptable impedance has already been tested.

As another embodiment, FIG. 9 illustrates a flowchart 900 for identifying an impedance or combination of impedances that provide an acceptable impedance match with the loop 106 (FIG 1). Initially, the ADSL modem 132 (FIG. 4) is reset pursuant to block 902. Then, the ADSL modem is powered up and the DSP 402 (FIG. 4) is initialized pursuant to block 904. Next, one of the impedances, Zl is selected as the default impedance Z₀ pursuant to block 906. In one embodiment, the default impedance Zl has an impedance of about 100 ohms or an impedance that is acceptable for the most common loop impedances. Once the ADSL modem 132 is thus set up, the echo threshold Eo is set pursuant to block 908. Eo is a predetermined echo signal magnitude that represents an acceptable echo signal threshold so that any impedance producing an associated echo signal that is equal to or less than Eo is an acceptable impedance match with the loop 106.

Then, a first impedance, Z , is turned on or switched in so as to be the active impedance of the AFE 406 pursuant to block 910. The ADSL modem 132 then probes the loop 106 and measures the reflected echo signal E_N associated with the first impedance ZN pursuant to block 912. Once the echo signal E_N has been determined, the DSP 402 compares the echo threshold Eo with the measured echo signal E_N to determine whether the difference between Eo and E_N is greater than or equal to zero pursuant to block 914. In other words, the action of block 914 determines whether the measured echo signal E_N associated with the impedance ZN is less than or equal to the echo threshold Eo and thus represents an acceptable impedance match. If so, then execution proceeds to block 916 where the process terminates with Zoptimized = Z₀. If not, then execution proceeds to block 918.

At block 918, ZN is turned off, or switched out and the next impedance, Z_N+I, is turned on and made the new default impedance Z₀. Then, the DSP 402 determines whether this newly turned on impedance, Z_N+_I, is the last impedance to be checked, pursuant to block 920. That is, the DSP 402 determines whether there are any more impedances Zl - Zn to be checked. If the impedance Z_N+ι is the last impedance to be checked, then execution continues to block 922 and Z₀ is assigned to be equal to the first impedance Zl, which, as discussed above, is chosen as a good impedance match with the most common loop characteristic impedance. Preferably, however, one of the tested impedances will have an associated echo signal that is less than or equal to the echo threshold Eo. If the determination of block 920 is "no," then execution continues to block 912 so that the newly switched in impedance may be tested to see if it yields an echo signal that is less than or equal to the echo threshold E₀. FIG. 10 is a flowchart 1000 that depicts yet another embodiment of a method for matching the impedance of the ADSL modem 132 with the loop 106. As described below, the flowchart 1000 combines aspects of the flowcharts 800 and 900 described above with reference to FIGS. 8 and 9 respectively. Initially, the ADSL modem 132 (FIG. 4) is reset pursuant to block 1002. Then, the

ADSL modem is powered up and the DSP 402 (FIG. 4) is initialized pursuant to block 1004. Next, one of the impedances, Z_N is selected as the default impedance Zo pursuant to block 1006. Once the ADSL modem 132 is thus set up, the echo threshold Eo is set pursuant to block 1008. As discussed above, E₀ is a predetermined echo signal magnitude that represents an acceptable echo signal threshold so that any impedance having an associated echo signal that is equal to or less than E₀ is an acceptable impedance match with the loop 106.

Then, a first impedance, Z_N, is turned on or switched in so as to be the active impedance of the AFE 406 pursuant to block 1010. The ADSL modem 132 then probes the loop 106 and measures the reflected echo signal E_N associated with the first impedance Z pursuant to block 1012. Once the echo signal EN has been determined, the DSP 402 compares the echo threshold Eo with the measured echo signal E to determine whether the difference between Eo and E_N is greater than or equal to zero pursuant to block 1014. In other words, the action of block 1014 determines whether the measured echo signal E_N associated with Z_N is less than or equal to the echo threshold E₀ and thus represents an acceptable impedance match. If so, then execution proceeds to block 1016 where the process terminates with Zo_ptimized = Z₀. If not, execution proceeds to block 1018.

At block 1018, Z_N is turned off, or switched out and the next impedance, Z_N+I, is turned on and made the new default impedance Zo. Then, the DSP 402 determines whether this newly turned on impedance, ZN+I, is the last impedance to be checked, pursuant to block 1020. That is, the DSP 402 determines whether there are any more impedances Zl - Zn to be checked. If the impedance ZN+I is the last impedance to be checked, then execution continues to block 1020, which directs execution to block 806 of the flowchart 800 shown in FIG. 8 and described above so that the best impedance match of the available impedances may be employed. If the determination of block 1020 is "no," then execution continues to block 1012 so that the newly switched in impedance may be tested to see if it yields an echo signal that is less than or equal to the echo threshold Eo.

The invention has been described above with reference to specific embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The foregoing description and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

What is claimed is: 1. A modem for interfacing a computer and a loop, the loop having a loop impedance, the modem comprising: an analog front end having multiple impedance networks for actively providing an impedance value that approximates the loop impedance; and a digital signal processor configured to control activation of the multiple impedance networks.

2. The modem of claim 1 , wherein the analog front end in conjunction with the digital signal processor tests each of the impedance networks to determine which one of the impedance networks approximates the loop impedance.

3. The modem of claim 2, wherein the analog front end tests at least one of the impedance networks by measuring an echo signal corresponding to the tested impedance network.

4. The modem of claim 3, wherein the digital signal processor compares the echo signal corresponding to at least one of the impedance networks to an echo threshold value to identify one of the impedance networks that acceptably approximates the loop impedance.

5. The modem of claim 4, wherein the impedance network that corresponds to an echo signal less than or equal to the echo threshold value is the impedance network that approximates the loop impedance.

6. The modem of claim 3, wherein the digital signal processor identifies which of the impedance networks yields a minimum echo signal, and employs the identified impedance network to approximate the loop impedance.

7. The modem of claim 3, wherein the digital signal processor compares the echo signal corresponding to each tested impedance network to an echo threshold value, determines whether the corresponding echo signal is less than or equal to the echo threshold value, and if none of the tested impedance networks corresponds to an echo signal that is less than or equal to the echo threshold value, the processor selects the impedance network corresponding to the weakest echo signal.

8. The modem of claim 1, wherein the impedance networks are connected in parallel.

9. The modem of claim 1, wherein the impedance networks are connected in series.

10. The modem of claim 1, wherein the impedance networks are complex impedances including capacitance values.

11. The modem of claim 1, wherein the impedance networks are complex impedances including inductance values.

12. The modem of claim 1, wherein the impedance networks are complex impedances including capacitance values and inductance values.

13. The modem of claim 1 being an Asymmetric Digital Subscriber Line (ADSL) modem.

14. The modem of claim 1, wherein the analog front end in conjunction with the digital signal processor tests combinations of the impedance networks to determine a combination of the impedance networks that approximates the loop impedance.

15. A method for approximating a loop impedance of a loop, comprising the steps of: providing a set of impedance networks; measuring an echo signal corresponding to each of the impedance networks; and determining which one of the impedance networks approximates the loop impedance using the echo signals corresponding to the impedance networks.

16. The method of claim 15, wherein the step of determining which one of the impedance networks approximates the loop impedance includes comparing the echo signal corresponding to each of the impedance networks to an echo threshold value, wherein a measured echo signal that is less than or equal to the echo threshold value corresponds to the impedance network that approximates the loop impedance.

17. The method of claim 15, wherein the step of determining which one of the impedance networks approximates the loop impedance further comprises determining a minimum echo signal of the echo signals corresponding to the impedance networks such that the minimum echo signal corresponds to the impedance network that approximates the loop impedance.

18. The method of claim 15 , wherein the step of determining which one of the impedance networks approximates the loop impedance further comprises comparing the echo signal corresponding to each of the impedance networks to an echo threshold value, wherein an echo signal that is less than or equal to the echo threshold value corresponds to the impedance network that approximates the loop impedance, and if no echo signal is less than or equal to the echo threshold value, determining a minimum echo signal such that the minimum echo signal corresponds to the impedance network that approximates the loop impedance.

19. The method of claim 15, wherein the set of impedance networks includes complex impedances.

20. The method of claim 15 implemented in a modem for interfacing a computer to the loop.

21. The method of claim 20 wherein the modem is an Asymmetric Digital Subscriber Line (ADSL) modem.

22. A device for approximating an unknown impedance of a system, the device comprising: a plurality of impedance networks, each impedance network having an impedance value; a switching mechanism for selectively activating at least one of the impedance networks; and a processor configured to control the switching mechanism to select an impedance network that approximates the unknown impedance.

23. The device of claim 22, wherein the processor is configured to select the impedance network that approximates the unknown impedance by testing each of the impedance networks, and selecting the impedance network that best approximates the unknown impedance.

24. The device of claim 22, wherein the processor is configured to select the impedance network that approximates the unknown impedance by measuring an echo signal that corresponds to each impedance network, and selecting the impedance network that best approximates the unknown impedance.

25. The device of claim 22, wherein the switching mechanism is implemented as a relay.

26. The device of claim 22, wherein the switching mechanism is implemented as an analog multiplexer.

27. The device of claim 22, wherein the processor is a digital signal processor and the impedance values are complex impedances.

28. The device of claim 27, wherein the complex impedances include capacitance values.

29. The device of claim 27, wherein the complex impedances include inductance values.

0. A device for substantially matching an unknown impedance, comprising: a set of impedance network means; means for measuring an echo signal corresponding to each of the impedance network means; and means for determining which one of the impedance network means substantially matches the unknown impedance using the echo signals corresponding to the impedance network means.