WO2000077933A1

WO2000077933A1 - Circuit comprising a disconnectable power semiconductor switch

Info

Publication number: WO2000077933A1
Application number: PCT/DE2000/001872
Authority: WO
Inventors: Benno Weis; Eric Baudelot; Manfred Bruckmann; Heinz Mitlehner
Original assignee: Siemens Aktiengesellschaft
Priority date: 1999-06-11
Filing date: 2000-06-13
Publication date: 2000-12-21

Abstract

The invention relates to a circuit comprising a disconnectable power semiconductor switch, a drive circuit (10) and a desaturation measuring circuit (8). According to the invention, a cascode circuit (2) comprised of a series-connection of a low-blocking and high-blocking semiconductor switch (4, 6) is provided as a disconnectable power semiconductor switch. The desaturation measuring circuit (8) is connected to a drain terminal (D') of the low-blocking semiconductor switch (4) via a decoupling diode (12), and the drive circuit (10) is connected on the output side to the gate terminal (G') of the low-blocking semiconductor switch (4). This enables a short-circuit to be identified even when the cascode circuit (2) is switched to an existing short-circuit.

Description

description

Circuit arrangement with a switchable power semiconductor switch

The invention relates to a circuit arrangement with a power semiconductor switch that can be switched off in accordance with the preamble of claim 1.

In many applications, electronic circuits are required to recognize and manage overcurrents and short circuits. If non-latching, switchable semiconductor switches, e.g. Insulated gate bipolar transistors (IGBT) or metal oxide layer field-effect transistors (MOSFET) are used, so that the aforementioned requirements can be met without additional passive components in the power circuit by controlling the semiconductor switch alone.

The currently most common solution to the problem described is the use of saturation monitoring. This principle takes advantage of the fact that non-locking, switchable power semiconductor switches have output characteristics which are shown schematically in FIG.

The output voltage of this semiconductor switch is monitored during the conducting state of the semiconductor switch. Based on the known output characteristic, the level of the output voltage is a measure of the current which the semiconductor switch carries. If the semiconductor switch carries an overcurrent, its output voltage rises, whereby this rise becomes disproportionately strong with very large currents (short-circuit case). The rise in the output voltage of the semiconductor switch is used as a signal for an overcurrent or short-circuit current. Such a circuit with saturation monitoring for a switching transistor is known from EP 0 361 212 Bl. This circuit arrangement has a desaturation measuring circuit, which is linked on the input side by means of a decoupling diode to a collector terminal of the switching transistor. On the output side, this desaturation measuring circuit is connected to a switch-off device which is arranged in the gate supply line. In addition, this circuit arrangement has a protective circuit which has a timing element on the input side and a series circuit comprising a zener diode and an off switch electrically in parallel with the base-emitter path of the switching transistor. The control signal of the switching transistor is present at the input of the timing element, a control signal being present at its output. This control signal, which is the time-delayed control signal, opens the switch and simultaneously activates the desaturation measuring circuit. As soon as the control signal is withdrawn, the switch immediately returns to its rest position (closed). On the one hand, this protective circuit limits the collector current of the switching transistor when it has been connected to an existing short circuit, and on the other hand it only activates the desaturation measuring circuit when the switching transistor is in nominal operation.

This circuit arrangement has several disadvantages:

a) The measuring circuit for detecting the desaturation of the power semiconductor switch must be decoupled in the switched-off state of the semiconductor switch by a high-blocking component, which is generally a diode, the diode having to have the dielectric strength of the power semiconductor switch . b) When the power semiconductor switch is switched on, the desaturation measuring circuit must be deactivated until the collector-emitter voltage of the power semiconductor switch has dropped to its stationary end value (saturation voltage). Switches the power semiconductor Switch to an existing short circuit or if a short circuit occurs immediately after switching on, this short circuit is not recognized, but the collector current of the switching transistor is limited, c) The design of the power semiconductor switch must be designed to saturate at the lowest possible current values. This limits the optimization of the power semiconductor switch, for example, to improved transmission behavior.

The invention is based on the object of specifying a circuit arrangement which no longer has the disadvantages described.

This object is achieved according to the invention by the characterizing features of claim 1.

Characterized in that a cascode circuit consisting of a series circuit of a low and high blocking semiconductor switch, is used as a power semiconductor switch that can be switched off, the output voltage of the low blocking semiconductor switch is used for the desaturation measuring circuit. As a result, the high-blocking semiconductor switch does not have to be optimized for a low desaturation current. Since the output voltage of the low-blocking semiconductor switch is now used for the detection of desaturation, the dielectric strength of the decoupling diode drops to the level of the low-blocking semiconductor switch of the cascode circuit. It is now also possible to optimize the two semiconductor switches of the cascode circuit separately. The low-blocking semiconductor switch is optimized for low forward voltage and low desaturation current, whereas the high-blocking semiconductor switch of the cascode circuit is optimized with regard to improved forward behavior. In an advantageous embodiment of the circuit arrangement, a hybrid power MOSFET is used as the cascode circuit, which as the low-blocking semiconductor switch is a MOSFET, in particular a self-blocking n-channel MOSFET, and the high-blocking semiconductor switch is a barrier layer FET, in particular a self-conducting n-channel blocking layer - FET, wherein the gate connection of the junction FET is connected to the source connection of the MOSFET by means of a resistor. The junction FET is also referred to as a junction field effect transistor (JFET). This special configuration of the cascode circuit ensures that the maximum reverse voltage of the MOSFET is 30 V. Therefore a high voltage decoupling of the desaturation measuring circuit is not necessary. In addition, the output voltage of the MOSFET drops so quickly due to an Em-switching signal that the load current can only increase slightly during this very short time interval. As a result, the saturation voltage of the MOSFET is available as a signal for short-circuit detection after a short time. It is therefore possible for a short circuit to be detected when the cascode circuit switches to an existing short circuit. In addition, no blanking circuit is required for the desaturation measuring circuit.

In a further advantageous embodiment of the circuit arrangement, a cascade connection of a MOSFET with a voltage-controlled semiconductor switch is used as the cascode circuit, the gate connection of the voltage-controlled semiconductor switch being linked to the source connection of the MOSFET by means of a constant voltage source. This embodiment also has the advantages mentioned above, regardless of the embodiment of the voltage-controlled semiconductor switch.

For a more detailed explanation of the invention, reference is made to the drawing, in which several embodiments of the required Circuit arrangement according to the invention are schematically illustrated.

1 shows output characteristics of a non-latching, switchable power semiconductor switch

2 shows an advantageous embodiment of a circuit arrangement according to the invention. In FIG. 3, pass characteristics of the low and high blocking semiconductor switch of the cascode circuit according to FIG. 2 are shown

FIG. 4 shows a diagram over time t of the load current and the output voltages of the two semiconductor switches of the cascode circuit according to FIG. 2

5 shows a further advantageous embodiment of the circuit arrangement according to the invention.

2 shows an advantageous embodiment of a circuit arrangement according to the invention. This circuit arrangement has a cascode circuit 2, consisting of a series connection of a low and high blocking semiconductor switches 4 and 6, as a power semiconductor switch that can be switched off. In addition, this circuit arrangement also has a desaturation measuring circuit 8 and a control device 10. The desaturation measuring circuit 8 is linked on the input side by means of a decoupling diode 12 to a drain terminal D 'of the low-blocking semiconductor switch 4 of the cascode circuit 2 and on the output side to an input of the control circuit 10. On the output side, this drive circuit 10 is linked to the gate and source terminals G 'and S' of the low-blocking semiconductor switch 4 of the cascode circuit 2. A control signal U _S r from a control circuit, not shown in more detail, is present at the control input of the control circuit 10. In order to limit the current through the decoupling diode 12, the anode of this decoupling diode 12 is a voltage supply by means of a resistor R _GD with a positive supply voltage + U _V the control circuit 12 connected. As soon as the output voltage U _{D'S 'of} the low-blocking semiconductor switch 4 of the cascode circuit 2 is saturated, the decoupling diode 12 blocks and a current flows from the voltage supply (not shown in more detail) to the desaturation measuring circuit 8, which then generates an error signal S _F s. This error signal S _S causes the control circuit 10 to suppress the control signal U _S t _> which causes the low-blocking semiconductor switch 4 and the high-blocking semiconductor switch 6 of the cascode circuit 2 to be switched off.

In this advantageous embodiment of the circuit arrangement according to the invention, a hybrid power MOSFET is provided as the cascode circuit 2. This hybrid power MOSFET has a self-locking n-channel MOSFET, in particular a low-voltage power MOSFET, as a low-blocking semiconductor switch 4, and a self-conducting junction FET as a high-blocking semiconductor switch 6. This high blocking junction FET is also referred to as a junction field effect transistor (JFET). These two FETs are electrically connected in series such that the source terminal S of the junction FET is connected directly to the dram terminal D 'of the MOSFET and that the gate terminal G of the junction FET is connected to the source by means of a resistor R _G j -Connection S 'of the MOSFET are electrically connected. The low-blocking MOSFET of this cascode circuit 2 has an internal bipolar diode Dτ _.N , which is connected antiparallel to the MOSFET and is generally referred to as an inverse diode or internal freewheeling diode.

In a particularly advantageous embodiment of this cascode circuit, the normally-off n-channel MOSFET is made of silicon, whereas the normally-off n-channel JFET is made of silicon carbide. This hybrid power MOSFET is designed for a high reverse voltage of over 600 V and yet has only low losses in the pass band. This cascode circuit 2 is controlled by means of the gate voltage UQ _'S' of the normally-off MOSFET. If this MOSFET is switched on or the anti-parallel internal diode D _{N of} the MOSFET carries a current, then the dram voltage is U _D'S . of the MOSFET approximately zero. By coupling the gate connection of the JFET to the source connection S 'of the MOSFET, the gate voltage U _G s _{' of} the JFET is zero to little or negative. Thus, the largest drain current I _D flows through the JFET. If the MOSFET is switched off, the dram voltage U _{D '} s- increases until the maximum permissible reverse voltage of the MOSFET is reached. The value of the reverse voltage in a low-voltage power MOSFET is, for example, 30 V. As soon as the value of the dram voltage U _D. _{S 'of} the MOSFET exceeds the value of a dram voltage, the drain current I _{D of} the JFET is zero. That is, the JFET is turned off. By coupling the gate connection G of the JFET to the source connection S 'of the MOSFET, the dram voltage U _D. _S. of the MOSFET to the gate G of the JFET.

3 shows pass characteristics of the MOSFET and the JFET of the cascode circuit 2. It can be seen from these characteristics that only the output characteristic U _{D '} s _{' of} the low-blocking MOSFET can form the signal for short-circuit monitoring if the dielectric strength of the decoupling diode 12 is to be low. The high blocking JFET therefore does not have to be optimized for a low saturation current, which leaves freedom with regard to other optimization criteria, for example improved forward behavior. The low blocking MOSFET is a better compromise between low forward voltage and low

Desaturation current achievable, since in this case the channel resistance determines a larger part of the total resistance and the MOSFET contributes only a small part to the total forward voltage drop. This allows the short-circuit strength of high-blocking components that have the property only at currents that are much larger than yours Nominal current must be desaturated in order to achieve acceptable forward voltages.

FIG. 4 shows a switch-on process of the cathode circuit 2 according to FIG. 2 in more detail. According to this representation, the gate of the low-blocking MOSFET is charged at the time to by the level change of the control signal U _S f from "low" to "high". As a result, the drain voltage U _{D '} S _{' of} the low-blocking MOSFET drops very quickly. The MOSFET of the cascode circuit 2 is already in the saturated state at time ti. This very rapidly falling dram voltage U _{D '} s _{' of} the MOSFET is fed back as a control voltage to the gate of the JFET. The time range tι ~ t ₀ is so short that a load current I _D can only increase slightly in this range. Depending on the gate time constant of the JFET, which is formed from a gate-source capacitance and the resistor R _G J, also referred to as the gate resistor, the load current I _{D increases} to its stationary end value. The Dra source voltage U _{DS '} at the JFET then drops to its saturation value until time t ₃ .

When using conventional power semiconductors, such as, for example, IGBT, power MOSFET, bipolar transistor, the desaturation measuring circuit 8 must be masked out until time t ₃ . Since the length of the time range t ₃ -t ₀ also increases sharply both with the load current I _D and with the commutation voltage, the "worst case" including a safety reserve must always be observed for the fade-out time. In cascode circuit 2, voltage U _{D '} s _' at MOSFET is available as a signal for short-circuit detection from time ti. This is particularly advantageous in the event that the cascode circuit 2 switches on a short-circuited load.

5 shows a further advantageous embodiment of the circuit arrangement according to the invention. This embodiment differs from the embodiment according to FIG only in that instead of a JFET as a high-blocking semiconductor switch 6 em voltage-controlled semiconductor switch 14 is provided. When using a voltage-controlled semiconductor switch 14 as a high-blocking semiconductor switch 6 of the cascode circuit 2, the gate connection G of this voltage-controlled semiconductor switch 14 is connected to the source connection S ′ of the low-blocking semiconductor switch 4 of the cascode circuit 2 by means of a gate resistor R and a constant voltage source 16 connected. A DC voltage source, for example a battery of approximately 15 V, is used as the constant voltage source. The voltage-controlled semiconductor switch 14 can be, for example, an insulated gate bipolar transistor (IGBT), an MOSFET, an MOS-controlled thyristor (MCT),... Only an IGBT as a high-blocking semi-power switch 6 of the cascode circuit 2 is shown. By using a voltage-controlled semiconductor switch 14 as a high-blocking semiconductor switch 6 of the cascode circuit 2, nothing has changed in the functioning of this circuit arrangement.

Claims

claims

1. Circuit arrangement with a power semiconductor switch that can be switched off, a control circuit (10) and a desaturation measuring circuit (8), the control circuit (10) being linked on the output side to a gate terminal (G ') of the power semiconductor switch that can be switched off, the Desaturation measuring circuit (8) is connected by means of a decoupling diode (12) to a drain terminal of the power semiconductor switch and on the output side to an input of the control circuit (10), characterized in that a cascode circuit (2) is used as the power semiconductor switch that can be switched off. , consisting of a series connection of a low and high blocking semiconductor switch (4,6) that the desaturation measuring circuit (8) by means of the diode (12) with the dram connection (D ') of the low blocking semiconductor switch (4) of the cascode circuit (2nd ) is connected, and that the drive circuit (10) on the output side to the gate terminal (G ') of the low-blocking half it switch (4) of the cascode circuit (2) is linked.

2. Circuit arrangement according to claim 1, characterized in that the low-blocking semiconductor switch (4) em MOSFET and the high-blocking semiconductor switch (6) em JFET, wherein the gate terminal (G) of the JFET by means of a resistor (R _G ) with the source -Connection (S ') of the MOSFET is linked.

3. Circuit arrangement according to claim 1, characterized in that the low-blocking semiconductor switch (4) em MOSFET and the high-blocking semiconductor switch (6) em voltage-controlled semiconductor switch (14), wherein the gate terminal (G) of the voltage-controlled semiconductor switch (14) is linked to the source terminal (S ') of the MOSFET by means of a constant voltage source (16).

4. Circuit arrangement according to claim 3, characterized in that the voltage-controlled semiconductor switch (14) em Insu- 1ated-Gate-Bipolar-Translstör.

5. Circuit arrangement according to claim 3, characterized in that the voltage-controlled semiconductor switch (14) is a MOS-controlled thyristor.

6. Circuit arrangement according to one of claims 1 to 5, characterized in that the low-blocking semiconductor switch (4) made of silicon and the high-blocking semiconductor switch (6) consists of silicon carbide.