WO2000072444A2 - Scannable flip flop circuit and method of operating an integrated circuit - Google Patents
Scannable flip flop circuit and method of operating an integrated circuit Download PDFInfo
- Publication number
- WO2000072444A2 WO2000072444A2 PCT/US2000/011348 US0011348W WO0072444A2 WO 2000072444 A2 WO2000072444 A2 WO 2000072444A2 US 0011348 W US0011348 W US 0011348W WO 0072444 A2 WO0072444 A2 WO 0072444A2
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- WIPO (PCT)
- Prior art keywords
- input
- latch
- clock
- scan
- output
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0372—Bistable circuits of the master-slave type
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Definitions
- the present invention is related to U.S. Patent Applications No. 09/ (Atty.
- the present invention is related to radiation hardened integrated circuits and, more
- IC integrated circuit
- FET Field Effect Transistor
- CMOS complementary metal oxide semiconductor
- Radiation hardened storage elements latches are well known and are used, effectively, to reduce or eliminate SEE in space based IC registers, latches and other storage elements.
- radiation hardened storage elements can be referred to as radiation hardened latches
- level sensitive scan design (LSSD) latches were used in spaced-based
- Figure 1 is a block diagram of a
- the LSSD latch 100 includes a first stage 102 and a second
- the first stage 102 includes a serial input SCANIN (SI) 106 clocked by a clock A0 signal 108 and a data input DAT AIN (DI) 110 clocked by a clock CO signal 112.
- SI serial input SCANIN
- DI data input DAT AIN
- An output 114 of the first stage 102 is the input of the second stage 104 which is clocked by a clock B0
- An output DATAOUT 118 of the second stage 104 is an output P10 of the LSSD
- LSSD latches 100 are linked together serially to form several scan chains
- test data may be scanned in on one scan chain, at the input to the particular logic function and
- the logic function's response to the test data may be scanned out on another chain at the logic function's output.
- the data scanned out may be compared against an expected result and
- the CO and BO clock signals 112 and 1 16 are non- overlapping phases derived from the same system clock. During each clock cycle, data at
- data input DAT AIN 110 is latched in the first stage 102 when the CO clock signal 112 is driven high. Then, after the first stage latch 102 has set, the CO clock signal 112 is driven low. Next, the B0 clock signal 116 is driven high, passing the contents of the first stage 102
- test data is loaded into all of the scan chains, either individually or, several at a time.
- CO clock signal 112 is pulsed with a single pulse to clock the function output into first stage
- Edge-triggered latches set on the falling or rising edge of a single clock.
- Figure 2 illustrates a conventional scan d-flip-flop (scan dff) 200.
- flop 200 includes a 2: 1 multiplexer 202, which is coupled to a first level sensitive latch 204.
- the first level sensitive latch 204 is coupled to a second level sensitive latch 206.
- dff 200 is clocked by a clock signal 207.
- the clock signal 207 is split into complementary signals by inverting clock signal 207 with inverter 208.
- the complementary clock signals are
- first level sensitive latch 204 and second level sensitive latch 206 gating first and second pairs of pass gates 210, 212 and 214, 216, respectively.
- multiplexer 202 to the first pair of pass gates 210, 212 as complementary outputs 220, 222.
- pass gates 210, 212 are turned on so that data on
- complementary outputs 220, 222 are passed to first level sensitive latch 204 and, tentatively,
- the second pair of pass gates 214, 216 are contemporaneously turned off, and isolate the second level sensitive latch 206 from the
- clock signal 207 turns on the second pair of pass gates 214, 216 as the output of inverter 208 falls, simultaneously, to turn off the first pair of pass gates 210,
- the false clock pulse is a pulse perturbated by an SEE.
- this scan dff 200 is both incompatible with LSSD and is even more sensitive to SEE than LSSD latches. This increased sensitivity is because either the first level
- inverter 208 can clock the entire flip flop 200 or the second
- level sensitive latch 206 Furthermore, because an event occurring in the clock tree is, most of the events occurring in the clock tree is, most of the events occurring in the clock tree is, most of the events occurring in the clock tree is, most of the events occurring in the clock tree is, most of the events occurring in the clock tree is, most of the events occurring in the clock tree is, most of the events occurring in the clock tree is, most of the events occurring in the clock tree is, most of the events occurring in the clock tree is, most of events occurring in the clock tree is, most of events occurring in the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is, most of the clock tree is
- edge triggered logic also, is power constrained.
- a scannable register may be formed from the scannable flip flops.
- Each scannable flip flops can be radiation hardened.
- Each scannable flip flops can include a 2:1 input multiplexer, a first latch and a second latch.
- the multiplexer can be coupled to the first latch
- the pass gates can be gated by a clock signal (CO).
- CO clock signal
- a second clock signal (BO) can gate
- the clock signals can be non-overlapping and can be provided by a clock splitter that splits a chip clock into two individual clock phase signals.
- clock splitter combination can be employed as edge-triggered logic. Representing the LSSD
- testable circuit as an edge- triggered D-flip flop in ECAD tools permits logic synthesis and
- the resulting logic can operate as edge- triggered logic and can be tested using LSSD testing techniques and patterns.
- An example embodiment of the present invention includes an integrated circuit including an input multiplexer, a first latch selectively coupled to an output of the input multiplexer, a second latch selectively coupled to an output of the first latch, a first clock input signal selectively coupling the first latch to the input multiplexer output, and a second
- the input multiplexer is a 2: 1 input multiplexer.
- the input multiplexer includes a scan input signal and a data input signal.
- the first latch is coupled to the input multiplexer by a first pair of pass gates, the first pair of pass gates being gated by the
- first latch by a second pair of pass gates, the second pair of pass gates being gated by the second clock input signal.
- the second clock input signal is coupled to a second clock input signal of the at least one other flip flop.
- Another example embodiment of the present invention includes an integrated circuit including at least one scannable register, the at least one scannable register including a
- each of the plurality of flip flops including an input multiplexer, a first latch, a first pass gate pair selectively coupling an output of the input multiplexer to an input of the first latch, a second latch, and a second pass gate pair selectively coupling an output of
- first latch to an input of the second latch, a first clock input signal selectively coupling the input of the first latch to the output of the input multiplexer, and a second clock input signal non-overlapping and separate from the first clock input, selectively coupling the output of the
- the input multiplexer is a 2:1
- the input multiplexer includes a scan input and a data input, the plurality of flip flops being serially coupled into a scan string,
- register is one or more pairs of the scannable registers, a first of each of the pairs of scannable
- registers providing an input to a logic circuit and a second of each of the pairs of scannable
- registers receiving an output of the logic circuit.
- an integrated circuit In another example embodiment of the present invention, an integrated circuit
- each of the plurality of scannable registers including a plurality of latches, wherein each of the plurality of latches includes an input multiplexer selecting between a scan input and a data input, a first latch selectively coupled to an output of the input multiplexer responsive to the first clock input signal, the
- first latch storing a state of the output of the input multiplexer
- second latch selectively coupled to an output of the first latch responsive to the second clock input signal, the second latch storing a state of the output of the first latch and providing a latch output responsive to
- plurality of logic functions being one of the latch outputs from one of the plurality of
- the input multiplexer is a 2:1
- the plurality of latches being serially coupled into one or more scan strings, an output of a first of the plurality of latches of the scan string being coupled to a
- the circuit further includes a
- the flip flop including a 2:1 input multiplexer, a first pair of pass gates having inputs coupled to a pair of outputs of the 2:1 input multiplexer, a first latch having inputs coupled to outputs of the first pair of pass gates, a second pair of pass gates having inputs coupled to a pair of outputs of the first latch, a second latch having inputs coupled to outputs of the second pair of pass gates, a first clock input signal gating the first pair of pass
- the flip flop can operate as an edge-triggered flip flop.
- the first latch and the second latch are radiation hardened latches.
- the 2:1 input multiplexer In one example embodiment of the present invention the 2:1 input multiplexer
- the flip flop includes a scan input and a data input, the flip flop being serially coupled with additional of the flip flops into one or more scan strings, an output of a first the flip flop of each of the scan
- test pattern data is scanned into one of the scan strings
- test result data is scanned out on a second one of the scan strings.
- the flip flop when clocked by an
- SEU tolerant clock splitter can be represented as a scan d flip flop for ECAD logic synthesis.
- the integrated circuit having a test mode of operation and a functional mode of operation, the method including the steps of configuring the IC in its test mode and testing the
- the step of configuring the IC in its functional mode and providing a clock to an input to the IC, wherein single event upsets occurring in clock trees on the ICs are not propagated as clock pulses to latches on the IC.
- the step of configuring the IC in its functional mode and providing a clock to an input to the IC, wherein single event upsets occurring in clock trees on the ICs are not propagated as clock pulses to latches on the IC.
- test mode and testing includes selecting a scan input to one or more scannable registers
- the step of configuring the IC in functional mode includes configuring the scannable registers to select a data input, providing a clock to the IC, splitting the clock into
- Figure 2 is an example of a typical conventional scan d-flip-flop (scan dff);
- Figure 3 is an exemplary embodiment of a scannable hybrid flip flop
- Figure 4 A is a block diagram of an exemplary embodiment of a single event upset
- Figure 4B is an example timing diagram for the exemplary embodiment of the SEU
- Figure 5 A is an example of a cross-sectional view of an exemplary embodiment of an integrated circuit chip for space-based applications with LSSD testable logic between two exemplary scannable registers of hybrid flip flops of the present invention.
- Figure 5B is a timing diagram for the IC depicted in the cross-sectional view of Figure 5A.
- signal name in this application indicates that the signal is negative or inverse logic. Negative or inverse logic is considered active when the signal is low.
- Figure 3 is a schematic of a
- the scannable hybrid flip flop 300 can include a 2:1 multiplexer 302, a first level sensitive latch 304 and a second level
- Complementary outputs 308, 310 of 2:1 multiplexer 302 can be inputs to the first level sensitive latch 304 through pass gates 312, 314.
- Outputs 316, 318 of the first level sensitive latch 304 can be inputs to the second level sensitive latch 306 through pass
- Each level sensitive latch 304, 306 is clocked by non-
- Either data input DATAIN 1 10 or scan test data SCANIN 106 is passed through 2:1 multiplexer 302 depending on the state of selector input select 218.
- the outputs 308, 310 of 2:1 multiplexer 302 can be coupled to pass gates 312 and 314. Thus, when pass gates 312
- first independent clock signal PCO 324 the outputs 308, 310 of 2:1 multiplexer 302 are passed into first level sensitive latch 304. After storing data in the first level sensitive latch 304 the PCO clock signal 324 can be driven low to turn off pass
- the PB0 clock signal 326 can be driven high, which turns on pass gates 320 and 322, passing data into second level sensitive latch 306. As data is passed into
- second level sensitive latch 306 it, simultaneously passes out on output DATAOUT 118.
- 300 includes two independently clocked level sensitive latches 304, 306, the clock stages
- both LSSD clocks may not be high simultaneously. However, driving both clocks low simultaneously merely pauses flip flop operation. Thus, a false low pulse during a clock
- latches 304, 306 need only be hardened against SEE induced false high pulses.
- Figure 4A is a block diagram of an exemplary embodiment of a Single Event Upset (SEU) tolerant clock splitter circuit 400, as described in detail in U.S. Patent
- the SEU tolerant clock splitter circuit 400 by eliminating
- inverter 208 avoids the SEE sensitivity of the inverter 208 and avoids false pulses from SEUs
- the SEU tolerant clock splitter circuit 400 can include an event offset delay 402
- A0 406 and A0_DLY 410 are inputs to an inverting event blocking filter 414. Delayed clock output signals 408 and 412 are inputs to a second inverting event blocking filter 416.
- Event blocking filter 414 is enabled by an enable signal 434 and event blocking filter 416 is enabled by an enable signal 436.
- Inverting clock drivers 426 and 428 each provide one of a pair of
- Each of inverting event blocking filters 414 or 416 compares a respective undelayed clock output signal A0 406 or AON 408 with a corresponding delayed clock output signal
- each event blocking filter 414 or 416 provides pairs of inverted in-phase output signals 418, 420 and 422, 424, respectively.
- Output signal 420 from inverting event blocking filter 414 is passed as a
- output signal 424 from inverting event blocking filter 416 can be passed as a feedback input to inverting event blocking filter 414.
- Figure 4B is a timing diagram for the SEU tolerant clock splitter circuit 400 of Figure
- offset delay circuit 402 can be sized such that the delayed output signals A0_DLY 410 or
- A0N_DLY 412 can be delayed from signal A0 406 and AON 408, respectively, by t SEE ,
- the inverting clock drivers 426, 428 ignore a false low pulse signal on either inphase output of either of inverting event blocking filters 414, 416.
- the exemplary clock splitter 400 thereby avoids inadvertently driving the driver's PCO clock driver output
- the feedback input 420, 424 to event blocking filters 414, 416, respectively, must be high in order to drive the in-phase output clock signals 418, 420 and 422, 424 low. So, both
- event blocking filter output signal pairs 418, 420 and 422, 424 must be high before either signal pair can be driven low. Thus, when these in phase output signal pairs 418. 420 and 422, 424 are inverted by inverting clock drivers 426 and 428, respectively, the resulting pair
- Figure 5 A is a cross sectional view of an exemplary embodiment integrated circuit
- IC integrated circuit
- LSSD Level sensitive scan design
- Each register 502, 504, is clocked by
- an independent clock driver 506, 508 that includes one or more SEU tolerant clock splitter
- Each pair represents one or more pairs of clock splitter circuit outputs 430, 432.
- Input clock 522 is buffered and split in clock drivers 504, 506 and then passed as clock output pairs 510, 512 and 514, 516 to registers 502, 504, which are operating as scan dff registers.
- register 502 on inputs DI 0 -DI n 524. Data, latched in register 502 in the previous clock cycle,
- Register 504 passes out of register 502 on outputs DO 0 -DO n 526, propagating through logic 500 to inputs 528 of register 504. Register 504, in turn, is passing data that was latched in the previous
- FIG. 5B is a timing diagram of a typical LSSD test for the cross section of Figure
- the latches operate as LSSD latches.
- Latches in the register 502 are set, as represented by SELECT, to select a
- register 502 As a first-in first-out serial register.
- the SEU clock splitter enables E0, El are low.
- Enable E0 518 is driven high, individually,
- the enabled clocks 510, 512 clock register 502 to serially scan
- test data in on SC 0 534 (which is the SCANIN input for the scan chain) until test data is
- enable E0 518 is driven low to disable clocks 510, 512 and the latch data inputs are selected as represented by SELECT -.witching state. Then, enable El 520 is driven high to enable SEU clock splitters 400 in
- test phase 538 the SCANIN input 534 is selected again as represented by SELECT switching.
- the captured test results are serially scanned out on DO n .
- the entire logic 500 may be tested using ATPG or LSSD techniques, while operating normally as a scan dff design that has additional, normally unavailable SEE
- the exemplary embodiment hybrid design has eliminated the LSSD need for individual A0, CO clocks.
- D-flip flop 200 D-flip flop 200. Therefore the circuits 300, 400 in combination can be represented to ECAD logic synthesis and scan creation tools a d-flip flop 200. Therefore, the present invention hybrid flip flop 300 can be used in an automation process in combination with a
- clock splitter 400 permitting the use of the many standard logic synthesis algorithms and for
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU63341/00A AU6334100A (en) | 1999-04-30 | 2000-04-28 | Method and apparatus for a scannable hybrid flip flop |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13212199P | 1999-04-30 | 1999-04-30 | |
US60/132,121 | 1999-04-30 |
Publications (3)
Publication Number | Publication Date |
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WO2000072444A2 true WO2000072444A2 (en) | 2000-11-30 |
WO2000072444A3 WO2000072444A3 (en) | 2001-06-28 |
WO2000072444A9 WO2000072444A9 (en) | 2001-07-26 |
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PCT/US2000/011348 WO2000072444A2 (en) | 1999-04-30 | 2000-04-28 | Scannable flip flop circuit and method of operating an integrated circuit |
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AU (1) | AU6334100A (en) |
WO (1) | WO2000072444A2 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4602210A (en) * | 1984-12-28 | 1986-07-22 | General Electric Company | Multiplexed-access scan testable integrated circuit |
US4692634A (en) * | 1986-04-28 | 1987-09-08 | Advanced Micro Devices, Inc. | Selectable multi-input CMOS data register |
US5155432A (en) * | 1987-10-07 | 1992-10-13 | Xilinx, Inc. | System for scan testing of logic circuit networks |
EP0651566A1 (en) * | 1993-10-29 | 1995-05-03 | International Business Machines Corporation | Programmable on-focal plane signal processor |
-
2000
- 2000-04-28 AU AU63341/00A patent/AU6334100A/en not_active Abandoned
- 2000-04-28 WO PCT/US2000/011348 patent/WO2000072444A2/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4602210A (en) * | 1984-12-28 | 1986-07-22 | General Electric Company | Multiplexed-access scan testable integrated circuit |
US4692634A (en) * | 1986-04-28 | 1987-09-08 | Advanced Micro Devices, Inc. | Selectable multi-input CMOS data register |
US5155432A (en) * | 1987-10-07 | 1992-10-13 | Xilinx, Inc. | System for scan testing of logic circuit networks |
EP0651566A1 (en) * | 1993-10-29 | 1995-05-03 | International Business Machines Corporation | Programmable on-focal plane signal processor |
Non-Patent Citations (1)
Title |
---|
"HIGH-PERFORMANCE CMOS REGISTER" IBM TECHNICAL DISCLOSURE BULLETIN,US,IBM CORP. NEW YORK, vol. 33, no. 3B, 1 August 1990 (1990-08-01), pages 363-366, XP000124389 ISSN: 0018-8689 * |
Also Published As
Publication number | Publication date |
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AU6334100A (en) | 2000-12-12 |
WO2000072444A9 (en) | 2001-07-26 |
WO2000072444A3 (en) | 2001-06-28 |
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