AU6334100A - Method and apparatus for a scannable hybrid flip flop - Google Patents

Method and apparatus for a scannable hybrid flip flop

Info

Publication number
AU6334100A
AU6334100A AU63341/00A AU6334100A AU6334100A AU 6334100 A AU6334100 A AU 6334100A AU 63341/00 A AU63341/00 A AU 63341/00A AU 6334100 A AU6334100 A AU 6334100A AU 6334100 A AU6334100 A AU 6334100A
Authority
AU
Australia
Prior art keywords
scannable
flip flop
hybrid flip
hybrid
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU63341/00A
Inventor
Joseph A Hoffman
Joseph W. Yoder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lockheed Martin Corp
Original Assignee
Lockheed Corp
Lockheed Martin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lockheed Corp, Lockheed Martin Corp filed Critical Lockheed Corp
Publication of AU6334100A publication Critical patent/AU6334100A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
AU63341/00A 1999-04-30 2000-04-28 Method and apparatus for a scannable hybrid flip flop Abandoned AU6334100A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13212199P 1999-04-30 1999-04-30
US60132121 1999-04-30
PCT/US2000/011348 WO2000072444A2 (en) 1999-04-30 2000-04-28 Scannable flip flop circuit and method of operating an integrated circuit

Publications (1)

Publication Number Publication Date
AU6334100A true AU6334100A (en) 2000-12-12

Family

ID=22452577

Family Applications (1)

Application Number Title Priority Date Filing Date
AU63341/00A Abandoned AU6334100A (en) 1999-04-30 2000-04-28 Method and apparatus for a scannable hybrid flip flop

Country Status (2)

Country Link
AU (1) AU6334100A (en)
WO (1) WO2000072444A2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4602210A (en) * 1984-12-28 1986-07-22 General Electric Company Multiplexed-access scan testable integrated circuit
US4692634A (en) * 1986-04-28 1987-09-08 Advanced Micro Devices, Inc. Selectable multi-input CMOS data register
US5155432A (en) * 1987-10-07 1992-10-13 Xilinx, Inc. System for scan testing of logic circuit networks
US5449907A (en) * 1993-10-29 1995-09-12 International Business Machines Corporation Programmable on-focal plane signal processor

Also Published As

Publication number Publication date
WO2000072444A3 (en) 2001-06-28
WO2000072444A9 (en) 2001-07-26
WO2000072444A2 (en) 2000-11-30

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AU6334100A (en) Method and apparatus for a scannable hybrid flip flop

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase