WO2000070433A1 - A system and a method to reduce power consumption - Google Patents
A system and a method to reduce power consumption Download PDFInfo
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- WO2000070433A1 WO2000070433A1 PCT/US2000/012467 US0012467W WO0070433A1 WO 2000070433 A1 WO2000070433 A1 WO 2000070433A1 US 0012467 W US0012467 W US 0012467W WO 0070433 A1 WO0070433 A1 WO 0070433A1
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- 238000000034 method Methods 0.000 title claims abstract description 85
- 230000009467 reduction Effects 0.000 claims abstract description 93
- 210000003813 thumb Anatomy 0.000 claims abstract description 72
- 238000012545 processing Methods 0.000 claims description 14
- 238000012546 transfer Methods 0.000 description 14
- 230000008859 change Effects 0.000 description 6
- 230000007704 transition Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
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- 238000000844 transformation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to the field of computer processing systems and methods. More particularly, the present invention relates to a system and method to improve, that is to reduce, power consumption in advanced RISC machines (ARM) based systems. One way of handling this is by turning off certain features when operating in THUMB state.
- ARM advanced RISC machines
- Computer systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results.
- Computer systems typically include a processor that operates in accordance with a set of instructions.
- Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems include processors that have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment.
- the processors designed to provide these results are advanced RISC machines (ARM) that operate in accordance with a reduced instruction set computer architecture (RISC).
- RISC reduced instruction set computer architecture
- ARM processors deliver relatively high performance and offer significant flexibility through a very powerful instruction set.
- the relative simplicity of a typical ARM processor facilitates a high instruction throughput and efficient time interrupt response from a compact and cost effective device.
- Pipelining is utilized to enable multiple components of the processing and memory systems to operate at the same time. For example, while one instruction is being executed, a subsequent instruction is being decoded, and a third instruction is fetched from memory.
- One state or instruction set includes a 32-bit ARM set and another state or instruction set includes a 16-bit THUMB set.
- the THUMB set of instructions operates on the same 32-bit registers as the ARM set of instructions and achieves approximately twice the density of the ARM set while maintaining most of the ARM set performance advantages.
- a coprocessor is usually included in a system.
- An ARM coprocessor provides additional processing power in the ARM state. Often it is advantageous to have the coprocessor executing particular instructions while a main ARM processor is performing other functions. For example a coprocessor often performs functions such as floating point operations, graphics transformations, and image compression. However, in typical ARM systems with coprocessors, some of the coprocessor features are continuously maintained even though the coprocessor is not being utilized to process instructions or information.
- Coprocessors usually consume significant amounts of system power even though the coprocessor is not contributing to primary system operations.
- the coprocessor is not contributing to primary system operations during 16-bit THUMB transactions since a coprocessor is not used to perform 16-bit transactions.
- the THUMB instruction set is smaller than the ARM instruction set and while operating in the THUMB state the coprocessor in an ARM system is not utilized.
- the coprocessor continues to consume power even when the coprocessor is not processing instructions or information. For example the clock in the coprocessor continues to run and the coprocessor registers continue to switch state which consumes power.
- Reducing power consumption by components that are not contributing to the functionality of an ARM system offers many benefits. For example, power availability is often critical in wireless communication systems that utilize ARM systems to provide processing capabilities. Wireless communication systems often rely on batteries as a power supply and reducing power consumption results in longer battery life. Reducing power consumption also permits battery sizes to be reduced which permits smaller wireless communication devices to be produce. Compact wireless communication devices usually offer greater practical application utility.
- the system and method of the present invention reduces power consumption by coprocessors in an ARM system.
- the system and method does not interfere with the operational functionality of the ARM system.
- Coprocessor register switching during THUMB state operations is reduced by the present invention and the present invention also facilitates the reduction of power supply requirements.
- an ARM coprocessor power reduction system and method detects when an ARM system is engaging in activities that do not utilize an ARM coprocessor and turns off the ARM coprocessor clock.
- the ARM coprocessor power reduction system and method of the present invention tracks if the ARM core is engaging in ARM state or THUMB state operations.
- ARM coprocessor power reduction system and method analyzes a THUMB bit (TBIT) signal that indicates whether the ARM core is performing in an ARM state or THUMB state. If the ARM core is engaging in THUMB state operations the ARM coprocessor power reduction system and method of the present invention instructs a coprocessor clock to turn off. If the ARM core is engaging in ARM state operations the ARM coprocessor power reduction system and method of the present invention instructs a coprocessor clock to turn on.
- TBIT THUMB bit
- Figure 1 is one example of a coprocessor clock stop waveform table associated with one embodiment of an ARM coprocessor power reduction system and method of the present invention.
- Figure 2 is one example of a coprocessor clock start waveform table associated with one embodiment of an ARM coprocessor power reduction system and method of the present invention.
- Figure 3 is a schematic of an ARM coprocessor power reduction system, one embodiment of the present invention.
- Figure 4 is an illustration of an ARM coprocessor power reduction truth table for an ARM coprocessor power reduction system of the present invention.
- FIG. 5 is a flow chart of one embodiment of an ARM coprocessor power reduction method of the present invention. DETAILED DESCRIP ⁇ ON OF THE INVEN ⁇ ON
- the present invention is an ARM coprocessor power reduction system and method that detects when an ARM system is engaging in activities that do not utilize an ARM coprocessor and turns off the ARM coprocessor clock.
- the present invention tracks signals from the ARM core periphery to determine if the ARM core is attempting to facilitate ARM state or THUMB state operations. If the ARM coprocessor power reduction system and method of the present invention detects that the ARM core is attempting to facilitate THUMB state operations the ARM coprocessor power reduction system and method signals a clock associated with the ARM coprocessor to turn off. Since the ARM coprocessor clock is turned off the registers in the ARM coprocessor are not switching and consuming power. If the ARM coprocessor power reduction system and method of the present invention senses the ARM core is attempting to facilitate ARM state operations the ARM coprocessor power reduction system and method signals a clock associated with the ARM coprocessor to turn on.
- the ARM pipeline comprises a fetch stage, a decode stage and an execute stage.
- the ARM coprocessor power reduction system of the present invention tracks what stage a particular instruction is at in the ARM core (whether it is in fetch, decode or execute stage).
- a change in state of operation e.g., a change from ARM state to THUMB state or vice versa
- an instruction indicating the change flows though the ARM pipeline.
- the instruction is fetched, decoded and then in the execute stage the ARM core determines if the instruction is directing the ARM core to switch to a 16 bit THUMB instruction set or the 32 bit ARM instruction set.
- TBIT TSUMB Bit
- the state change instruction gets executed there are potentially two more operations to get executed pending in the pipeline, one operation in the fetch stage and one operation in the decode stage. If the operation state is changing from ARM state to THUMB state the ARM coprocessor power reduction system and method does not power off the ARM coprocessor clocks until the remaining two operations in the decode and execute stage are fully executed. Thus, if the remaining two operations in the decode stage and execute stage include ARM state operations the coprocessor has its clocks running and available to continue processing 32 bit ARM state operations.
- FIG. 1 is one example of a coprocessor clock stop waveform table 100 associated with one embodiment of an ARM coprocessor power reduction system and method of the present invention.
- Coprocessor clock stop waveform table 100 illustrates when first ARM instruction 110, second ARM instruction 111 and third ARM instruction 112 and their corresponding first ARM data transfer 120, second ARM data transfer 121 and third ARM data transfer 123 are fetched, the value in a CPSTOPC register is high indicating the coprocessor clock is running.
- first THUMB instruction 113 is fetched signal AC " TBIT transitions from a logical zero (low) to a logical one (high).
- signal CP_STOPC does not switch a logical zero (instructing the coprocessor clock to continue running) to a logical one (instructing the coprocessor clock to stop running).
- Signal CP_STOPC does not transition until second THUMB instruction 114 and third THUMB instruction 116 and their associated second THUMB data transfer 124 and third THUMB data transfer 126 are complete.
- Signal CP_STOPC even senses the extended processing duration indicated by the coprocessor absent instruction 115 and its associated coprocessor absent data transaction 125 between second THUMB data transfer 124 and third THUMB data transfer 126.
- the AC_TBIT signal remains at a logical one (high) for forth THUMB instruction 117, fifth THUMB instruction 118 and forth THUMB data transfer 127.
- the TBIT signal When an ARM system is exiting the THUMB state and going to the ARM state the TBIT signal will indicate (e.g., go low) it is processing ARM state operations.
- the coprocessor clock starts during the same cycle when the ARM system is exiting the THUMB state and going to the ARM state.
- the coprocessor is available to continue processing 32 bit ARM state operations if the next instruction that gets executed is a 32 bit ATM state operation.
- FIG. 2 is one example of a coprocessor clock start waveform table 200 associated with one embodiment of an ARM coprocessor power reduction system and method of the present invention
- Coprocessor clock stop waveform table 200 illustrates when first THUMB instruction 210, second THUMB instruction 211 and third THUMB instruction 212 and their corresponding first THUMB data transfer 220, second THUMB data transfer 221 and third THUMB data transfer 223 are fetched, the value in a CPSTOPC register is low indicating the coprocessor clock is not running.
- first ARM instruction 213 is fetched signal AC_TBH transitions from a logical one to a logical zero.
- Signal CP_STOPC transitions from a logical one to a logical zero instructing the coprocessor clock to start running.
- the value in the CPSTOPC register transitions from a logical zero to a logical one indicating the clock started running.
- the value in the CPSTOPC register remains at a logical one for second ARM instruction 214, third ARM instruction 215, first ARM data transfer 223, second ARM data transfer 224 and third ARM data transfer 225.
- the ARM core utilizes several signals to indicate progress and advancement through the stages of the ARM coprocessor pipeline follower.
- the not memory request signal (MREQ_N or nMREQ) indicates whether a memory access is required in the next cycle. If NMREQ is low the ARM core processor requires a memory access in the next cycle.
- the not op-code fetch signal (OPC_N or nOPC) indicates whether an ARM core processor is fetching an instruction from memory. If OPC_N is low the ARM core processor is fetching an instruction from memory and if OPC_N is high data is being transferred (if there is data present).
- the not wait (WAIT_N or nWAIT) signal is utilized to cause an ARM core to wait or stall for an integer number of memory clock input (MCLK) cycles.
- MCLK is a clock that times ARM core memory accesses and internal operations.
- WAIT_N is low the ARM core waits or is stalled.
- FIG. 3 is a schematic of ARM coprocessor power reduction system 300, one embodiment of the present invention.
- ARM coprocessor power reduction system 300 comprises THUMB bit register TBIT_PF 310, wait register WAIT_N_PF 321, first logic OR component 325, not op-code fetch register OPC _N_PF 327, third logic AND component 328, second logic AND component 329, data hold register DATA_HOLD_NF 331, multiplexer MUX 332, decode register DECODE_NF 333, execute register EXECUTE_NF 334, first logic AND component 340 and stop clock register STOPCLK_NF 345.
- Registers that include a PF in their identification comprise flip flops triggered by a positive going edge of a signal and registers that include a NF in their identification comprise flip flops triggered by a negative going edge of a signal.
- TBIT_PF 310 is coupled to first logic AND component 340.
- Third logic AND component 328 is coupled to WAIT_N_PF 321, first logic OR component 325, OPC_N_PF 327, and DATA_HOLD_NF 331.
- Second logic AND component 329 is coupled to WAIT_N_PF 321, first logic OR component 325, OPC_N_PF 327, DECODE_NF 333, and EXECUTE _NF 334.
- MUX 332 is coupled to DATA_HOLD_NF 331 and DECODE_NF 333 which is coupled to EXECUTE_NF 334.
- EXECUTE_NF 334 is coupled to first logic AND component 340 which is coupled to STOPCLK_NF 345.
- First logic AND component 340 is adapted to logically analyze input signals and provide a signal that turns on or off a coprocessor clock based upon the state of instructions in an ARM pipeline. For example, first logic AND component 340 provides a signal that turns off the coprocessor clock if instructions in the ARM pipeline are THUMB state instructions and turns on the coprocessor clock if an instruction in the ARM pipeline is an ARM state instruction.
- THUMB bit register TBIT_PF 310 stores a logical value of a THUMB bit (TBIT) signal that indicates whether an instruction in an ARM pipeline is operating in a THUMB state or ARM state.
- Execute register EXECUTE_NF 334 stores information associated with an execution stage of said ARM pipeline.
- Second logic AND component 329 controls advancement of instructions and data through the ARM pipeline.
- Logic OR component 325 transmits a logical one value if an input (e.g., a not memory request signal (MREQ_N and a not op-code fetch signal OPC_N) to logic OR component 325 is a logical 1 and a logical zero if said input to logic OR component 325 is a logical zero.
- Wait register WAIT_N_PF 321 captures a value of a not wait signal (e.g., WAIT_N).
- Third logic AND component 328 transmits a signal directing stored data to be forwarded in the ARM pipeline.
- Data hold register DATA_HOLD_NF 331 stores data waiting to be processed in the ARM pipeline.
- _ Not op-code fetch register OPC_N_PF 327 stores the status of a not op-code fetch signal that indicates whether an ARM core processor is fetching an instruction from memory.
- Decode register DECODE_NF 333 stores information associated with a decode stage of the ARM pipeline.
- Multiplexer MUX 332 selects a signal to transmit to said decode register, such as a signal from a data hold register or from a data in signal.
- ARM instruction pipeline logic examines the information in WAIT_N_PF 321, and logical status of signals OPC_N and MREQ SF to determine when to latch instructions from an ARM system data bus through various ARM core registers. TBIT value from the previous rising edge is sampled and sent along with the data which is moving towards decode and execute stages. This enables ARM coprocessor power reduction system 300 to properly start/stop the coprocessor clock.
- Figure 4 is an illustration of ARM coprocessor power reduction truth table 400.
- ARM coprocessor power reduction truth table 400 is the truth table for ARM coprocessor power reduction system 300.
- the ARM core is fetching an instruction.
- the instruction itself is put on the ARM core data bus at the following falling edge of the clock.
- the instruction remains on the ARM core data bus and no instructions are moved between DATA_HOLD_NF 331, multiplexer MUX 332, decode register DECODE_NF 333, or execute register EXECUTE _NF 334 if the value stored in WAIT_N_PF is a logical zero.
- OPC_N_PF If the information in OPC_N_PF is a logical 0, then the instruction on the ARM data bus is put in DATA_HOLD_NF 331 and is in an "on-hold" status. During the remaining states of ARM coprocessor power reduction truth table 400 instructions are moving through stages of the pipeline. If the information in WAIT_N_PF 321 is a logical one and the OPC_N signal is a logical zero and the MREQ_N signal is a logical zero at the falling edge of the clock, the ARM core moves a current instruction to the decode stage. The status of the information in OPC_NPF 327 determines which instruction is moved to the decode stage.
- OPC_N_PF 327 If the information in OPC_N_PF 327 is a logical one then the instruction in DATA_HOLD_NF 331 is moved to the decode stage because the instruction in DATA_HOLD_NF 331 didn't go through decode stage yet. If the information in OPC_N_PF 327 is a logical zero, then the instruction on the ARM data bus is put in REGISTER DECODE_NF 333 for decoding. If the value in WAIT_N_PF 321 is a logical 1 and signal OPC_N is a logical zero and signal MREQ_N is a logical zero at the falling edge of the clock, the contents of register DECODE_NF 333 flows to register EXECUTE_NF 334 for execution.
- First logic AND component 340 transmits a logical one value if its inputs, the value stored in TBIT PF 310 and the TBIT of the value stored in EXECUTE_NF 343 are a logical one and a logical zero value if any of the inputs are a logical zero value.
- the logical values transmitted by First logic AND component 340 are temporarily stored in STOPCLK_NF 345 and then forwarded as signal CLKSTOP to the coprocessor clock. If CLKSTOP is a --,_,-..,, 0/70433
- FIG. 5 is a flow chart of ARM coprocessor power reduction method 500, one embodiment of the present invention.
- ARM coprocessor power reduction method 500 establishes if an ARM system is engaging in activities that do not utilize an ARM coprocessor and reduces power consumption by the ARM coprocessor.
- ARM coprocessor power reduction method 500 inspects signals from an ARM core periphery to determine if the ARM core is attempting to facilitate ARM state or THUMB state operations. If ARM coprocessor power reduction method 500 detects the ARM core is attempting to facilitate THUMB state operations, ARM coprocessor power reduction method 500 signals a clock associated with the ARM coprocessor to turn off.
- ARM coprocessor power reduction method 500 establishes that the series of instructions in an ARM pipeline are all THUMB state operations ARM coprocessor power reduction method 500 causes the coprocessor clock to turn off. Since the ARM coprocessor clock is turned off the registers in the ARM coprocessor are not switching and consuming power.
- Step 510 ARM coprocessor power reduction method 500 determines if an ARM core is fetching a THUMB state instruction. In one embodiment, ARM coprocessor power reduction method 500 checks if the ARM processor 0433
- ARM coprocessor power reduction method 500 captures the logical state of a TBIT signal associated with the instruction being fetched. For example, ARM coprocessor power reduction method 500 scans a not memory request signal (MREQ_N or nMREQ), a not op-code fetch signal (OPC_N or nOPC) and a not wait signal (WAIT_N or nWAIT) to determine if an ARM core is fetching an instruction. In one example a logical zero (low) TBIT signal indicates an ARM state instruction and a logical one (high) TBIT signal indicates a THUMB state instruction. After ARM coprocessor power reduction method 500 determines if the ARM core is fetching a THUMB state instruction, ARM coprocessor power reduction method 500 proceeds to Step 520
- ARM coprocessor power reduction method 500 continues normal ARM core and coprocessing procedures in Step 520 ARM.
- ARM coprocessor power reduction method 500 continues normal ARM core and coprocessing procedures by moving an instruction from the fetch stage to the decode stage and advancing the instruction on to the execution stage.
- ARM coprocessor power reduction method 500 tracks the state of following instructions being processed in the ARM pipeline.
- ARM coprocessor power reduction method 500 stores the logical value of a TBIT signal in a TBIT register (e.g., TBIT_PF 210). In one exa ple the TBIT value is stored when an instruction is moved from the fetch stage into the decode stage of the pipeline.
- Step 540 ARM coprocessor power reduction method 500 analyzes if it is appropriate to turn off a coprocessor clock.
- ARM coprocessor power reduction method 500 it is appropriate to turn off a coprocessor clock if ARM coprocessor power reduction method 500 establishes the instructions being processing in an ARM pipeline are THUMB state instructions or data associated with a THUMB state instruction. For example, if THUMB state instruction or data associated with the THUMB state instructions are occupying the stages of the ARM pipeline it is appropriate to turn off the coprocessor clock. If it is not appropriate to turn off a coprocessor clock ARM coprocessor power reduction method 500 loops back to step 520. If it is appropriate to turn off a coprocessor clock ARM coprocessor power reduction method 500 proceeds to step 550.
- ARM coprocessor power reduction method 500 turns off the coprocessor clock. In one embodiment of the present invention ARM coprocessor power reduction method 500 transmits a signal to the coprocessor clock to stop.
- ARM coprocessor power reduction method 500 examines if it is appropriate to turn on a coprocessor clock. In one embodiment of ARM coprocessor power reduction method 500 it is appropriate to turn on a coprocessor clock if ARM coprocessor power reduction method 500 ascertains an instruction in an ARM pipeline is an ARM state instruction or data associated with an ARM state instruction. For example, if an ARM state instruction or data associated with the ARM state instruction is occupying an ARM pipeline register it is appropriate to turn on the coprocessor clock. In one embodiment, ARM coprocessor power reduction method 500 continues to monitor a TBIT signal associated with instruction fetches after the coprocessor clock is turned off.
- ARM coprocessor power reduction method 500 interprets a TBIT value of logical zero to indicate the associated instruction fetch is an ARM state instruction fetch. If a following fetch is an ARM state instruction then it is appropriate to turn on the coprocessor clock. If it is not appropriate to turn on a coprocessor clock ARM coprocessor power reduction method 500 loops back to step 550. If it is appropriate to turn on a coprocessor clock ARM coprocessor power reduction method 500 proceeds to step 570.
- step 570 ARM coprocessor power reduction method 500 switches on a coprocessor clock and loops back to step 510.
- ARM coprocessor power reduction method 500 establishes in step 540 if an instruction being processing in an ARM pipeline are THUMB state instructions or data associated with a THUMB state 70433
- ARM coprocessor power reduction method 500 if a stored wait value (e.g., WAIT_N_PF 221) is a logical one and both an OPC_N signal and a MREQ---N signal are a logical zero, ARM coprocessor power reduction method 500 compares the TBIT associated with an instruction in a pipeline execute register (e.g., EXECUTE_NF 234) and a stored TBIT value in a TBIT register (e.g., TBIT_PF 210).
- a stored wait value e.g., WAIT_N_PF 221
- a stored TBIT value in a TBIT register e.g., TBIT_PF 210.
- both the TBIT associated with an instruction in a pipeline execute register e.g., EXECUTE_NF 234
- a stored TBIT value in the TBIT register e.g., TBITJPF 210
- ARM coprocessor power reduction method 500 does not stop the coprocessor clock.
- the system and method of the present invention reduces power consumption by coprocessors in an ARM system.
- the system and method does not interfere with the operational functionality of the ARM system.
- Coprocessor register switching during THUMB state operations is reduced by the present invention and the present invention also facilitates the reduction of power supply requirements.
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP00930452A EP1099151B1 (en) | 1999-05-18 | 2000-05-08 | A system to reduce power consumption |
DE60034526T DE60034526T2 (en) | 1999-05-18 | 2000-05-08 | System for reducing energy consumption |
JP2000618810A JP4632279B2 (en) | 1999-05-18 | 2000-05-08 | System and method for reducing power consumption |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/313,933 US6438700B1 (en) | 1999-05-18 | 1999-05-18 | System and method to reduce power consumption in advanced RISC machine (ARM) based systems |
US09/313,933 | 1999-05-18 |
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WO2000070433A1 true WO2000070433A1 (en) | 2000-11-23 |
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PCT/US2000/012467 WO2000070433A1 (en) | 1999-05-18 | 2000-05-08 | A system and a method to reduce power consumption |
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US (1) | US6438700B1 (en) |
EP (1) | EP1099151B1 (en) |
JP (1) | JP4632279B2 (en) |
CN (1) | CN100485584C (en) |
DE (1) | DE60034526T2 (en) |
WO (1) | WO2000070433A1 (en) |
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EP1338956A1 (en) * | 2002-02-20 | 2003-08-27 | STMicroelectronics S.A. | Electronic data processing apparatus, especially audio processor for audio/video decoder |
EP1372065A2 (en) * | 2002-05-30 | 2003-12-17 | NEC Electronics Corporation | System large scale integrated circuit (LSI), method of designing the same, and program therefor |
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WO2002046894A2 (en) * | 2000-11-13 | 2002-06-13 | Intel Corporation | Processor idle state |
WO2002046894A3 (en) * | 2000-11-13 | 2003-08-21 | Intel Corp | Processor idle state |
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EP1372065A2 (en) * | 2002-05-30 | 2003-12-17 | NEC Electronics Corporation | System large scale integrated circuit (LSI), method of designing the same, and program therefor |
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Also Published As
Publication number | Publication date |
---|---|
CN1318165A (en) | 2001-10-17 |
EP1099151A1 (en) | 2001-05-16 |
CN100485584C (en) | 2009-05-06 |
JP2002544618A (en) | 2002-12-24 |
US6438700B1 (en) | 2002-08-20 |
DE60034526D1 (en) | 2007-06-06 |
DE60034526T2 (en) | 2007-11-22 |
JP4632279B2 (en) | 2011-02-16 |
EP1099151B1 (en) | 2007-04-25 |
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