CN101593287B - Power consumption balancing method of smart card - Google Patents

Power consumption balancing method of smart card Download PDF

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Publication number
CN101593287B
CN101593287B CN 200810113122 CN200810113122A CN101593287B CN 101593287 B CN101593287 B CN 101593287B CN 200810113122 CN200810113122 CN 200810113122 CN 200810113122 A CN200810113122 A CN 200810113122A CN 101593287 B CN101593287 B CN 101593287B
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power
consumption
card
smart
invention
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CN 200810113122
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Chinese (zh)
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CN101593287A (en )
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包乌日吐
李自然
郑晓光
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北京中电华大电子设计有限责任公司
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Abstract

The invention discloses a power consumption balancing method of a smart card, being mainly applied to the field of power consumption optimization of smart card design. The invention adopts a starting waiting mechanism so as to realize smooth transition of power consumption of a card in the switching process of a main controller and a coprocessor, so that overlarge power consumption caused by power consumption superposition can be effectively solved.

Description

一种智能卡功耗平衡方法 An intelligent power card balance method

技术领域 FIELD

[0001] 本发明主要应用于智能卡设计的功耗优化领域。 [0001] The present invention is mainly applied power to optimize the field of smart card design. 背景技术 Background technique

[0002] 随着计算机软件技术和集成电路的不断发展,智能卡的应用越来越广泛,从手机SIM卡到金融业的银行卡和身份认证,智能卡在发挥着重要作用。 [0002] With the development of computer software technology and integrated circuits, smart card applications more widely, from the mobile phone SIM card to the financial sector and bank card authentication, smart card plays an important role. 目前对于智能卡低功耗设计方面的技术有很多,通常用到的有Clock_Gating、Multi_VDD、Multi_Vth等,其中Clock_ Gating应用最广泛也比较容易实现,后两者需要工艺库的支持。 There are techniques for low-power design of many smart cards, commonly used have Clock_Gating, Multi_VDD, Multi_Vth, of which the most widely used Clock_ Gating is relatively easy to implement, the latter two processes need to support the library. 智能卡系统的日益复杂对功耗设计也提出了更高的要求,不仅仅是在低功耗,还包括功耗平衡。 The increasing complexity of smart card system power design but also put forward higher requirements, not only in low-power, also includes power balance.

[0003] 本发明所公开的智能卡功耗平衡方法,从系统的角度去考虑功耗平衡的实现。 [0003] The smart card power balancing method disclosed in the present invention, from the perspective of the system to consider the balance of power. 本发明通过软硬件配合实现主控制器和协处理器切换过程中的功耗平稳过渡。 The present invention is implemented with hardware and software by the coprocessor and the host controller during the power switch smooth transition.

发明内容 SUMMARY

[0004] 本发明旨在通过智能卡软硬件协同来实现功耗平衡,具体包含以下步骤: [0004] The present invention aims to achieve a synergistic power is balanced by the smart card hardware and software, particularly comprising the steps of:

[0005] 本发明实现智能卡功耗平衡,具体有以下步骤: [0005] The present invention realizes a smart card power balance, specifically the following steps:

[0006] (1)主控制器开启协处理器启动等待机制,在配置阶段主控制器需要开启协处理器启动等待机制,当协处理器启动运算时首先会检查此控制,若有效,从收到启动命令开始延时一段时间等到主控制器真正进入节电模式后才开始启动运算操作。 [0006] (1) the main controller switches the coprocessor mechanism start wait, wait to start the coprocessor need to open the configuration phase the master controller mechanism, when the operator starts the coprocessor will first check this control, if effective, from the received command to start the beginning of a period of delay until after the main controller really started to conserve power arithmetic operations.

[0007] (2)主控制器启动协处理器运算。 [0007] (2) the main controller starts the coprocessor arithmetic.

[0008] (3)主控制器进入节电模式,由于主控制器发完协处理器启动命令之后才能进入节电模式,因此主控制器的进入节电模式操作和协处理器的延时操作是并行操作。 [0008] (3) the main controller enters the power saving mode, since the main controller coprocessor finished to enter the power saving mode after a start command, and thus enters the power saving mode of the main controller coprocessor latency operation parallel operation.

[0009] (4)协处理器等待机制启动,当主控制器启动协处理器运算时,首先协处理器等待机制开始工作并判断是否等待延时。 [0009] (4) wait for the coprocessor to start the mechanism, when the main controller starts the coprocessor arithmetic, the coprocessor waits first begin working mechanism determines whether latency.

[0010] (5)协处理器开始运算。 [0010] (5) starts the coprocessor arithmetic.

[0011] 主控制器通过启动等待控制机制来控制协处理器启动时是否等待延时。 [0011] The main controller controls the coprocessor control mechanism is waiting to start at startup latency. 在协处理器启动时插入硬件延时,使主控制器和协处理器的功耗不产生叠加,整个芯片的功耗平稳过渡。 When inserted into the coprocessor hardware delay start, the main controller and the power superposition no coprocessor, the power consumption of the whole chip smooth transition.

附图说明 BRIEF DESCRIPTION

[0012] 图1主控制器和协处理器硬件框图 [0012] FIG. 1 and the host controller hardware block diagram of the coprocessor

[0013] 图2操作流程 [0013] The operation flow in FIG. 2

具体实施方式 detailed description

[0014] 如图1所示,主控制器和协处理器的配合实现功耗平衡需要以下几个控制,等待延时控制、启动控制、协处理器运算结束等。 [0014] As shown, with the main controller 1 and the coprocessor realization requires the following power balance control, latency control, startup control, the end of the coprocessor operation and the like.

[0015] 下面结合图2对本发明进行详细描述,本发明所述的功耗平衡方法包括以下几个步骤: [0015] FIG. 2 below in connection with the present invention will be described in detail, the method of balancing the power consumption of the present invention comprises the following steps:

[0016] (1)主控制器开启协处理器启动等待机制。 [0016] (1) the main controller switches the coprocessor start wait mechanism.

[0017] (2)主控制器启动协处理器运算。 [0017] (2) the main controller starts the coprocessor arithmetic.

[0018] (3)主控制器进入节电模式。 [0018] (3) the main controller enters the power saving mode.

[0019] (4)协处理器等待机制启动。 [0019] (4) wait for the coprocessor to start mechanism.

[0020] (5)协处理器开始运算。 [0020] (5) starts the coprocessor arithmetic.

[0021] 主控制器开启协处理器启动等待机制:在配置阶段主控制器需要开启协处理器启动等待机制,当协处理器启动运算时首先会检查此控制,若有效,从收到启动命令开始延时一段时间等到主控制器真正进入节电模式后才开始启动运算操作。 [0021] The main controller switches the coprocessor start wait mechanism: In the configuration phase the master controller needs to turn on the coprocessor start wait mechanism, when the operator starts the coprocessor will first check this control, when active, a start command from start delayed for some time to wait until the master controller really started to conserve power arithmetic operations.

[0022] 主控制器启动协处理器运算:主控制器发出启动运算命令来启动协处理器运算。 [0022] The main controller starts the coprocessor arithmetic: the master sends the start command to start the coprocessor arithmetic operations.

[0023] 主控制器进入节电模式:由于主控制器发完协处理器启动命令之后才能进入节电模式,因此主控制器的进入节电模式操作和协处理器的延时操作是并行操作。 [0023] The main controller enters the power saving mode: As the main controller coprocessor finished to enter the power saving mode after the start command, so the operation proceeds to delay operation of the power saving mode and the coprocessor is master controller operating in parallel .

[0024] 协处理器等待机制启动:当主控制器启动协处理器运算时,首先协处理器等待机制开始工作并判断是否等待延时。 [0024] Mechanism of the coprocessor waits for start: when the main controller starts the coprocessor arithmetic, the coprocessor waits first begin working mechanism determines whether latency.

[0025] 协处理器开始运算:协处理器等待主控制器进入节电模式后才真正启动运算。 [0025] Coprocessor operation starts: the coprocessor waits for the main controller enters the power saving mode after the operation really started.

[0026] 为了控制芯片整体的功耗,主控制器支持软件在协处理器运算期间让主控制器进入节电状态。 [0026] In order to control the overall power consumption of chips, the main controller software support during the coprocessor arithmetic allow the main controller enters the power saving state. 主控制器必须先执行启动协处理器运算命令再进入节电模式。 The main controller must perform arithmetic coprocessor command to start re-enter the power saving mode. 为了防止在切换过程中主控制器和协处理器同时工作而功耗过大(功耗叠加),加入了等待机制使协处理器模块在收到运算命令后是否还需等待主控制器进入节电模式才真正启动运算。 In order to prevent the main controller and the work while the coprocessor power dissipation (power superposition), was added to make the waiting mechanism coprocessor module after receiving the operation command if the need to wait for the master controller enters in the handover process section electric mode only really started operation. 一旦等待机制开启,协处理器运算在主控制器进入节电模式后才真正启动。 Once the waiting open mechanism, the coprocessor calculation actually started after the master controller enters the power saving mode. 运算完成后,主控制器自动退出节电模式,并继续执行下一条指令。 After the completion of the operation, the main controller automatically exits the power saving mode, and executes the next instruction. 当主控制器对协处理器发启动运算命令后,协处理器根据等待控制机制是否开启来判断等待延时与否。 When the master issues a command to start operation to the coprocessor, the coprocessor control mechanism according wait latency is determined whether or not to open. 如果不需等,硬件立即开始工作; 如果需要等待,则一直等到等待延时结束(即主控制器完全进入节电模式)后,硬件才会开始启动运算。 If you do not need other hardware to begin work immediately; if you need to wait, then wait until the end of latency (ie, the main controller fully into the power-saving mode), the hardware will be started operations.

[0027] 通过本发明公开的智能卡功耗平衡方法,使卡在主控制器和协处理器切换过程中实现功耗平稳过渡,有效解决了功耗叠加引起的功耗过大问题。 [0027] The power balance of the smart card by the method disclosed in the present invention, the power consumption to achieve a smooth transition so that the card host controller and a coprocessor handover process, power consumption effectively solve the problem is too large due to superposition.

Claims (1)

  1. 一种智能卡功耗平衡方法,其特征在于包括以下步骤:(1)主控制器开启协处理器启动等待机制,在配置阶段主控制器开启协处理器启动等待机制,当协处理器启动运算时首先会检查主控制器是否开启协处理器启动等待机制,若有效,从收到启动命令开始延时一段时间等到主控制器真正进入节电模式后才开始启动运算操作;如果不需等待,协处理器硬件立即开始工作;(2)主控制器启动协处理器运算;(3)主控制器进入节电模式,由于主控制器发完协处理器启动命令之后才能进入节电模式,因此主控制器的进入节电模式操作和协处理器的延时操作是并行操作;协处理器等待机制启动,当主控制器启动协处理器运算时,首先协处理器等待机制开始工作并判断是否等待延时;(4)协处理器开始运算。 An intelligent card power balancing method, comprising the steps of: (1) the main controller switches the coprocessor mechanism start wait, wait to start opening the coprocessor configuration phase the master controller mechanism, when the operator starts the coprocessor first checks the master controller is turned coprocessor start wait mechanism, if effective, from receiving a start command to start the period of delay until after the main controller really started to conserve power arithmetic operations; if no waiting, Association processor hardware to work immediately; (2) the main controller starts the coprocessor arithmetic; (3) the main controller enters the power saving mode, since the main controller coprocessor finished to enter the power saving mode after a start command, thus the main delay operation and enter a power save mode of operation of the coprocessor controller is operating in parallel; wait for the coprocessor to start the mechanism, when the main controller starts the coprocessor arithmetic, the coprocessor waits mechanism first starts and determines whether to wait for the extension of the work time; (4) starts the coprocessor arithmetic.
CN 200810113122 2008-05-28 2008-05-28 Power consumption balancing method of smart card CN101593287B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6438700B1 (en) 1999-05-18 2002-08-20 Koninklijke Philips Electronics N.V. System and method to reduce power consumption in advanced RISC machine (ARM) based systems
CN1512295A (en) 2002-12-26 2004-07-14 上海华虹集成电路有限责任公司 Power saving processing method of non-contact IC card receiving and transmitting signal
CN101145080A (en) 2007-11-07 2008-03-19 威盛电子股份有限公司 Computer system and computer system power management method
CN101174176A (en) 2006-11-03 2008-05-07 北京中电华大电子设计有限责任公司 Low-power dissipation SOC circuit and method based on orderly-control

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6438700B1 (en) 1999-05-18 2002-08-20 Koninklijke Philips Electronics N.V. System and method to reduce power consumption in advanced RISC machine (ARM) based systems
CN1512295A (en) 2002-12-26 2004-07-14 上海华虹集成电路有限责任公司 Power saving processing method of non-contact IC card receiving and transmitting signal
CN101174176A (en) 2006-11-03 2008-05-07 北京中电华大电子设计有限责任公司 Low-power dissipation SOC circuit and method based on orderly-control
CN101145080A (en) 2007-11-07 2008-03-19 威盛电子股份有限公司 Computer system and computer system power management method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2002-164841A 2002.06.07

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