WO2000067538A1 - Method for manufacturing solderless high density electronic modules - Google Patents

Method for manufacturing solderless high density electronic modules Download PDF

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Publication number
WO2000067538A1
WO2000067538A1 PCT/FI2000/000327 FI0000327W WO0067538A1 WO 2000067538 A1 WO2000067538 A1 WO 2000067538A1 FI 0000327 W FI0000327 W FI 0000327W WO 0067538 A1 WO0067538 A1 WO 0067538A1
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Prior art keywords
technique
microcircuits
components
active
fabπcation
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PCT/FI2000/000327
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French (fr)
Inventor
Jorma Kalevi Kivilahti
Arni Kujala
Risto Tuominen
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Jorma Kalevi Kivilahti
Arni Kujala
Risto Tuominen
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Publication date
Application filed by Jorma Kalevi Kivilahti, Arni Kujala, Risto Tuominen filed Critical Jorma Kalevi Kivilahti
Priority to AU39701/00A priority Critical patent/AU3970100A/en
Priority to EP00918922A priority patent/EP1104647B1/en
Publication of WO2000067538A1 publication Critical patent/WO2000067538A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Definitions

  • the flat surface of polymer is normally roughened p ⁇ or to the activation step Depending on the properties of the polymer the roughening can be made by employing chemical, mechanical, elect ⁇ cal or thermal treatments The surface is roughened for achieving adequate adhesion of the deposited metal to the polymer The roughened substrate surface and the openings or (I/O) pads of microcircuits are activated The activation is earned out with a catalyst Typically colloidal tin- palladium solution is used as a catalyst for the electroless copper solution Palladium is the catalyst for the oxidation/reduction reaction and the tin protects the palladium from the oxidation The activated surface is electncally non-conductiv e

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

The invention relates to a fabrication method and technique for producing functional devices where active and/or passive components are embedded and interconnected during the substrate fabrication process. It is characteristic for the invention that the active and passive components are embedded into low-cost polymer substrates, preferably flexible, and interconnected using photodefinable dielectrics and the electroless copper deposition. Besides embedding passive components they can be fabricated using dielectrics and electroless deposition processes. The fabrication is carried out at ambient temperatures without vacuum-based processes like evaporation or sputtering. It is also an important advantage of the invention that wire bonding or soldering are not needed, since the latter interconnection techniques will meet increasing difficulties with higher frequencies and smaller interconnection volumes. The interconnections of active components produced with a technique according to the present invention are electrically very good and their mechanical reliability is superior to those produced with the existing techniques.

Description

Method for manufacturing solderless high density electronic modules
This invention relates to a manufacturing method of electronic devices which combines the solderless fabπcation of reliable high
Figure imgf000003_0001
interconnections between active and passive components, packaging and manufacturing of structural substrate
Continually increasing functionality of integrated circuits - especially higher signal transmission rates, lower operating voltages and smaller line widths in integrated circuits - imposes increasing demands on the physical and chemical compatibility between dissimilar materials in electrical contacts as well as on manufactunng technologies T erefore, the reliability of the most advanced electronics is becoming one of the most important factors in limiting electrical performance The reliability of electronics is especially important in portable products, because these high performance products with ever higher packaging densities experience - in addition to their operational stresses - various environments Moreover, the usage of new environmental-fhendly matenals and processes set additional requirements to the reliability of electronics On the other hand, shorter time-to-market cycles increase the reliability risk, because regardless of more effective R&D cycles especially new matenals and manufactunng technologies demand careful evaluation and testing of products
When producing ever higher density and higher performance electronic devices, more fundamental limitations are also being encountered the solutions to which will alter presently used matenals and manufacturing techniques For example, increasing I/O densities and smaller conductor widths of microcircuits require thinner metallizations and smaller interconnection volumes, and therefore higher current densities or interfacial chemical reactions between thin matenal layers, which are difficult to control, increase the failure nsk of electronic products Correspondingly, the increase m the wiring densities of printed circuit boards decreases the solder joint volumes, when the BGA and CSP components and especially Flip Chip assemblies are being used in greater extent Hence, harmful effects of relative large fractions of brittle mtermetalhc compounds and impurities become stronger in the microjouits being under larger shear strains, the fact that decreases the reliability significantly
"Flip Chip (FC)" technique, in which bare, non-encapsulated semiconductor chips are interconnected directly onto substrate, resembles BGA and CSP techniques, where interconnection bumps generally made of SnPb solder alloy are also under component However, microcircuit is not encapsulated and the bump pitch is smaller - typically below 250 μm Due to the smallness of bumps the accuracy of assembh machines must be very high regardless of the self alignment effect of molten solder balls For the same reason underfill material is always used to protect the microcircuit, when the substrate material is FR4 or comparable In addition to diminishing the stress peaks, the underfill protects the microcircuit from harmful effects of moisture and contaminations The underfilling requires, however, additional process steps and thereby increases processing costs Besides perfect underfilling becomes ever more difficult with smaller solder bumps and increasing bump densities The testing and repair must be earned out before the underfilling, because after the cure of the underfill the microcircuit cannot be removed from the substrate Flip chip assembly requires also high quality printed winng boards
With increased interconnection densities both bare and encapsulated semiconductor chips are getting closer to the substrate surface which adds to shear strains and so increases the failure πsk of a component board assembled with surface mount technology The situation is also especially problematic due to low metallurgical stability of very small solder joints and large mismatch between the coefficients of thermal expansion of the substrate and silicon Despite the underfilling the solder joints may crack during testing
One of the most significant obstacles to the adoption of CSP packages and Flip Chip technique is the availability of low-cost and high density printed wiring boards Presently so-called additive pπnted wiring board manufacturing technologies are most promising, although they are relatively expensive However, these technologies offer significant advantages in improving the reliability of rmcrojoints as well as m embedding passπ e and active components It is expected that the line widths of integrated circuits will decrease well below 0 1 μm before the year 2010 Correspondingly, the contact areas or (l/0)'s pads on the chip will decrease below 10 μm, when the number of interconnections increases and interconnection volumes decrease strongly In such a situation the attention will be paid to the metallurgical stability of small solder joints and to the fabncation of pπnted winng boards, because the production of contact areas of 10 μm in order of magnitude sets very high requirements for the development of pπnted winng board technology
New environmental regulations and consumers increasing awareness of environment issues dnve electronics manufactunng towards lead-free and no-clean solutions Therefore new matenals and manufactunng technologies are adopted, which mav affect also the reliability of electronics Lead is a harmful element to human beings and therefore the use of lead is banned or restncted in many applications The electronics industry is employing lead above all in solder alloys and in protective coatings on components and printed winng boards
Presently there is no drop-m replacement for the eutectic tin-lead solder alloys in electronics manufactunng, although some very promising alternatives have been developed Lead-free solders having the best mechanical properties are tin-nch alloys which have small amounts of alloying elements Therefore their melting points are 30-50 °C higher than those of the most common tin-lead solders, that will change also the component assembly processes Likewise, the usage of lead-free surface finishes on pπnted winng boards will change the assembly processes Along with the lead-free issue much attention is being paid to the environmental causes of fluxes and other chemicals used in soldenng Surface mount technology being based on so-called no- clean soldering is very much alike to conventional surface mount technology except for the cleaning of flux residues The development of no-clean processes is also dπven by the expectations of lower production costs The removal of the cleaning process from the production line reduces equipment, chemical, labor and waste disposal costs This is, however, possible only if the no-clean assembly process can be executed reliably
Hence, the need to enhance concurrently the reliability, performance and economy of electronics manufactunng dnves the integration of manufactunng technologies Similarly, continuously decreasing size and increasing number of passive components on the printed winng board dnves to integrate the components into the substrate Especially manufacturers of consumer electronics are interested in integration of passive components into the substrate In this way more space is left for other discrete components In addition to the increased packaging density, l e larger sihcon-to-substrate ration, the manufacturing process is simplified But also active components can be embedded into printed winng boards
Integration of microcircuits into pπnted winng board with so-called "chip firsf'-techmque is one of the methods to solve the problems related to interconnecting high density microcircuits In this method a microcircuit is connected to the substrate before the winng and electπcal contacts are formed
The patents US 5353195, US 5353498. US 5422513 and US 5497033 present solutions to problems related to high density component interconnections In the methods presented in these patents the microcircuits are attached to ceramic or polymeπc substrates When microcircuits are integrated into the ceramic substrate, cavities being slightly larger than the microcircuits are formed so that the top surfaces of the microcircuits are on the same level with the ceramic substrate T e cavities can be formed by mechanical or laser drilling or by casting the substrate into a mould Microcircuits are attached to the cavities with an adhesive from the backside of the circuits, after which the gap between the microcircuits and the substrate is cast with a ceramic or polymer matenal After this a polyimide film is laminated onto the substrate surface and the vias to the microcircuits are formed through the polyimide film by laser dπlling The winng is produced with the semiadditive technique, in which the surface of the substrate is sputtered with a metal or alloy, and this is followed by the electrochemical plating of the conductors Because of the nonplananty of the substrate surface the exposure of the photoimageable resist is made with laser When microcircuits are integrated into polymeπc substrate, the microcircuits are aligned onto a thin polymer film This is followed by casting of the microcircuits into the epoxy by using a casting mould The properties of the epoxy are improved by filling the polymer with glass or ceramic particles, mostly with silica particles The epoxy must have good mechanical durability, low shrinkage, similar CTE with silicon, and it must be compatible also with other matenals used After casting the component is detached from the mold and the vias are formed through the thin polymer film with the laser dπlling The winng structure on the component surface is also produced with the semiadditive technique
According to the above-mentioned patents the manufactunng of electncal contacts to the microcircuits and the winng on the substrate requires the field metallisation which is produced by sputtering before the electrolytic plating The sputtering technique demands the use of vacuum, which makes the process time-consuming, expensive and restncts the size of the substrate Moreover, the perfect coverage of the complicated surfaces is difficult and m some applications it requires the use of elevated temperatures In mass production the repeated use of vacuum decreases the throughput of the process The size of the vacuum chamber restncts the size and number of the substrates to be sputtered simultaneously The semiadditive method requires the coating of several thin metal layers (for example, adhesion layers) Consequently, there are several interfaces between dissimilar metallisations which present potential reliability nsk. In the semiadditive manufactunng of the winng structure the excess panel plating is etched away The etching process sets limitations to the minimum line width which can be fabπcated It also produces toxic wastes The pnncipal objective of the present invention related to manufactunng reliable high density electronics is to provide a new technique and method without the drawbacks of the techniques and methods of the known art The interconnections and microjoints manufactured by using the technique and method of the present invention are electπcally. mechanically and chemically supeπor to those produced with the techniques of the known art Passive components that are connected to active components can be fabπcated by using the technique of the present invention
In the following the embodiments of the present
Figure imgf000007_0001
and its benefits in comparison to the fabncation techniques of the previous art are described
The fully additive fabncation technique of the present invention is simpler to execute, it is more cost-effective and it can be used to eliminate the disadvantages related to the techniques of the known art With the technique and method of the present invention a package of one active component or integrated functional modules with one or several active and passive components can be fabncated Microcircuits of vanous thickness can be embedded into a single module board so that the active surface of the components are at the same level with the substrate Copper, nickel or gold can be used as a pad metallisation for the embedded microcircuits When copper (I/O) pads on integrated circuits are used copper-to-copper interconnections can be fabπcated with the invented fully additive active component embedding and interconnection technique In such a case the interconnections are made solely of copper
More specifically the present invention concerning the solderless fabncation technique and method are charactensed by what is stated in the novelty parts of the claims
Several advantages are achieved with the fully additive active component embedding technique as compared the techniques of the known art The fully additive active component embedding technique does not require metal etching at am process step The interconnections are fabncated at ambient temperatures using w et-chemical. electroless deposition process The composition of the electroless baths can be refreshed during the deposition process, thus enabling a long service life and producing only a small amount of bath residuals The fully additive embedding technique of microcircuits includes only a few process steps Therefore, the technique is reliable, cost- effective and simple to use Both single large area components and several small area components can be interconnected simultaneously with the technique Copper conductors and copper-to-copper electπcal contacts can be fabπcated with the invented technique Consequently, there is the perfect metallurgical compatibility between contact metals and therefore the problems related to small interconnections produced with the techniques of the known art can be eliminated The fabncation process does not require vacuum or high processing temperatures dunng the fabncation of the interconnections As a matter of fact, the technique and method of the present invention combines the three presently separate manufactunng processes substrate or PWB manufacturing, active component packaging and the fabπcation of the interconnections into one simple, reliable and cost-effective fabncation process Because the electπcal interconnections are fabncated using chemical deposition, soldenng is not needed This gives significant benefits when manufactunng reliable electπcally functional high density interconnections
Figure 1 shows schematically an integrated module board fabπcated with the technique of the present invention This example presents the cross-section of a "pπnted winng board" or module board containing three interconnection levels The active components (1) are embedded into the substrate (2) so that the opening of the active components (3) are visible The conductors for the active components openings (4) are fabncated using the fully additive build-up technique of the present invention
In the following a simple example of integrated module boards which can be fabπcated with the invented fully additive component embedding and interconnection technique is presented
Phase 1
The microcircuits or active components (1) are embedded into a substrate (2) so that the open (I/O) pads of the components (3) are visible, while the rest of the active components are molded inside polymer substrate
Phase 2
The flat surface of polymer is normally roughened pπor to the activation step Depending on the properties of the polymer the roughening can be made by employing chemical, mechanical, electπcal or thermal treatments The surface is roughened for achieving adequate adhesion of the deposited metal to the polymer The roughened substrate surface and the openings or (I/O) pads of microcircuits are activated The activation is earned out with a catalyst Typically colloidal tin- palladium solution is used as a catalyst for the electroless copper solution Palladium is the catalyst for the oxidation/reduction reaction and the tin protects the palladium from the oxidation The activated surface is electncally non-conductiv e
Phase 3
The conductor structure is defined by using a permanent photodefinable polymer dielectnc in the photolithographic process Typically the photolithographic process is divided into the four processing steps coating, exposure, development and the curing Dunng the exposure step the properties of the photodefinable polymer are modified so that the polymer can be dissolved selectively Dunng the development step the activated surface (2) is uncovered under the photodefinable polymer for the electroless copper deposition in the phase 4
Phase 4
Electroless copper is deposited on the uncovered areas of the substrate and on the I/O's of the microcircuit After the complex chemical reactions the copper ions are deposited onto the activated surface The copper deposition process is autocatalytic (or self-catalytic)
Electroless copper deposition is slower than that of the electrochemical copper The deposition rates for electroless copper are typically 2-3 μm per hour, which makes it easy to control the deposited copper thickness The deposition rate can be adjusted with the deposition temperature, which is typically somewhat higher than room temperature The conductivity of the copper can be increased with the increasing thickness
The above-descπbed fabπcation steps or phases 2 - 4 are repeated several times for fabncating a desired multilayer structure with all the electπcal interconnections (In Fig 1 the phases are repeated three times)
In addition to the above-descπbed fabπcation process, all its vanations where alternative chemicals and different conductor metals than copper are used for fabncating integrated multilayer module boards belong to the scope of the present invention

Claims

Claims
1 Manufactunng process for electncally functional devices or modules, where the contact areas of microcircuits are interconnected using lithographic processes and semiadditive build-up techniques, wherein the fabncation method and technique compnses that embedded microcircuits and passive components are processed and interconnected solderlessly into electncally functional devices or modules with the fully additive buildup substrate fabncation technique
2 A fabπcation method according to claim 1 wherein the fabπcation process is compπsed of the following steps
- Phase 1 One or several microcircuits are embedded into substrates so that the electncal contact areas of the components remains visible,
- Phase 2 The surfaces of roughened substrates and the contact pads of the microcircuits or passives are activated,
- Phase 3 Conductor patterns on the activated surfaces are fabπcated using the photolithographic processing,
- Phase 4 Concurrent fabπcation of conductors and interconnections using the electroless copper deposition
3 A technique according to one of the claims 1 - 2 wherein the electncal mterconnections of bumped or bumpless active or passiv e components are fabncated at ambient temperatures and under atmosphenc pressure
4 A technique according to one of the claims 1 - 3 wherein the fabπcation of conductors and their interconnections do not require metal etching
PCT/FI2000/000327 1999-04-16 2000-04-17 Method for manufacturing solderless high density electronic modules WO2000067538A1 (en)

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AU39701/00A AU3970100A (en) 1999-04-16 2000-04-17 Method for manufacturing solderless high density electronic modules
EP00918922A EP1104647B1 (en) 1999-04-16 2000-04-17 Method for manufacturing solderless high density electronic modules

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FI990862 1999-04-16
FI990862A FI990862A (en) 1999-04-16 1999-04-16 New electronics joints without production technology

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US9966361B1 (en) * 2016-11-04 2018-05-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
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US10312194B2 (en) 2016-11-04 2019-06-04 General Electric Company Stacked electronics package and method of manufacturing thereof
US10553556B2 (en) 2016-11-04 2020-02-04 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10700035B2 (en) 2016-11-04 2020-06-30 General Electric Company Stacked electronics package and method of manufacturing thereof
US10770444B2 (en) 2016-11-04 2020-09-08 General Electric Company Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10497648B2 (en) 2018-04-03 2019-12-03 General Electric Company Embedded electronics package with multi-thickness interconnect structure and method of making same

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EP1104647A1 (en) 2001-06-06
EP1104647B1 (en) 2013-01-23
FI990862A0 (en) 1999-04-16
FI990862A (en) 2000-10-17

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