WO2000057551A1

WO2000057551A1 - Circuit arrangement for producing a voltage with a ramp-type time history

Info

Publication number: WO2000057551A1
Application number: PCT/EP2000/001715
Authority: WO
Inventors: Karlheinz Panzer
Original assignee: Mannesmann Rexroth Ag
Priority date: 1999-03-18
Filing date: 2000-03-01
Publication date: 2000-09-28
Also published as: DE19912112A1

Abstract

The invention relates to a circuit arrangement for producing a voltage with a ramp-type time history between a first voltage value and a second voltage value according to the temporal modification of an input voltage. The circuit arrangement has an integrator with an input which is subjected to a voltage. Said voltage depends on the difference between the input voltage and the output voltage of the integrator. In known circuit arrangements of this type, the ramp time is modified by a modification of a resistance in the input arm of the integrator. In order to verify the ramp time, the resistance value must be measured, or the time function of the output voltage must be evaluated after a jump in the input voltage. In order to simplify the determination of the ramp time, a voltage limiting circuit is connected in series to the integrator which limits the voltage that is supplied to said integrator to a value predetermined by an adjustable control voltage. The ramp duration can be determined by measuring the control voltage. The circuit arrangement is particularly suitable as a ramp generator for input signals of electrical amplifiers for controlling proportional valves for liquid media.

Description

description

Circuit arrangement for generating a voltage with a ramp-shaped course over time

The invention relates to a circuit arrangement for generating a voltage with a ramp-shaped time profile according to the preamble of claim 1.

Circuit arrangements of this type have been manufactured and sold by Mannesmann Rexroth GmbH as a component of electrical amplifiers for controlling proportional valves. Such an amplifier is e.g. B. in data sheet RE 29904 / 04.98 "Electrical amplifier - Type VT 2000, Series 5X" from Mannesmann Rexroth AG.

FIG. 1 shows the basic circuit diagram of a circuit arrangement that is part of the prior art for generating a voltage with a ramp-shaped course over time. Such a circuit arrangement is referred to below as a ramp generator. The input voltage supplied to the ramp generator is designated Uein. The output voltage of the ramp generator is designated Uaus. In the event of a sudden change in the voltage Uein from a first voltage value U1 to a second voltage value U2, the voltage U follows from the voltage Uein according to a ramp-shaped course over time. The voltages Uein and Uaus are fed to a comparator circuit 1 as input voltages. The comparator circuit 1 outputs a signal dependent on the difference between the voltages Uein and Uaus out. The relationship between the difference in the input voltages of the comparator circuit 1 and its output voltage is shown as a characteristic in block 1. The characteristic curve shows a three-point behavior, ie the output voltage of the comparator circuit 1 takes on only three different values depending on the difference between the voltages U in and U out supplied to it. In practice, there is a steep transition from a constant negative voltage to a constant positive voltage in the region of the zero point. The comparator circuit 1 is followed by an integrator 2. The integrator 2 contains an operational amplifier 3, in whose input branch an adjustable resistor 4 and in the feedback branch a capacitor 5 is arranged. The output of the comparator circuit 1 is connected via a diode 6 to a negative reference voltage -Uref and via a diode 7 to a positive reference voltage + Uref. The forward voltages of the diodes 6 and 7, ie the voltages that drop across the diodes 6 and 7 when the current flows, are practically constant. In the following they are referred to as Ud. The positive and negative supply voltages of the comparator circuit 1 are larger in magnitude than the corresponding reference voltages + Uref and -Uref. As long as the voltage U in is greater than the voltage U out, current flows from the negative reference voltage -Uref via the diode 6 and the output of the comparator circuit 1 to the negative supply voltage. The output voltage of the comparator circuit 1 adjusts to the value - (Uref + Ud). This voltage is fed to the integrator 2 as a fixed input voltage. The integrator 2 effects a sign reversal between in a manner known per se Input voltage and output voltage. As long as the voltage - (Uref + Ud) is present at the input of the integrator 2, the voltage Uout increases linearly with a slope corresponding to

Ramp time U100%

TR = χ T0

Uref + Ud, where U100% is the standardized maximum input voltage and TO is the time constant of integrator 2. The time constant of integrator 2 is TO = R4 x C5.

R4 and C5 denote the resistance value of the resistor 4 or the capacitance of the capacitor 5. When the voltage Uout has reached the voltage Uein, the output voltage of the comparator circuit 1 assumes the value zero. As long as the voltage zero is supplied to the integrator 2, the voltage Uout remains constant. If the voltage Uein is now reduced, the voltage Uaus is greater than the voltage Uein. Current now flows from the positive supply voltage via the output of the comparator circuit 1 and the diode 7 to the positive reference voltage + Uref. The output voltage of the comparator circuit 1 adjusts to the value Uref + Ud. This voltage is fed to the integrator 2 as a fixed input voltage. Because of the sign reversal between the input voltage and the output voltage of the integrator 2, the voltage Uout decreases linearly with an increase corresponding to the ramp time TR until it has reached the voltage Uein again. The ramp time TR is in ^{^"the"} voltage Vout has reached after a jump of voltage Vin by 100% the new value the time. This time is determined by the voltage supplied to the input of the integrator 2 and by the time constant T0 of the integrator 2 certainly. If the voltage Uref + Ud and the capacitance C5 are known, the ramp time TR can be calculated from the resistance value R4 of the adjustable resistor 4. If the adjustable resistor 4 is provided with an adjustment scale, the respectively set resistance value R4 can be read off the adjustment scale. Such resistors with setting scale, especially in a multi-course version, are voluminous and expensive. Another possibility for determining the ramp time TR is a measurement of the resistance value R4 of the adjustable resistor 4. Such a measurement is complex since the resistance measurement would have to be carried out on a resistor built into a circuit. In addition, the flux voltage Ud of the diodes 6 and 7, which is assumed to be constant above, is not constant in practice, but is influenced, among other things, by specimen scatter or by the ambient temperature. Another possibility of determining the ramp time is to record and evaluate the transition function of the voltage Uout after a jump in the voltage Uein. Although this method can be used to determine the size of a set ramp time TR, setting the ramp time TR to a specific value requires a number of attempts until this value is reached.

The invention has for its object to provide a circuit arrangement of the type mentioned that allows the ramp time to be determined in a simple manner.

This object is achieved by the features characterized in claim 1. Since the ramp time according to the invention by the level of a control voltage is determined, the ramp time can be easily determined by measuring the control voltage. The control voltage can either be used to check the set ramp time or be carried out simultaneously with the setting of the ramp time.

Advantageous developments of the invention are characterized in the subclaims. The measurement of the control voltage is simplified if the control voltage is related to the reference potential of the circuit arrangement. In a preferred embodiment of the invention, the control voltage is tapped at the tap of a voltage divider supplied by a reference voltage source. If several voltage dividers are connected to the reference voltage source, several, preferably different, voltages are present at the taps of the voltage dividers. If these voltages are fed to the control input of the limiting circuit in succession via a controlled switch, program-controlled ramp-like profiles with different slopes can be implemented. By using multi-turn potentiometers, a sensitive setting of the ramp time is possible. Since the ramp time is set via the voltage tapped at the potentiometer, multi-turn potentiometers without a scale can be used, which can be arranged to save space. In a special embodiment of the

Voltage limiting circuit uses the same control voltage for rising and falling ramps. The invention is explained in more detail below with its further details using exemplary embodiments shown in the drawings. Show it

FIG. 1 shows a circuit arrangement that is part of the prior art for generating a voltage with a ramp-shaped course over time,

Figure 2 shows a first circuit arrangement for generating a voltage with a ramp shape according to the invention in a schematic representation and

Figure 3 shows a second, compared to the circuit arrangement shown in Figure 2 expanded circuit arrangement for generating a voltage with a ramp-shaped course according to the invention.

The same components are provided with the same reference symbols in the figures.

FIG. 2 shows a schematic representation of a first circuit arrangement for generating a voltage with a ramp-shaped course according to the invention. A voltage circuit Uein and the output voltage Uaus of an integrator 2 are supplied to a comparator circuit 1 as input voltages. The structure and mode of operation of the comparator circuit 1 and the integrator 2 have already been described in detail above in connection with FIG. 1. According to the invention in FIG. 2 there is a voltage limitation between the output of the comparator circuit 1 and the input of the integrator 2. Circuit 8 arranged. The voltage supplied to the integrator 2 is referred to below as Ui. The voltage limiting circuit 8 limits the voltage Ui to a value that can be set by a control voltage Ust if the amount of the voltage supplied to the voltage limiting circuit 8 is greater than the control voltage Ust. If the magnitude of the voltage supplied to the voltage limiting circuit 8 is less than the control voltage Ust, the voltage limiting circuit 8 is not effective; the voltage supplied to it is directly connected to the input of the

Integrators 2 forwarded. This is e.g. B. the case when the voltage Uout is equal to the voltage Uein. In this case, the output voltage of the comparator circuit 1 is zero. As described above, the operational amplifier 3 together with the resistor 4 in the input branch and the capacitor 5 in the feedback branch forms the integrator 2. The time constant TO of the integrator 2 is equal to R4 x C5. Since the time constant TO is predetermined by the resistor 4 and the capacitor 5, the ramp time TR is changed via the voltage Ui supplied to the integrator 2. This voltage depends on the difference between the voltages Uein and Uaus. It can take three different values. If the voltages Uein and Uaus are the same, the output voltage of the comparator circuit 1 is zero. If the voltage Uout deviates from the voltage Uein, a voltage is present at the output of the comparator circuit 1 which is greater in magnitude than the control voltage Ust, the sign of this voltage depending on which of the voltages Uein and Uaus is greater. The circuitry complexity can be kept low if the output voltage of the comparator circuit 1 the positive and the negative supply voltage of the comparator circuit 1 are used. Fluctuations in the supply voltage - provided the supply voltage does not drop below the greatest value that the control voltage Ust can assume - are irrelevant, since the level of the voltage Ui is determined by the control voltage Ust. A voltage divider 11 formed from two resistors 9 and 10 is connected to a reference voltage Uref. The partial voltage drop across the resistor 9 is fed to the control input of the voltage limiting circuit 8 as the control voltage Ust. The control voltage Ust is related to ground potential. A measuring socket 12 is connected to the common circuit point of the resistors 9 and 10. It is used to measure the control voltage Ust. The ramp time TR results from the relationship

U100% TR = TO x

VAT

If the division ratio of the voltage divider 11 is denoted by x, the result is when the voltage divider is not loaded

Control voltage at Ust = x x Uref, where the divider ratio x can assume values between 0 and 1. The relationship then applies to the ramp time

T0 U100% TR = x. x Uref

FIG. 3 shows the circuit arrangement of a further ramp generator according to the invention. FIG. 3 shows in particular details of the structure of the comparator circuit 1, the integrator 2 and the voltage limiting circuit Σ and details of the arrangement for setting the control voltage Ust.

The comparator circuit 1 contains an operational amplifier 13 and two resistors 14 and 15. In principle, the resistors 14 and 15 are not required. They are used for

Improvement in signal quality. For this purpose, the resistor 15 is chosen to be much larger than the resistor 14. The resistor 14 limits the energy supplied to the operational amplifier 13 in the event of EMC interference. The inverting input of the operational amplifier 13 is supplied with its output voltage via the resistor 15 and the voltage Uein via the resistor 14. The voltage Uout is supplied to the non-inverting input of the operational amplifier 13. In the area in which the voltage Uout is approximately equal to Uein, there is a steep transition in the output voltage of the comparator circuit 1 from the constant negative voltage to the constant positive voltage or from the constant positive voltage to the constant negative voltage.

The voltage limiting circuit 8 contains a resistor 16 which is connected between the output of the comparator circuit 1 and the input of the integrator 2. The voltage limiting circuit 8 contains a first circuit part 17, which limits a positive output voltage of the comparator circuit 1 to the positive value of the control voltage Ust and “a second circuit part 18, which limits a negative output voltage of the comparator circuit 1 to the negative value of the control voltage Ust. The outputs of the circuit parts 17 and 18 are connected via a line 19 connected to the input of the integrator 2. The circuit part 17 contains an operational amplifier 20 and a diode 21. The voltage Ust is fed to the non-inverting input of the operational amplifier 20. The output voltage of the operational amplifier 20 is supplied to the inverting input of the operational amplifier 20 via the diode 21. The circuit part 18 contains an operational amplifier 22, a diode 23 and two resistors 24 and 25 of the same size. The control voltage Ust is fed to the inverting input of the operational amplifier 22 via the resistor 24. The output voltage of the operational amplifier 22 is supplied via the diode 23 and the resistor 25 to the inverting input of the operational amplifier 22.

If the output voltage of the comparator circuit 1 is positive and greater than the control voltage Ust, the voltage supplied to the inverting input of the operational amplifier 20 is greater than the voltage Ust supplied to its non-inverting input. The output voltage of the operational amplifier 20 is negative at the first moment, current flows through the diode 21 and the voltage Ui adjusts itself to be equal to the voltage Ust. In the steady state, the output voltage of the operational amplifier 20 is lower than the voltage Ust by the forward voltage of the diode 21. The voltage Ui is also supplied to the resistor 25. Since the voltage Ust is supplied to the resistor 24, the voltage Ust is also supplied to the inverting input of the operational amplifier 22. Since the non-inverting input of operational amplifier 22 is at ground potential the output voltage of the operational amplifier 22 is negative and the diode 23 blocks.

If, on the other hand, the output voltage of the comparator circuit 1 is negative and larger in magnitude than the control voltage Ust, the voltage supplied to the inverting input of the operational amplifier 20 is also negative. The control voltage supplied to the non-inverting input of operational amplifier 20 is positive. The output voltage of the operational amplifier 20 is positive in this case and the diode 21 blocks. The inverting input of the operational amplifier 22 is supplied with the positive control voltage Ust via the resistor 24 and the negative voltage Ui via the resistor 25. Since the voltage Ui is initially greater in magnitude than the control voltage Ust, the voltage supplied to the inverting input of the operational amplifier 22 is slightly negative. In the first moment, this leads to a positive output voltage of the operational amplifier 22. Current flows through the diode 23 and the voltage Ui is set such that the potential of the inverting input of the operational amplifier 22 is equal to the ground potential. Since the resistors 24 and 25 are the same size, the voltage Ui is set to the value -Ust. In the steady state, the output voltage of the operational amplifier 22 is greater than the voltage Ui by the forward voltage of the diode 23, which in this case is equal to the negative value of the control voltage Ust.

The limiting circuit 8 is designed so that it has a positive voltage to one with the same control voltage Ust positive value, namely Ui = + Ust, and a negative voltage is limited to a negative value of the same amount, namely Ui = -Ust. No particular demands are made on the accuracy of the output voltage of the comparator circuit 1, in particular on the temperature constancy.

A correction circuit 26 is arranged between the non-inverting input of the operational amplifier 3 of the integrator 2 and ground potential and supplies a correction voltage to the non-inverting input of the operational amplifier 3. The correction voltage is used for offset correction and for balancing the positive and negative ramp times of deviations, in particular due to tolerances of components of the limiting circuit 8.

To generate the control voltage Ust, three potentiometers 27, 28, 29 are provided in FIG. 3, which are connected to a constant one

Voltage Uref are connected. The voltages Ustl = xl x Uref, Ust2 = x2 x Uref or Ust3 = x3 x Uref are present at the taps of the potentiometers 27, 28, 29 in accordance with the divider ratios designated xl, x2 and x3. The taps of the potentiometers 27, 28, 29 are with a

Switch 30 and connected to measuring sockets 31, 32 and 33. The switch 30 selects one of the control voltages Ustl, Ust2, Ust3 as a function of a control signal which is fed to the control input denoted by the reference numeral 34 and supplies it to the one input of a maximum value selection circuit 35. A minimum control voltage Ustmin tapped off at the voltage divider 11 is fed to the other input of the maximum value selection circuit 35. The minimum control voltage Ustmin determines the greatest ramp time of the ramp builder. The maximum value selection circuit 35 supplies the input of the voltage limiting circuit 8 with the largest of the voltages supplied to it as the control voltage Ust. The maximum value selection ensures that even in cases in which a voltage tapped at the potentiometers 27, 28 or 29 is less than the voltage Ustmin or in which the switch 30 is open, the voltage Ust supplied to the voltage limiting circuit 8 Voltage does not fall below Ustmin. The voltage Ust is measured at the measuring socket 12. The series connection of a resistor 36 and a capacitor 37 is connected between the input of the voltage limiting circuit 8 and ground potential. The measuring socket 12 is connected between the resistor 36 and the capacitor 37. The resistor 36 and the capacitor 37 filter the control voltage Ust during the measurement. As described above, the voltage measured at the measuring socket 12 is a measure of the effective ramp time TR of the ramp generator. The measuring sockets 31, 32, 33 allow the setting of voltage values for different ramp times in advance. With the switch 30, selected control voltages can be supplied to the input of the voltage limiting circuit 8 in order to implement ramp times of different sizes. For reasons of clarity, only three potentiometers 27, 28, 29 are shown in FIG. However, it is readily possible to provide a larger number of potentiometers and to connect their taps to the switch 30 if a larger number of ramp times is desired. Since it is for setting the ramp time to that measured on the tap of the potentiometers 27, 28, 29 Voltage arrives and not the position of the slider of the potentiometer, simple multi-turn potentiometers can be used without scaling. Little space is required for such multi-turn potentiometers. This is particularly advantageous if the setting means of the potentiometers should be operable from the front panel of an electrical assembly.

The control voltage Ust can alternatively from an external adjustable voltage source, for. B. a higher-level control.

If the voltage Uein is specified by a programmable logic controller, it is advantageous to also specify the ramp time TR using this controller. For this purpose, the maximum value selection circuit 35 is supplied with an analog voltage instead of the output voltage of the switch 30, the magnitude of which determines the size of the ramp time.

Claims

claims

1. Circuit arrangement for generating an output voltage with a ramp-like time profile between a first voltage value and a second voltage value as a function of the time change of an input voltage with an integrator whose input is dependent on the difference between the input voltage and the output voltage is applied, characterized in that the integrator (2) is connected upstream of a voltage limiting circuit (8) which limits the voltage (Ui) supplied to the integrator (2) to a value predetermined by an adjustable control voltage (Ust).

2. Circuit arrangement according to claim 1, characterized in that the voltage limiting circuit (8) the

Integrator (2) supplied voltage limited to a value that is equal to the control voltage (Ust).

3. Circuit arrangement according to claim 1 or claim 2, characterized in that the control voltage (Ust) is based on ground potential (_L).

4. Circuit arrangement according to one of the preceding claims, characterized in that the control voltage

(Ust) is a partial voltage of a voltage divider (11) supplied by a reference voltage (Uref).

5. Circuit arrangement according to claim 4, characterized in that the voltage divider is designed as a potentiometer (27, 28, 29).

6. Circuit arrangement according to claim 5, characterized in that the potentiometer (27, 28, 29) is designed as a multi-turn potentiometer.

7. Circuit arrangement according to one of claims 4 to 6, characterized in that a plurality of voltage dividers (27, 28, 29) with different divider ratios (xη_, X ₂ , 3) are provided and that the taps of the voltage dividers (27, 28, 29) can be connected to the control input of the voltage limiting circuit (8) via a controlled switch (30).

8. Circuit arrangement according to one of the preceding claims, characterized in that the voltage limiting circuit (8) with the same control voltage (Ust) limits a positive voltage to a positive value and a negative voltage to a negative value.

9. Circuit arrangement according to claim 8, characterized in that

- A first resistor (16) is connected between the output of a comparator circuit (1), the inputs of which are supplied with the input voltage (Uein) and the output voltage (Uaus), and the input of the integrator (2), - That the control voltage (Ust) is supplied to the non-inverting input of a first operational amplifier (20),

- That the output of the first operational amplifier (20) is connected to the cathode of a first diode (21),

- That the anode of the first diode (21) is connected to the inverting input of the first operational amplifier (20) and to the input of the integrator (2),

- That the control voltage (Ust) is fed via a second resistor (24) to the inverting input of a second operational amplifier (22),

- That the output of the second operational amplifier (22) is connected to the anode of a second diode (23),

- That the cathode of the second diode (23) is connected to the input of the integrator (2) and via a third resistor (25), which is the same size as the second resistor (24), with the inverting input of the second operational amplifier (22nd ) is connected and

- That the non-inverting input of the second operational amplifier (22) is connected to ground potential (_L).