WO2000057461A1 - Method for producing a mushroom-shaped or t-shaped gate - Google Patents

Method for producing a mushroom-shaped or t-shaped gate Download PDF

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Publication number
WO2000057461A1
WO2000057461A1 PCT/FR2000/000640 FR0000640W WO0057461A1 WO 2000057461 A1 WO2000057461 A1 WO 2000057461A1 FR 0000640 W FR0000640 W FR 0000640W WO 0057461 A1 WO0057461 A1 WO 0057461A1
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Prior art keywords
etching
grid
lateral
mushroom
grid body
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PCT/FR2000/000640
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French (fr)
Inventor
Thomas Skotnicki
Malgorzata Jurczak
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France Telecom
Commissariat A L'energie Atomique
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Publication of WO2000057461A1 publication Critical patent/WO2000057461A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Definitions

  • the present invention relates generally to a method of making a grid of a semiconductor device, and more particularly to a method of making a mushroom-shaped grid also called a "T" grid.
  • CMOS circuits such as transistors
  • CMOS complementary metal-oxide-semiconductor
  • RF radio frequency
  • CMOS complementary metal-oxide-semiconductor
  • Semiconductor mushroom gate devices are well known for their advantages in terms of switching speed.
  • Si MOSFET's fabrication Metal for a new self-aligned T-shaped grid for the fabrication of deep submicron MOSFETs "Horng-Chih Lin et al., IEEE, T. ED-19, January 1998, pp. 26- 28;
  • the main factor in improving the switching speed is the reduction in gate resistance resulting from the enlargement due to the cap of the mushroom-shaped gate.
  • the mushroom grid is produced by forming a grid base in polycrystalline silicon, depositing a layer of insulating material (ethyl tetraorthosilicate), planarization by mechanical polishing -chemical, etching, deposition of a second layer of polycrystalline silicon, formation of spacer and etching by beam of reactive ions.
  • insulating material ethyl tetraorthosilicate
  • the enlarged cap of the grid is formed by vapor deposition of tungsten above an engraved grid. Due to the isotropic growth of tungsten, an enlarged deposit is automatically obtained.
  • a drawback common to the three methods mentioned above is that they act on only one factor limiting the switching speed, namely the gate resistance, while this switching speed is also greatly reduced by the covering capacities. .
  • the subject of the invention is therefore a method of producing a mushroom-shaped grid for a semiconductor device, in particular a CMOS device, self-aligned and remedying the drawbacks of the prior art.
  • the invention relates to such a method of realization of a mushroom-shaped grid making it possible to improve several factors influencing the switching speed and not only the grid resistance.
  • a method for producing a mushroom-shaped grid in a semiconductor device comprising a foot surmounted by a cap which comprises:
  • the length of the lateral sub-etching, from two opposite sides of the grid body is from 5 to 50 nm, better still from 10 to 40 nm from each of the sides.
  • the lateral under-etching is such that it forms in the upper part of the grid body a cap longer than the grid base.
  • the height of the base obtained by lateral under-etching will preferably represent at most 80% of the total height of the grid body.
  • the height of the foot of the mushroom-shaped grid will generally be at least 2 nm.
  • the lateral under-etching of the base of the grid in the form of mushroom can be produced by any lateral under-etching process, but is preferably localized by plasma under-etching, in particular a two-stage plasma under-etching comprising a first under-etching step using a plasma -high energy and a second step of under-etching by means of a low-energy plasma.
  • a heterogeneous grid body is used, that is to say a grid body consisting of a stack of at least two superposed layers of different conductive materials and generally having different lateral etching speeds for a given etching process.
  • the material of the first layer will have a higher lateral etching speed than the material of the second layer.
  • the lateral under-etching can be done by any suitable method such as a lateral etching controlled by means of an appropriate solution, but preferably by plasma etching and in particular a plasma etching comprising a first etching step with a high energy plasma and a second etching step with a low energy plasma.
  • the lateral under-etching can be carried out after the conventional etching of the grid (resin mask), by allowing controlled lateral etching during the removal of the mask.
  • resin in an acid solution H 2 S0 4 H 2 ⁇ 2
  • a chemical solution selective with respect to silicon such as a 40 ml solution HN0 3 70% - 20 ml H 2 0 2 - 5 ml 0.5% HF, and even pure water if the Ge concentration of the SiGe alloy is high enough. All the same, preferably, this lateral etching is carried out by an isotropic plasma attack selective with respect to silicon and oxide.
  • pairs Si j ⁇ Ge ⁇ (0 ⁇ x ⁇ 1) / Si; Si / Si 1. ⁇ Ge ⁇ (0 ⁇ x ⁇ 1); 95, 0 ⁇ tal, metal / Si and metal / metal.
  • a semiconductor substrate for example made of silicon, having a main face covered with a layer of gate oxide (Si0 2 ) 2, a heterogeneous grid body 3 consisting of a lower layer of a first material 4, for example of Si- j _ ⁇ Ge ⁇ alloy and of an upper layer of a second material 5, for example silicon .
  • the lower and upper layers of the grid body 3 can be conventionally deposited, for example by chemical vapor deposition.
  • the next step, illustrated in Figure 2 is to form, by lateral etching, cavities 6 in the lower layer 4 on opposite sides thereof.
  • this lateral etching is preferably carried out by plasma etching.
  • LDD junctions lightly doped

Abstract

The invention concerns a method which consists in: forming on a main surface of a semiconductor substrate covered with a thin oxide film a gate body in conductive material; etching the sides of the gate body to form the foot of the gate in the shape of a mushroom. The invention is applicable to CMOS devices.

Description

Procédé de réalisation d'une grille en forme de champignon ou grille en "T". Method of making a mushroom-shaped grid or "T" grid.
La présente invention concerne d'une manière générale un procédé de réalisation d'une grille d'un dispositif semi-conducteur, et plus particulièrement un procédé de réalisation d'une grille en forme de champignon également dite grille en "T". Dans le domaine des circuits CMOS, tels que les transistorsThe present invention relates generally to a method of making a grid of a semiconductor device, and more particularly to a method of making a mushroom-shaped grid also called a "T" grid. In the field of CMOS circuits, such as transistors
CMOS, pour des applications à des produits fonctionnant en radiofréquence (RF) ou pour le traitement de données, la vitesse de commutation des dispositifs semi-conducteurs utilisés est une caractéristique importante de ceux-ci. Les dispositifs semi-conducteurs à grille en forme de champignon sont bien connus pour leurs avantages en termes de vitesse de commutation.CMOS, for applications to products operating in radio frequency (RF) or for data processing, the switching speed of the semiconductor devices used is an important characteristic of these. Semiconductor mushroom gate devices are well known for their advantages in terms of switching speed.
De tels dispositifs à grille en forme de champignon sont décrits entre autres dans les documents : "A novel self-aligned T-shape gâte process for deep submicronSuch mushroom-shaped grid devices are described, among others, in the documents: "A novel self-aligned T-shape spoiling process for deep submicron
Si MOSFET's fabrication (Procédé pour une nouvelle grille en forme de T auto-alignée pour la fabrication de MOSFET à Si submicronique profond)" Horng-Chih Lin et al., IEEE, T. ED-19, janvier 1998, pp. 26-28;Si MOSFET's fabrication (Method for a new self-aligned T-shaped grid for the fabrication of deep submicron MOSFETs) "Horng-Chih Lin et al., IEEE, T. ED-19, January 1998, pp. 26- 28;
"A low-resistance self-aligned T-shape gâte for high performance sub-0,1 μm CMOS (grille en forme de T, auto-alignée de faible résistance pour CMOS sub-0,1 μm de haute performance)" Digh Hisamoto et al., IEEE, T. ED-44, juin 1997, pp. 951-956; et"A low-resistance self-aligned T-shape spoils for high performance sub-0.1 μm CMOS (T-shaped, low-resistance self-aligned grid for CMOS sub-0.1 μm high performance)" Digh Hisamoto et al., IEEE, T. ED-44, June 1997, pp. 951-956; and
"Sub-100 nm gâte length métal gâte NMOS transistors fabricated by a replacement gâte process (Transistors NMOS à grille métallique de longueur sub-100 nm fabriqués par un procédé de remplacement de grille)", A. Chatterjee et al., IEDM'97, pp. 821 -824."Sub-100 nm spade length metal spade NMOS transistors fabricated by a replacement spade process (NMOS transistors with metal grid of length sub-100 nm manufactured by a process of replacement of grid) ", A. Chatterjee et al., IEDM'97, pp. 821 -824.
Dans ces publications de l'art antérieur, le principal facteur de l'amélioration de la vitesse de commutation est la réduction de la résistance de grille résultant de l'élargissement dû au chapeau de la grille en forme de champignon.In these prior art publications, the main factor in improving the switching speed is the reduction in gate resistance resulting from the enlargement due to the cap of the mushroom-shaped gate.
Dans l'article de Horng-Chih Lin et al., la grille-champignon est réalisée par formation d'un pied de grille en silicium polycristallin, dépôt d'une couche de matériau isolant (tétraorthosilicate d'éthyle), aplanissement par polissage mécano-chimique, gravure, dépôt d'une seconde couche de silicium polycristallin, formation d'espaceur et gravure par faisceau d'ions réactifs.In the article by Horng-Chih Lin et al., The mushroom grid is produced by forming a grid base in polycrystalline silicon, depositing a layer of insulating material (ethyl tetraorthosilicate), planarization by mechanical polishing -chemical, etching, deposition of a second layer of polycrystalline silicon, formation of spacer and etching by beam of reactive ions.
Dans le mode de réalisation décrit dans l'article de Digh Hisamoto et al., le chapeau élargi de la grille est formé par dépôt en phase vapeur de tungstène au dessus d'une grille gravée. Du fait de la croissance isotropique du tungstène, on obtient automatiquement un dépôt élargi.In the embodiment described in the article by Digh Hisamoto et al., The enlarged cap of the grid is formed by vapor deposition of tungsten above an engraved grid. Due to the isotropic growth of tungsten, an enlarged deposit is automatically obtained.
Quant au procédé dit de "remplacement de grille" de l'article A. Chatterjee et al., il s'apparente à un procédé double damascène.As for the process called "grid replacement" of article A. Chatterjee et al., It is similar to a double damascene process.
Un inconvénient commun aux trois procédés évoqués ci-dessus est qu'ils n'agissent que sur un seul facteur limitant la vitesse de commutation, à savoir la résistance de grille, cependant que cette vitesse de commutation est également fortement réduite par les capacités de recouvrement.A drawback common to the three methods mentioned above is that they act on only one factor limiting the switching speed, namely the gate resistance, while this switching speed is also greatly reduced by the covering capacities. .
En outre, le procédé de Horng-Chih Lin et al. apparaît complexe et difficile à contrôler, cependant que le procédé de Digh Hisamoto et al. soulève des problèmes de masquage et de fiabilité d'un dépôt de tungstène débordant.In addition, the method of Horng-Chih Lin et al. appears complex and difficult to control, while the method of Digh Hisamoto et al. raises problems of masking and reliability of an overflowing tungsten deposit.
Enfin, la technique décrite dans l'article de A. Chatterjee et al. n'est pas auto-alignée, apparaît également très complexe, nécessitant la création d'une fausse grille (éliminée ultérieurement) et un polissage mécano-chimique au niveau de la grille.Finally, the technique described in the article by A. Chatterjee et al. is not self-aligned, also appears very complex, requiring the creation of a false grid (eliminated later) and chemical mechanical polishing at the grid.
L'invention a donc pour objet un procédé de réalisation d'une grille en forme de champignon pour un dispositif semi-conducteur, en particulier un dispositif CMOS, auto-aligné et remédiant aux inconvénients de l'art antérieur. En particulier, l'invention a pour objet un tel procédé de réalisation d'une grille en forme de champignon permettant d'améliorer plusieurs facteurs influant sur la vitesse de commutation et non pas seulement sur la résistance de grille.The subject of the invention is therefore a method of producing a mushroom-shaped grid for a semiconductor device, in particular a CMOS device, self-aligned and remedying the drawbacks of the prior art. In particular, the invention relates to such a method of realization of a mushroom-shaped grid making it possible to improve several factors influencing the switching speed and not only the grid resistance.
Selon l'invention, on fournit un procédé de réalisation dans un dispositif semi-conducteur d'une grille en forme de champignon comprenant un pied surmonté d'un chapeau qui comprend :According to the invention, a method is provided for producing a mushroom-shaped grid in a semiconductor device comprising a foot surmounted by a cap which comprises:
- la formation sur une surface principale d'un substrat semiconducteur recouvert d'une mince couche d'oxyde de grille d'un corps de grille en matériau conducteur; et - la sous-gravure latérale du corps de grille pour former le pied de la grille en forme de champignon.- the formation on a main surface of a semiconductor substrate covered with a thin layer of gate oxide of a gate body of conductive material; and - the lateral under-etching of the grid body to form the foot of the mushroom-shaped grid.
De préférence, la longueur de la sous-gravure latérale, depuis deux côtés opposés du corps de grille est de 5 à 50 nm, mieux de 10 à 40 nm depuis chacun des côtés. Bien évidemment, la sous-gravure latérale est telle qu'elle forme dans la partie supérieure du corps de grille un chapeau plus long que le pied de grille. Ainsi, la hauteur du pied obtenu par sous-gravure latérale représentera de préférence au plus 80% de la hauteur totale du corps de grille. En outre, la hauteur du pied de la grille en forme de champignon sera généralement d'au moins 2 nm.Preferably, the length of the lateral sub-etching, from two opposite sides of the grid body is from 5 to 50 nm, better still from 10 to 40 nm from each of the sides. Obviously, the lateral under-etching is such that it forms in the upper part of the grid body a cap longer than the grid base. Thus, the height of the base obtained by lateral under-etching will preferably represent at most 80% of the total height of the grid body. In addition, the height of the foot of the mushroom-shaped grid will generally be at least 2 nm.
Dans le cas d'un corps de grille homogène, c'est-à-dire que l'ensemble de la grille est constitué par un unique matériau tel que du silicium polycristallin, la sous-gravure latérale du pied de la grille en forme de champignon peut être réalisée par tout procédé de sous-gravure latérale, mais est de préférence localisée par sous-gravure par plasma, en particulier une sous-gravure par plasma en deux étapes comprenant une première étape de sous-gravure au moyen d'un plasma-haute énergie et une deuxième étape de sous-gravure au moyen d'un plasma-basse énergie.In the case of a homogeneous grid body, that is to say that the entire grid is made of a single material such as polycrystalline silicon, the lateral under-etching of the base of the grid in the form of mushroom can be produced by any lateral under-etching process, but is preferably localized by plasma under-etching, in particular a two-stage plasma under-etching comprising a first under-etching step using a plasma -high energy and a second step of under-etching by means of a low-energy plasma.
De préférence, dans la mise en oeuvre du procédé de l'invention, on utilise un corps de grille hétérogène, c'est-à-dire un corps de grille constitué d'un empilement d'au moins deux couches superposées de matériaux conducteurs différents et généralement ayant des vitesses de gravure latérale différentes pour un procédé de gravure donné. De préférence, le matériau de la première couche aura une vitesse de gravure latérale supérieure au matériau de la seconde couche. Comme dans le cas d'une grille homogène, la sous-gravure latérale peut se faire par tout procédé approprié tel qu'une gravure latérale contrôlée au moyen d'une solution appropriée, mais de préférence par gravure plasma et en particulier une gravure plasma comprenant une première étape de gravure avec un plasma haute énergie et une seconde étape de gravure avec un plasma basse énergie.Preferably, in the implementation of the method of the invention, a heterogeneous grid body is used, that is to say a grid body consisting of a stack of at least two superposed layers of different conductive materials and generally having different lateral etching speeds for a given etching process. Preferably, the material of the first layer will have a higher lateral etching speed than the material of the second layer. As in the case of a homogeneous grid, the lateral under-etching can be done by any suitable method such as a lateral etching controlled by means of an appropriate solution, but preferably by plasma etching and in particular a plasma etching comprising a first etching step with a high energy plasma and a second etching step with a low energy plasma.
A titre d'exemple, dans le cas d'un alliage SiGe, la sous-gravure latérale peut s'effectuer après la gravure classique de la grille (masque de résine), en autorisant une gravure latérale contrôlée au cours du retrait du masque de résine dans une solution acide (H2S04 H2θ2) ou encore après la gravure classique de la grille (masque dur), en utilisant une solution chimique sélective par rapport au silicium telle qu'une solution 40 ml HN03 70% - 20 ml H202 - 5 ml HF 0,5%, et même de l'eau pure si la concentration en Ge de l'alliage SiGe est suffisamment importante. Tout de même, de préférence, cette gravure latérale s'effectue par une attaque plasma isotrope sélective par rapport au silicium et à l'oxyde.For example, in the case of an SiGe alloy, the lateral under-etching can be carried out after the conventional etching of the grid (resin mask), by allowing controlled lateral etching during the removal of the mask. resin in an acid solution (H 2 S0 4 H 2 θ2) or even after the conventional etching of the grid (hard mask), using a chemical solution selective with respect to silicon such as a 40 ml solution HN0 3 70% - 20 ml H 2 0 2 - 5 ml 0.5% HF, and even pure water if the Ge concentration of the SiGe alloy is high enough. All the same, preferably, this lateral etching is carried out by an isotropic plasma attack selective with respect to silicon and oxide.
Parmi les couples de matériaux utilisables pour l'empilement de grille, on peut citer les couples Sij .χGeχ (0 < x < 1 ) / Si ; Si/Si1.χGeχ(0 < x ≤ 1); 95 , 0 <
Figure imgf000006_0001
tal, métal/Si et métal/métal.Among the pairs of materials that can be used for grid stacking, mention may be made of the pairs Si j .χ Ge χ (0 <x <1) / Si; Si / Si 1.χ Ge χ (0 <x ≤ 1); 95, 0 <
Figure imgf000006_0001
tal, metal / Si and metal / metal.
La suite de la description se réfère aux figures 1 à 4 annexées qui représentent schématiquement les étapes principales d'une mise en oeuvre du procédé de l'invention pour la réalisation d'une grille-champignon hétérogène.The following description refers to Figures 1 to 4 attached which schematically represent the main steps of an implementation of the method of the invention for the production of a heterogeneous mushroom grid.
Comme le montre la figure 1, on commence par former de manière classique, par dépôt et gravure, sur un substrat semi-conducteur 1, par exemple en silicium, ayant une face principale recouverte d'une couche d'oxyde de grille (Si02) 2, un corps de grille hétérogène 3 constitué d'une couche inférieure d'un premier matériau 4, par exemple en alliage Si-j_χGeχ et d'une couche supérieure d'un second matériau 5, par exemple du silicium. Les couches inférieure et supérieure du corps de grille 3 peuvent être classiquement déposées par exemple par dépôt chimique en phase vapeur. L'étape suivante, illustrée à la figure 2, consiste à former, par gravure latérale, des cavités 6 dans la couche inférieure 4 sur des côtés opposés à celle-ci.As shown in FIG. 1, we begin by forming in a conventional manner, by deposition and etching, on a semiconductor substrate 1, for example made of silicon, having a main face covered with a layer of gate oxide (Si0 2 ) 2, a heterogeneous grid body 3 consisting of a lower layer of a first material 4, for example of Si- j _ χ Ge χ alloy and of an upper layer of a second material 5, for example silicon . The lower and upper layers of the grid body 3 can be conventionally deposited, for example by chemical vapor deposition. The next step, illustrated in Figure 2, is to form, by lateral etching, cavities 6 in the lower layer 4 on opposite sides thereof.
Comme indiqué précédemment, cette gravure latérale s'effectue de préférence par gravure plasma. On procède alors comme le montre la figure 3 à une implantation classique de dopants pour former des jonctions 7 et 8 faiblement dopées (jonctions LDD), puis comme illustré à la figure 4, à la formation des espaceurs 9 et à une implantation de dopants pour réaliser les régions de source et de drain 10 et 1 1 de manière classique. Dans le contexte d'une technologie à dimension caractéristique égale à la longueur de la couche Si supérieure, le procédé de l'invention de réalisation d'une grille-champignon, on obtient les avantages suivants :As indicated above, this lateral etching is preferably carried out by plasma etching. We then proceed as shown in Figure 3 to a conventional implantation of dopants to form junctions 7 and 8 lightly doped (LDD junctions), then as illustrated in Figure 4, the formation of spacers 9 and an implantation of dopants for realize the source and drain regions 10 and 1 1 in a conventional manner. In the context of a technology with a characteristic dimension equal to the length of the upper layer Si, the method of the invention for producing a mushroom grid, the following advantages are obtained:
- un recouvrement très réduit grille/jonction d'où une réduction des capacités de recouvrement; - une résistance de grille inchangée dans le cas d'une grille siliciurée;- a very reduced grid / junction overlap hence a reduction in overlap capacities; - an unchanged grid resistance in the case of a silicided grid;
- une déplétion grille PMOS réduite du fait d'une meilleure activation du dopant (bore) dans l'alliage Sil χGeχ par rapport au Si;- a reduced PMOS grid depletion due to better activation of the dopant (boron) in the Si l χ Ge χ alloy compared to Si;
- un dopage du canal réduit du côté PMOS (par exemple pour une grille SiGe duale P+/N+).- reduced channel doping on the PMOS side (for example for a dual P + / N + SiGe grid).
Dans le contexte d'une technologie à dimension caractéristique égale à la longueur de la couche Sij_χGeχ :In the context of a technology with a characteristic dimension equal to the length of the layer Si j _ χ Ge χ :
- le recouvrement grille/jonction réduit (capacités Cgs et Cgd réduites); - la résistance grille réduite et la siliciuration, grille plus facile du faite de l'élargissement;- reduced grid / junction overlap (reduced Cgs and Cgd capacities); - reduced grid resistance and siliciding, easier grid due to enlargement;
- la déplétion grille PMOS réduite du fait d'une meilleure activation du bore dans le SiGe par rapport au Si;- reduced PMOS grid depletion due to better activation of boron in SiGe compared to Si;
- un dopage du canal réduit du côté PMOS (par exemple par une grille SiGe duale P+/N+). - reduced doping of the PMOS side (for example by a dual SiGe P + / N + grid).

Claims

REVENDICATIONS
1. Procédé de réalisation dans un dispositif semi-conducteur d'une grille en forme de champignon comportant un pied surmonté d'un chapeau, caractérisé en ce qu'il comprend :1. Method for producing a mushroom-shaped grid in a semiconductor device comprising a foot surmounted by a hat, characterized in that it comprises:
- la formation sur une surface principale d'un substrat semi- conducteur recouvert d'une mince couche d'oxyde de grille d'un corps de grille en matériau conducteur ; et- The formation on a main surface of a semiconductor substrate covered with a thin layer of gate oxide of a gate body of conductive material; and
- la gravure latérale du corps de grille pour former le pied de la grille en forme de champignon.- the lateral engraving of the grid body to form the foot of the mushroom-shaped grid.
2. Procédé selon la revendication 1, caractérisé en ce que la longueur de la gravure latérale de chaque côté du corps de grille est de 5 à2. Method according to claim 1, characterized in that the length of the lateral engraving on each side of the grid body is 5 to
50nm, de préférence 10 à 40 nm.50nm, preferably 10 to 40nm.
3. Procédé selon la revendication 1 ou 2, caractérisé en ce que la hauteur de gravure du corps de grille est de 2 nm à 80 % de la hauteur totale du corps de grille. 3. Method according to claim 1 or 2, characterized in that the etching height of the grid body is 2 nm to 80% of the total height of the grid body.
4. Procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce que le corps de grille est homogène et la gravure latérale s'effectue par gravure par plasma.4. Method according to any one of claims 1 to 3, characterized in that the grid body is homogeneous and the side etching is carried out by plasma etching.
5. Procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce que le corps de grille est un empilement hétérogène comprenant une couche inférieure et une couche supérieure en matériau conducteur, le matériau de la couche inférieure ayant une vitesse de gravure latérale supérieure à celle du matériau de la couche supérieure pour un processus de gravure latérale donné.5. Method according to any one of claims 1 to 3, characterized in that the grid body is a heterogeneous stack comprising a lower layer and an upper layer of conductive material, the material of the lower layer having a lateral etching speed higher than that of the upper layer material for a given side etching process.
6. Procédé selon la revendication 5, caractérisé en ce que les couples matériau de la couche inférieure / matériau de la couche supérieure sont choisis parmi les couples Sij.χGeχ (0 < x < 1) / Si ; Si/Sij. χGeχ (0 < x < 1), Sij.χ.yGeχCy (0 < x < 0,95, 0 < y < 0,05)/Si, Si/Si !_x_ yGeχCy(0 < x < 0,95, 0 < y < 0,05), Si dopé P+ / Si dopé N+, Si dopé N+ / Si dopé P+, Si/métal, métal/Si et métal/métal. 6. Method according to claim 5, characterized in that the material pairs of the lower layer / material of the upper layer are chosen from the pairs Si j.χ Ge χ (0 <x <1) / Si; If / If j. χ Ge χ (0 <x <1), Si j.χ.y Ge χ C y (0 <x <0.95, 0 <y <0.05) / Si, Si / Si! _ x _ y Ge χ C y (0 <x <0.95, 0 <y <0.05), Si doped P + / Si doped N + , Si doped N + / Si doped P + , Si / metal, metal / Si and metal /metal.
7. Procédé selon la revendication 6, caractérisé en ce que le corps de grille est formé par gravure à l'aide d'un masque de résine et la gravure latérale de la couche inférieure du corps s'effectue en même temps que le retrait de la résine. 7. Method according to claim 6, characterized in that the grid body is formed by etching using a resin mask and the lateral etching of the lower layer of the body is carried out at the same time as the removal of resin.
8. Procédé selon la revendication 6, caractérisé en ce que le corps de grille est formé par gravure au moyen d'un masque dur et la gravure latérale de la couche inférieure du corps s'effectue à l'aide d'une solution de gravure sélective vis-à-vis du silicium.8. Method according to claim 6, characterized in that the grid body is formed by etching by means of a hard mask and the lateral etching of the lower layer of the body is carried out using an etching solution selective with respect to silicon.
9. Procédé selon la revendication 6, caractérisé en ce que la gravure latérale de la couche inférieure s'effectue par gravure par plasma. 9. Method according to claim 6, characterized in that the lateral etching of the lower layer is carried out by plasma etching.
PCT/FR2000/000640 1999-03-19 2000-03-16 Method for producing a mushroom-shaped or t-shaped gate WO2000057461A1 (en)

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FR99/03469 1999-03-19
FR9903469A FR2791177A1 (en) 1999-03-19 1999-03-19 PROCESS FOR PRODUCING A MUSHROOM GRILLE OR "T" GRILLE

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