Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
  • H04N19/63—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using sub-band based transform, e.g. wavelets
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation

Definitions

• the present invention relates to signal/image processing. More specifically, the present invention relates to image compression.
• any signal may be approximated as a sum of sinusoidal waveforms of assorted frequencies. While Fourier transforms are ideally suited for signals having repeated behavior, such as speech signals, Fourier transforms fail to efficiently approximate signals with sharp discontinuities such as the edge features of images, or signals encoded for digital communications.
• Wavelets are used as a way to represent an image in both the frequency and spatial domain. Due to quantization effects, less visual side effects are produced when using wavelets compared to a block based discrete cosine transform (DCT).
• DCT discrete cosine transform
• the DWT is a "discrete" algorithm, that rather than approximating a signal using continuous waveforms, approximates the signal by discrete samples of waveforms. Since the transform is discrete, the DWT may be implemented using digital logics such as Very Large Scale Integrated (VLSI) circuits. Thus DWT may be integrated on a chip with other digital components.
• VLSI Very Large Scale Integrated
• DWT decompose an input signal into two or more frequency sub-bands.
• An input signal may be decomposed into two outputs—a low frequency sub- band output, obtained by using a low-pass filter, and a high frequency sub-band output, obtained by using a high-pass filter.
• Each of these sub-bands may be encoded separately using a suitable coding system.
• Each sub-band may further be divided into smaller and smaller sub-bands as is required.
• DWT is a computationally very intensive process and hence very slow when computed using a general purpose computing system.
• a special purpose custom VLSI chip may be used for DWT, exploiting the underlying data parallels to yield high throughput and hence high data rate.
• the present invention provides an apparatus to perform symmetric filtering image compression.
• the apparatus includes an N-element shift circuit, that has N shifting blocks (SB), to store and shift data elements. Each data element represents a pixel of an image.
• the apparatus also includes a first plurality of adder circuits to add data elements from a first plurality of pairs of SBs of the N SBs.
• the apparatus further includes a second plurality of adder circuits to add data elements from a second plurality of pairs of SBs of the N SBs.
• the apparatus includes a first plurality of multiplier circuits, to multiply by corresponding low pass coefficients results of additions performed by the first plurality of adder circuits.
• the apparatus also includes a second plurality of multiplier circuits, to multiply by corresponding high pass coefficients results of additions performed by the second plurality of adder circuits.
• Figure 1 is a block diagram illustrating basic steps involved in the filtering operation implemented by the apparatus according to the present invention
• Figure 2 is a block diagram illustrating the apparatus for performing symmetric filtering image compression according to one embodiment of the present invention
• Figure 3 is a block diagram illustrating the apparatus shown in Figure 2 where data elements shifted to the right by 2 and two additional data elements added;
• Figure 4 is a block diagram illustrating the apparatus of Figure 3 where data elements are shifted to the right by 2 and two additional elements are added;
• Figure 5 is a block diagram illustrating the apparatus of Figure 4 where data elements stored therein are shifted to the right by 2 and two additional data elements are added;
• Figure 6 is a block diagram illustrating the apparatus of Figure 5 where data elements are shifted to the right by 2 and two data elements are added;
• Figure 7 is a block diagram illustrating the apparatus of Figure 2 with the low pass elements L0-L4 stored therein;
• Figure 8 is a flow chart diagram in connection with an embodiment of a process of obtaining low and high pass coefficients according to the present invention.
• Discrete wavelet transform (DWT) based image compression is usually a computationally expensive process. Selection of a basis function is an important criteria to achieve expected performance and for efficient implementation.
• DWT Discrete wavelet transform
• a 9-7 biorthongonal Spline filtering based DWT that is suitable for image compression applications is utilized.
• a symmetric filtering architecture is utilized for optimal implementation of this particular DWT-based image compression scheme.
• h i and gi are the low-pass and high-pass filter coefficients respectively and H j and L j are data coefficients.
• the 9-7 biorthogonal spline filter based DWT which is utilized in one embodiment of the present invention, is well known in the art and is suitable for image compression applications.
• the 9 - 7 biorthogonal spline filter has 9 low-pass filter coefficients ⁇ _ 4 ,h_ 3 h_ 2 .h_ ⁇ ,11 0 ,1 1 ,11 2 , 1 3 ,1 4 ⁇ and 7 high-pass filter coefficients ⁇ g, 3 , g- 2 '8-i'8 ⁇ 'gi'g 2 'g 3 )-
• L 0 h 0 (0 + d 0 ) + h ⁇ i + d ⁇ ) + h 2 (d 2 + d 2 ) + 3 (d 3 + d 3 ) + h 4 (d 4 + d 4 )
• L x h 0 (0 + d 2 ) + h-J ⁇ + d 3 ) + h 2 (d 0 + d 4 ) + l ⁇ + d 5 ) + h 4 (d 2 + d 6 )
• 2 h 0 (0 + d 4 ) + h 1 (d 3 + d 5 ) + h 2 (d 2 + d 6 ) + t ⁇ td j. + d 7 ) + h 4 (d 0 + d 8 )
• H 0 g 0 d x + + d 2 ) + g 2 (d ⁇ + d 3 ) + g 3 (d 2 + d 4 )
• Hi g 0 d 3 + 9l( d 2 + d 4) + 92 ⁇ 1 + d 5) + 93 ⁇ d 0 + d 6>
• the other H_ terms may be expressed in a similar fashion.
• a one dimensional 9-7 biorthongonal- spline-filter-based DWT transforms a N-block of data into an N/2 high pass block of data and N/2 low-pass block of data. This process creates sub-bands that represent the image at different resolutions in varying significance to the human eye.
• incoming data elements dj are convolved with two filters: h, which is a 9-tap low-pass filter; and g which is a 7-tap high-pass filter.
• h which is a 9-tap low-pass filter
• g which is a 7-tap high-pass filter.
• Nyquist's theory as the resulting filtered representations do not contain the full frequency band width of the original image, one may reconstruct the filtered representation without utilizing all N elements.
• an apparatus of the present invention (not shown), based on the scheme of Figure 1, performs a convolution on every other data element.
• Step 1 the following operations may be performed:
• H 0 0 ⁇ 1 + 9l( d 0 + d 2> + 92 ⁇ d l + d 3 ) + 93 ⁇ d 2 + d 4>
• L refers to the low pass coefficient and H to the high pass coefficient.
• FIG. 1 illustrates block 102 (shown within dotted lines) that includes a sub-block 108 of data elements dg -d ⁇ demarcated by vertical dotted lines 104 and 106.
• Block 102 also includes sub-block 110 that includes data elements i, d 2 , d 3 > and d 4 - Data elements i, d 2.
• d 3 » n d 4 are symmetrically disposed about data element do.
• One reason that data is symmetrically disposed about do is to reduce edge effects.
• Each data element di is a 16-bit quantity that characterizes a pixel of an image, or the result of a previous filtering operation.
• FIG. 1 illustrates in 4 steps how the low pass coefficients ho, hi, h2, h3 and I14 and the high pass coefficients gg ,g ⁇ &2 an ⁇ 93 sae disposed relative to the block of data 102. Convolutions between the data elements di and the coefficients hi and gi may be calculated more easily, when knowing how to dispose coefficients h j and g ; with respect to the data elements d j of block 102.
• H 0 g 0 d 1 +g 1 (d 0 +d 2 )+g 2 (d 1 +d 3 )+g 3 (d 2 +d 4 ).
• the convolution is performed by shifting the blocks of low pass coefficients h j 116 and of high pass coefficients g ; 118 by 2 places to the right as is shown in the figure at Step 2.
• the results of the convolutions between the low pass coefficients h j and the data elements d ; are calculated in the following way.
• the multiplication between hi and di in the vertical direction yields the following results:
• LI h0d2 + hl(dl + d3) + h2(d0 + d4) + h3(dl + d5) + h4(d2 + d6).
• the high pass coefficient HI is obtained by convolving di with the high pass coefficients gi shifted to the right by 2 relative to the previous high pass coefficients from Step 1. Therefore, the centers of both the low pass and high pass filter have moved two places over to the right
• FIG. 2 illustrates a high level block diagram of an embodiment 200 of an apparatus for performing symmetric filtering image compression according to the present invention.
• the apparatus 200 includes a N-element shift circuit 201, shown in dotted lines, that includes N shifting blocks.
• the N- element shift circuit 201 includes 9 shifting blocks 202, 204, 206, 208, 210, 212, 214, 216 and 218.
• the shifting blocks are configured to store data elements therein and to shift the data elements stored therein to a next shifting block.
• each shifting block includes a shift register R ⁇ .
• Shift registers Ri are 16-bit shift registers to accommodate the 16-bit data elements di. Data elements such as do, di,d2, etc., are shifted between successive registers Ri from left to the right in the figure.
• Circuit 264 outputs data elements do-d4, passed through circuits 260 and 262, to a multiplexor 266.
• multiplexor 266 selects at an output thereof the data elements passed through circuits 260 and 262.
• Data elements do-d4, output by multiplexor 266, are then shifted from left to right in the figure through registers R Q , R,, R J , R 3 , R 4 , such that at the end of the shifting operation Ro stores d4, R j stores d3, R 2 stores d2, R 3 stores di and R 4 stores do.
• Figure 3 illustrates in diagrammatic form the configuration of apparatus 200 with data elements do,di,d2,d3 and d4 symmetrically stored in apparatus 200.
• data elements do-c_4 are stored in registers R4-R0 respectively, as shown in Figure 2, data elements R3, R2, Rl and R0 are symmetrically copied into registers R5, R6, R7, and R8, respectively about register R4 as the arrows 268, 270, 272 and 274, indicate. More specifically, dl is copied from R3 to R5, d2 is copied from R2 to R6, d3 is copied from Rl to R7 and d4 is copied from R0 to R8.
• the apparatus 200 has the hardware support to perform symmetric copying.
• the implementation of the hardware support to symmetrically copy data elements about register R4 is not explained herein as it is within the ambit of the knowledge of persons having ordinary skills in the art.
• the first pass is performed to obtain the low and the high pass filter coefficients LO, HO, LI, HI, L2, H2, L3, H3, L4, H4.
• elements LO, LI, L2, L3, L4, HO, HI, H2, H3, H4 are passed directly through registers R0-R8 and the respective operations explained above are performed on these elements.
• the operations for obtaining the low pass coefficient Lo by way of apparatus 200 include the following.
• Data elements stored in each symmetric pair of registers (R ⁇ R ⁇ , (R ⁇ R g ), (R,,R 7 ) and (R o ,R 8 ) are added therebetween in corresponding circuits 230, 232, 234 and 236 which are coupled to the above-mentioned symmetric pairs of registers.
• circuits 230, 232, 234 and 236 are called "add-dividers" as these circuits provide two functionality's: adding the pairs of data elements from the pairs of symmetrically extended registers, coupled to the add-divider; and dividing the result of the addition by 2 by extracting the 16 most significant bits.
• the apparatus of Figure 3 further includes a plurality of first multipliers 240, 242, 244, 246 and 248.
• Multipliers 240, 242, 244, and 246 are coupled to corresponding add- dividers 236, 234, 232, and 230 respectively. These multipliers multiply the low pass coefficients hi, h2, h3 and h4 with the result obtained by the operations performed by the add-dividers, i.e., addition of two symmetrical data elements and division of the result of the addition by 2.
• the low pass coefficients h ⁇ -h 4 are multiplied by 2 to compensate the division by 2 of the result of the addition of the symmetric data elements.
• multipliers 240-246 produce at the output ports thereof, values 2h 4 d 4 , 2h 3 d3, 2h2d2 and 2h ⁇ d ⁇ respectively.
• Data element do is multiplied by ho in multiplier 248 coupled to register R4.
• Multipliers 248, 246, 244, 242 and 240 are coupled to adder 250 that adds the results of the multiplications by the multipliers.
• the result of the addition, in adder 250 is the first low pass coefficient Lo which is equal to
• the apparatus of Figures 2 and 3 also calculates the high pass coefficient HO.
• Data elements of a plurality of pairs of registers are added together.
• Data elements of registers R2 and R4 are added together in an add-divider 222.
• Data elements of registers Rl and R5 are added together in add-divider 224.
• Data elements of registers R0 and R6 are added together in add-divider 226.
• the add-dividers mentioned above are configured to add pairs of data elements that are coupled thereto and then to divide the result of the addition by 2. Accordingly, after adding two data elements, from symmetrically disposed shift registers, add-dividers 222, 224, and 226 are configured to divide the result of the addition by two.
• data elements do and d2 are added in add-divider 222 and the result of the addition is divided by 2.
• Data elements d3 and di are added in add- divider 224 and the result of the addition is divided by 2.
• Data elements (I 4 and d2 are added in add-divider 226 and the result of the addition is divided by 2.
• the results of these operations are multiplied by 2g3, 2g2 and 2g in multipliers 227, 225 and 223 respectively.
• the data element dl from register 4 is multiplied by the coefficient gO in multiplier 221.
• the results of the multiplications are then added in adder 251.
• Adders 250 and 251 include 32 bit accumulators that store the results of the additions.
• the results of the addition from adder 250 are then multiplied by the coefficient hfq and the results of the addition in block 251 is multiplied by coefficient gfq.
• Multiplications by gfq and hfq represent how the accumulated results may be quantized prior to outputting the results.
• Quantization is a step down in image compression to reduce the range of incoming data by multiplying the element by a fraction.
• the apparatus 200 takes advantage of the symmetrical configuration of the stored data elements di and of the low and high pass coefficients. Due to the symmetrical configuration, only one multiplication is performed instead of two multiplications.
• Figure 4 illustrates the apparatus of Figure 3 where data elements are shifted to the right by 2 by the shifting circuit 201. Data elements 65 and d are shifted into register Rl and RO respectively.
• the configuration shown in Figure 4 produces, at Step 2, the low pass and high pass coefficients LI and HI.
• d2 stored in register R4 is multiplied in multiplier 248 by low pass coefficient hO.
• Data elements dl and d3 stored in symmetrically disposed registers R5 and R3 are added by add-divider 230 and the result divided by 2.
• the result of the addition divided by 2 is then multiplied in multiplier 246 by the quantity 2h ⁇ .
• Data stored in registers R2 and R6, i.e., d4 and do, respectively is added by the add-divider 232 and the result is divided by 2. After that, the result of the addition is multiplied by 2h2 in multiplier 244.
• Figure 5 illustrates the apparatus of Figure 4 where data elements stored in registers R0-R8 are shifted to the right by 2 and new data elements d7 and d6 are stored in registers Rl and R0 respectively.
• the rest of the operations concerning additions between data elements and division by 2, multiplication with low and high pass coefficients hi and gi, and addition of the results by adders 250 and 251 are the same as the operations explained above in connection with the description of the previous figures.
• Figure 6 illustrates the apparatus of Figure 5 where data elements stored in registers R0-R8 are shifted to the right by 2. Data elements d5 and d4 are stored in registers Rl and R0 respectively. Since d7 represents the last piece of data in this example, the apparatus starts symmetrically copying data around d7 to wrap up calculations.
• Low pass coefficients L0-L4 and high pass coefficients H0-H4 may be obtained after data elements are passed through the shift circuit 201 of the apparatus 200 and the operations explained earlier in connection with additions and multiplications are performed. More passes made with L0-L4 and H0-H4 may then be performed by way of the apparatus 200 and the methodology of processing data explained above.
• Figure 7 illustrates the apparatus of Figure 2 where low pass elements L 0 -L 4 obtained in the first pass are shifted through registers Ro-R 4 . Then the contents of registers R 3 -R Q are symmetrically copied, about register R4, to registers R j ,Rg,R 7 , and R 8 .
• L_-l- are not processed by circuits 260 and 262 but rather are directly provided to the shift circuit 20 ⁇ by multiplexor 266 that selects to the output thereof the input directly coupled to L ⁇ , L,, L ⁇ , L 3 and L 4 .
• the apparatus 200 then processes the coefficients Li and Hi in a fashion similar to the fashion in which data elements dj were processed.
• LLO and HL0 are obtained.
• LLi and HLi are obtained and so on.
• the running sums of the operations are stored in 32 bit accumulators included in adders 250 and 251.
• the 32 bit accumulator is advantageous over previous 40 bit and 54 bit accumulators used in digital signal processing. While typically all architectures that perform DWT utilize floating point number representation, the present invention utilizes 16 bit fixed point representation of a fraction. By extracting the 16 left most significant bits of a fraction, one is maintaining as much precision from operation to operation as possible. Since each data element is a 16 bit data element, the results of the additions performed by the add-dividers are also configured to be 16 bit fixed point representations of a fraction.
• Converting numbers from a floating point to a fixed point arithmetic is an operation that is well known in the art.
• unsigned data elements are converted to fixed point fractions by performing a level shift on the data and normalizing the result.
• shifting device 260 receives d0-d4 data elements, each having 16 bits, and converts the values of the data elements into fixed point fractions by first subtracting an offset value which in one embodiment of the present invention is 128. The value 128 is subtracted from the value of each data element so that the values of the data elements are between -128 and 127 and, therefore centered around 0.
• Figure 8 illustrates a flow chart diagram in connection with an embodiment of a process for obtaining coefficients L 0 - L 4 and H 0 - H 4 according to the present invention.
• the process starts at block 802 where index i is assigned the value "0".
• the process then flows to block 804 where data in all registers R Q through R g is shifted to the right by 1.
• register R ⁇ stores data element d 0 .
• the index i is assigned a value of i + 1.
• a new data element is shifted into R Q and the contents of the rest of the registers are shifted to the right by one.
• Data element d 3 is stored in register R Q
• data element d 2 is stored in register R
• data element d is stored in register R 2
• data element d 0 is stored in register R 3 .
• Index "i" is then incremented by "1" therefore becoming equal to "4".
• data in the registers Ro through R 8 is shifted to the right by "1" and register R Q receives the value d j which is d 4 .
• the process performs symmetric copying of data about register R 4 which stores data element do.
• the apparatus that performed this process is configured as illustrated in Figure 3. Coefficients L 0 and H Q are calculated as explained earlier in this description.

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• 1999
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