WO2000049651A9 - Improved masking methods and etching sequences for patterning electrodes of high density ram capacitors - Google Patents

Improved masking methods and etching sequences for patterning electrodes of high density ram capacitors

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Publication number
WO2000049651A9
WO2000049651A9 PCT/US2000/004240 US0004240W WO0049651A9 WO 2000049651 A9 WO2000049651 A9 WO 2000049651A9 US 0004240 W US0004240 W US 0004240W WO 0049651 A9 WO0049651 A9 WO 0049651A9
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WO
WIPO (PCT)
Prior art keywords
layer
noble metal
residual
mask
etching
Prior art date
Application number
PCT/US2000/004240
Other languages
French (fr)
Other versions
WO2000049651A1 (en
Inventor
Jeng H Hwang
Steve S Y Mak
True-Lon Lin
Chentsau Ying
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/251,826 external-priority patent/US6323132B1/en
Priority claimed from US09/251,633 external-priority patent/US6265318B1/en
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Priority to JP2000600301A priority Critical patent/JP2003529914A/en
Publication of WO2000049651A1 publication Critical patent/WO2000049651A1/en
Publication of WO2000049651A9 publication Critical patent/WO2000049651A9/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • 09/251,633 is a continuation-in-part patent application of copending patent application entitled "ETCHING METHODS FOR ANISOTROPIC PLATINUM PROFILE, Serial No. 009/006,092, filed January 13, 1998. Benefit of all earlier filing dates with respect to all common subject matter is claimed.
  • This invention relates to plasma etching of a noble metal (e.g., Pt, Ir, Ru, Pd, etc.). More specifically, this invention provides masking methods and etching sequences for plasma etching of a noble metal, such as platinum and/or iridium, for producing semiconductor integrated circuits containing noble metal (e.g., platinum, iridium, or an oxide or alloy of platinum and/or iridium) electrodes.
  • a noble metal such as platinum and/or iridium
  • semiconductor integrated circuits containing noble metal e.g., platinum, iridium, or an oxide or alloy of platinum and/or iridium
  • DRAM dynamic random access memory
  • the high dielectric constant materials or ferroelectric materials are made primarily of sintered metal oxide and contain a substantial amount of very reactive oxygen.
  • the electrodes In the formation of capacitors with such ferroelectric materials or films, the electrodes must be composed of materials with least reactivity to prevent oxidation of the electrodes which would decrease the capacitance of storage capacitors. Therefore, precious metals, such as platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), etc., are preferred metals used in the manufacture of capacitors for high density DRAM.
  • platinum and iridium have emerged as an attractive candidate because they are inert to oxidation and are known to have a leakage current ( ⁇ 10 "9 amps/cm 2 ) lower than other electrodes such as Ru0 and Pd. Platinum and iridium also are good conductors.
  • platinum and iridium etching has been conducted by means of isotropic etching, such as wet etching with aqua regia, or by anisotropic etching, such as ion milling with Ar gas or by other means. Because of the nature of isotropic etching, using wet etching with aqua regia causes deteriorated processing accuracy. The grade of precision in isotropic etching is not high enough for fine pattern processing. Therefore, it is difficult to perform submicron patterning of platinum electrodes due to its isotropic property.
  • ion milling i.e., anisotropic etching
  • etching speed on platinum and iridium which is to form the electrode
  • etchant gases e.g., Cl 2 , HBr, O 2 , etc.
  • U.S. Patent No. 5,492,855 to Matsumoto et al. discloses a semiconductor device manufacturing method, wherein an insulation layer, a bottom electrode Pt layer, a dielectric film and a top electrode Pt layer are provided on top of a substrate having already-completed circuit elements and wiring, and then, a capacitor is formed by selectively dry etching the bottom electrode Pt layer after selectively dry etching the top electrode Pt layer and the dielectric film.
  • the manufacturing method uses a gas containing an S component as etching gas for Pt etching, or an etching gas containing S component as an additive gas; and also it implants S into the Pt layer before the Pt dry etching process by means of ion implantation to compose a S and Pt compound, and then dry etches the Pt compound thus composed.
  • U.S. Patent No. 5,527,729 to Matsumoto et al. discloses process steps to form on a substrate in which circuit elements and wirings, etc., are already shaped, an insulation layer, a first metal layer, a dielectric film and a second metal layer.
  • a top electrode and a capacitance film are formed by dry etching the second metal layer and the dielectric film.
  • a bottom electrode is formed by dry etching the first metal layer.
  • the etching gas for dry etching the second metal layer is a mixed gas containing hydrogen halide (e.g., HBr) and oxygen, having a ratio of oxygen against the total of hydrogen halide and oxygen set at about 10%-35%.
  • the etching gas is also taught as a gas containing hydrocarbon, such as chloroform.
  • a gas containing hydrocarbon such as chloroform.
  • Matsumoto et al. employs a silicon oxide layer as the insulation layer on the substrate, and a platinum layer or palladium layer as the first and second metal layers. Dry etching of the second metal layer and dielectric film is conducted in a low pressure region not higher than about 5 Pa, where the etching speed is high. Matsumoto et al.
  • the etching speed on the silicon oxide layer can be made sufficiently low relative to that on the second metal layer made of a platinum layer or a palladium layer; in this way, the excessive etching of the silicon oxide layer underlying the first metal layer is avoided, and damage to the circuit elements and wiring, etc. underneath the silicon oxide layer can be prevented.
  • the ratio of etching speed of the platinum and dielectric material to the resist can be increased by lowering the etching speed on the resist.
  • etching of the platinum and dielectric material may be conducted by using a mask of normal lay- thickness resist (generally speaking, about 1.2 ⁇ m to about 2.0 ⁇ m thick), instead of using a conventional thick-layer resist (about 3 ⁇ m and thicker).
  • a mask of normal lay- thickness resist generally speaking, about 1.2 ⁇ m to about 2.0 ⁇ m thick
  • a conventional thick-layer resist about 3 ⁇ m and thicker
  • Nishikawa et al. in an article entitled "Platinum Etching and Plasma Characteristics in RF Magnetron and Electron Cyclotron Resonance Plasmas", Jpn. J. Appl. Phys., Vol. 34 (1995), pages 767-770, discloses a study wherein the properties of platinum etching were investigated using both RF magnetron and electron cyclotron resonance (ECR) plasmas, together with measurement of the plasma parameters (neutral concentration, plasma density, etc.).
  • ECR electron cyclotron resonance
  • Nishikawa et al. performed experiments in Cl 2 plasmas over a pressure ranging from 0.4 to 50 mTorr. In RF magnetron plasmas, the etch rate of Pt was constant at the substrate temperature of from 20 to 160°C.
  • Nishikawa et al. found that the etch rate of Pt was almost constant ( ⁇ 100 nm/min) with gas pressure decreasing from 5 to 0.4 mTorr, while the plasma electron density gradually increased with decreasing gas pressure.
  • the study by Nishikawa et al. discusses these experimental results with respect to the relationship between the etch yield and the ratio of neutral Cl 2 flux and ion flux incident on the substrate.
  • PZT/Pt/TiN/Ti structure with a spin on glass (SOG) mask are demonstrated using a high- density electron cyclotron resonance (ECR) plasma and a high substrate temperature above 300°C.
  • ECR electron cyclotron resonance
  • a 30%-Cl 2 /Ar gas was used to etch a lead zirconate titanate (PZT) film. No deposits remained, which resulted in an etched profile of more than 80°.
  • a 40%- O 2 /Cl 2 gas was used to etch a Pt film. The etching was completely stopped at the Ti layer. 30-nm-thick deposits remained on the sidewall. They were removed by Yokoyama et al. after dipping in hydrochloric acid.
  • the etched profile of a Pt film was more than 80°.
  • the Ti/TiN/Ti layer was etched with pure Cl 2 gas.
  • the size shift from the SOG mask was less than 0.1 ⁇ m. Yokoyama et al. did not detect any interdiffusion between SOG and PZT by transmission electron microscopy and energy dispersive x-ray spectroscopy (TEM-EDX) analysis.
  • Yoo et al. in an article entitled "Control of Etch Slope During Etching of Pt in Ar/Cl 2 /O 2 Plasmas", Jpn. J. Appl. Phys., Vol. 35 (1996), pages 2501-2504, teaches etching of Pt patterns of the 0.25 ⁇ m design rule at 20°C using a magnetically enhanced reactive ion etcher (MERIE).
  • MERIE magnetically enhanced reactive ion etcher
  • the redeposits of the etch products onto the sidewall were reduced by the addition of Cl to Ar, although the etched slope was lowered to 45°.
  • the redeposits were removed by an HCl cleaning process.
  • Kotecki teaches that when considering the use of high-dielectric materials in a stack capacitor structure, the following issues need to be addressed: electrode patterning, high-dielectric material/barrier interaction, electrode/high-dielectric material interaction, surface roughness (e.g., hilocking, etc.), step coverage, high-dielectric material uniformity (e.g., thickness, composition, grain size/orientation, etc.), and barrier (e.g., O 2 and Si diffusion, conductivity, contact resistance and interactions, etc.).
  • Milkove et al. reported in a paper entitled "New Insight into the Reactive Ion Etching of Fence-Free Patterned Platinum Structures" at the 43rd Symposium of AVS, October 1996, Philadelphia, PA, that an investigation was undertaken to characterize the time progression of the Pt etch process during the reactive ion etching (RIE) offence-free patterned structures.
  • the experiment by Milkove et al. consisted of coprocessing two oxidized Si wafers possessing identical 2500 A thick Pt film layers, but different photoresist (PR) mask thicknesses. Etching was suspended at 20, 40, 60 and 80%) of the full etch process in order to cleave off small pieces of wafer for analysis by a scanning electron microscopy (SEM).
  • SEM scanning electron microscopy
  • Keil et al. teaches in an article entitled "The Etching of Platinum Electrodes for PZT Based Ferroelectric Devices", Electrochemical Society Proceedings, Vol. 96-12 (1996), pages 515-520, that the technical difficulties of fabricating capacitors employing platinum Pt etching is most often dominated by sputtering processes. While oxygen and/or various gaseous chlorides or fluorides are used to chemically enhance the etch process, the products of both etch mechanisms are usually of low volatility and tend to redeposit on the wafer. After etching, large wall-like structures extend up from the edges of the Pt region.
  • noble metal e.g., platinum, iridium, ruthenium, etc. and oxides and/or alloys of noble metals
  • a semiconductor device including a plurality of platinum or iridium electrodes having a platinum or iridium profile equal to or greater than about 85° and separated by a distance equal to or less than about 0.35 ⁇ m, preferably equal to or less than about 0.3 ⁇ m, with each electrode having a critical dimension (e.g., a width) equal to or less than about 0.35 ⁇ m, preferably equal to or less than about 0.3 ⁇ m.
  • a critical dimension e.g., a width
  • the present invention broadly provides a method of etching a platinum layer disposed on a substrate comprising the steps of: a) providing a substrate supporting a platinum layer; b) heating the substrate (such as with a pedestal supporting the substrate) of step (a) to a temperature greater than about 150°C; and c) etching the platinum layer including employing a high density plasma of an etchant gas comprising a halogen-containing gas (e.g., a halogen such as chlorine) and a noble gas (e.g., argon) to produce the substrate supporting at least one etched platinum layer.
  • a halogen-containing gas e.g., a halogen such as chlorine
  • a noble gas e.g., argon
  • the present invention broadly provides: a) providing a substrate supporting an iridium layer; b) heating the substrate of step (a) to a temperature greater than about 150°C; and c) etching the iridium layer including employing a high density plasma of an etchant gas comprising a halogen-containing gas, and a noble gas to produce said substrate supporting at least one etched iridium layer.
  • the etchant gas may additionally include a gas selected from the group consisting of O 2 and BC1 3 .
  • the etchant gas may additionally include a gas selected from the group consisting of O 2 , HCl, HBr, and mixtures thereof.
  • the substrate of step (a) may be heated by heating the pedestal supporting the substrate to a sufficient temperature to cause the substrate to possess a temperature greater than about 150°C.
  • the platinum layers are preferably a platinum electrode layer and an iridium electrode layer, respectively.
  • the high density plasma of an etchant gas is a plasma of an etchant gas having an ion density greater than about 10 9 /cm 3 , preferably greater than about 10 ⁇ /cm 3 .
  • the etchant gas may also include a gas selected from the group consisting of BC1 3 , HBr, SiC-U and mixtures thereof.
  • the platinum layer and the iridium layer may each additionally comprise a mask layer disposed on a selected part of the particular respective layer to selectively protect the particular respective layer during the etching step above.
  • the etchant gas having Ar/Cl 2 /O chemistry with high O concentration produces an iridium to Ti and/or TiN selectivity of greater than about 8 (preferably greater than about 10) during etching of iridium.
  • the platinum layer and the iridium layer may each also additionally comprise a protective layer disposed on the selected part of the particular respective layer between the mask layer and the particular respective layer.
  • the mask layer may be removed during or after the etching step.
  • the protective layer may be removed during or after the etching step.
  • the platinum layer is part of or is contained in a platinum wafer, and the method of etching a platinum layer additionally comprises disposing the platinum wafer including the platinum layer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step in the high density plasma chamber under the following process conditions:
  • Halogen Gas e.g., Cl 2 20% to 95% by vol.
  • RF Frequency of Wafer Pedestal 100 K to 300 MHz there is broadly provided a method of etching a platinum electrode layer disposed on a substrate comprising the steps of:
  • step (b) heating said substrate of step (a) to a temperature greater than about 150°C;
  • the plasma may be a low density plasma or a high density plasma and the etchant gas may additionally comprise a gas selected from the group consisting of a noble gas (e.g., argon), HBr, BC1 3 , SiCL, and mixtures thereof.
  • the etching step (c) may be performed in a low density (or high density) plasma chamber under the following process conditions:
  • Halogen Gas e.g., Cl 40% to 90% by vol.
  • Nitrogen gas 0.1% to 60% by vol.
  • the etched platinum layer includes a platinum profile equal to or greater than about 80°, preferably equal to or greater than about 85°, more preferably equal to or greater than about 87°, most preferably equal to or greater than about 88.5°.
  • the etchant gas for the process conditions immediately above may alternatively comprise from about 10% to about 90% by vol. of a halogen (e.g., Cl 2 ), from about 5% to about 80% by vol. of a noble gas (e.g., argon), and from about 4% to about 25%) by vol. HBr and/or BC1 3 .
  • the etchant gas may alternatively comprise from about 0.1% to about 60% by volume nitrogen, from about 40% to about 90% by volume of a halogen (e.g., Cl 2 ), from about 0.1% to about 40% by volume of a noble gas (e.g., argon), and from about 1% to about 30%) by volume of a gas selected from the group of combining HBr, BC1 3 , SiCl 4 , and mixtures thereof.
  • a halogen e.g., Cl 2
  • a noble gas e.g., argon
  • the iridium layer is part of or is contained in an iridium wafer, and the method of etching an iridium layer additionally comprises disposing the iridium wafer including the iridium layer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following process conditions:
  • Halogen Gas e.g., Cl 2 ) 10% to 60% by vol.
  • the etched iridium layer includes an iridium profile equal to or greater than about 80°, more preferably equal to or greater than about 82°, most preferably equal to or greater than about 85.0°.
  • the etchant gas for the process conditions immediately above may alternatively comprise from about 5% to about 20%> by vol. oxygen, from about 10%> to about 60%) by vol. of a halogen (e.g., Cl 2 ), from about 30% to about 80% by vol. of a noble gas (e.g., argon), and from about 5% to about 20% by vol. HBr and/or HCl.
  • the present invention also broadly provides a method for producing a capacitance structure including an electrode (i.e., a platinum electrode or an iridium electrode layer) comprising the steps of: a) providing a substrate supporting a layer (i.e., a platinum electrode layer or an iridium electrode layer), and at least one mask layer disposed on a selected part of said layer; b) heating the substrate of step (a) to a temperature greater than about 150°C; and c) .
  • an electrode i.e., a platinum electrode or an iridium electrode layer
  • etching the layer including employing a plasma of an etchant gas comprising a halogen (e.g., chlorine) and a noble gas (e.g., argon) to produce a capacitance structure having at least one electrode (i.e., the platinum electrode or iridium electrode).
  • an etchant gas comprising a halogen (e.g., chlorine) and a noble gas (e.g., argon) to produce a capacitance structure having at least one electrode (i.e., the platinum electrode or iridium electrode).
  • the etchant gas may also comprise nitrogen.
  • the at least one mask layer is removed during or after the etching step (c) immediately above.
  • the layer of step (a) immediately above may additionally comprise a protective layer disposed on the selected part of the layer between the mask layer and the layer.
  • the etched layer (i.e., the etched platinum layer or the etched iridium layer) produced by the etching step (c) immediately above includes a profile (i.e., a platinum profile or an iridium profile) equal to or greater than about.80° (particularly for iridium), preferable equal to or greater than about 85°, more preferably equal to or greater than about 87°, most preferably equal to or greater than about 88.5°.
  • the etchant gas of the plasma of step (c) more specifically includes a halogen (e.g., chlorine), a noble gas (e.g., argon), and a gas selected from the group consisting of HBr, BC1 3 and mixtures thereof.
  • the etchant gas of the plasma of step (c) includes nitrogen (N ) and a halogen (e.g., chlorine).
  • the etchant gas of the plasma of step (c) more specifically includes nitrogen (N 2 ), a halogen (e.g., chlorine), a noble gas (e.g., argon), and a gas selected from the group consisting of HBr, BC1 3 , SiCl , and mixtures thereof.
  • the platinum electrode layer is part of or is contained in a platinum electrode wafer, and the method for producing a capacitance structure including a platinum electrode layer additionally comprises disposing, prior to the etching step (c), the platinum electrode wafer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following previously indicated process conditions:
  • Halogen Gas e.g., Cl 2 ) about 10% to about 90% by vol.
  • Noble Gas e.g., Ar
  • Noble Gas about 5% to about 80% by vol.
  • HBr and or BC1 3 about 4% to about 25% by vol.
  • the produced platinum electrodes are separated by a distance or space having a dimension equal to or less than about 0.35 ⁇ m, preferably equal to or less than about 0.3 ⁇ m.
  • Each of the platinum electrodes include a dimension having a value equal to or less than about 0.6 ⁇ m, preferably equal to or less than about 0.35 ⁇ m, more preferably equal to or less than about 0.3 ⁇ m. More preferably, each of the platinum electrodes have a width equal to or less than about 0.35 ⁇ m, preferably equal to or less than about 0.3 ⁇ m, a length equal to or less than about 1.0 ⁇ m, preferably equal to or less than about 0.6 ⁇ m, and a height equal to or less than about 0.6 ⁇ m.
  • the plasma of the etchant gas for etching any of the metals of any of the embodiments of the present invention comprises a high density inductively coupled plasma.
  • the etchant gas preferably comprises a noble gas selected from the group consisting of helium, neon, argon, krypton, xenon, radon, and mixtures thereof. More preferably, the noble gas is selected from the group consisting of helium, neon, argon, and mixtures thereof. Most preferably, the noble gas is argon.
  • the etchant gas of the high density inductively coupled plasma most preferably comprises, or preferably consists of or consists essentially of, chlorine, argon, and BC1 3 and/or HBr.
  • the etchant gas of the plasma of step (c) more specifically includes oxygen, a halogen (e.g., chlorine), a noble gas (e.g., argon), and a gas selected from the group consisting of HBr, HCl and mixtures thereof.
  • a halogen e.g., chlorine
  • a noble gas e.g., argon
  • the iridium electrode layer is part of or is contained in an iridium electrode wafer, and the method for producing a capacitance structure including an iridium electrode layer additionally comprises disposing, prior to the etching step (c), the iridium electrode wafer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following previously indicated process conditions:
  • Oxygen about 5% to about 20% by vol.
  • Halogen Gas e.g., Cl ) about 10% to about 60% by vol.
  • HBr and/or HCl about 5% to about 20% by vol.
  • Iridium Electrode Wafer about 150° to about 500° C
  • the plasma of the etchant gas for etching iridium comprises a high density inductively coupled plasma.
  • the etchant gas preferably comprises a noble gas selected from the group consisting of helium, neon, argon, krypton, xenon, radon, and mixtures thereof. More preferably, the noble gas is selected from the group consisting of helium, neon, argon, and mixtures thereof. Most preferably, the noble gas is argon.
  • the etchant gas of the high density inductively coupled plasma for etching iridium most preferably comprises, or preferably consists of or consists essentially of, chlorine, argon, and oxygen or BC1 3 ; alternatively, oxygen, chlorine, argon, and HCl and/or HBr.
  • the present invention further broadly provides a method of manufacturing a semiconductor device comprising the steps of: a) forming a patterned resist layer, a mask layer and an electrode layer (e.g., a platinum electrode layer or an iridium electrode layer) on a substrate having circuit elements formed thereon; b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the electrode layer to produce the substrate supporting the patterned resist layer, a residual mask layer, and the electrode layer; c) removing the resist layer of step (b) to produce the substrate supporting the residual mask layer and the electrode layer; d) heating the substrate of step (c) to a temperature greater than about 150° C; and e) etching the electrode layer of step (d) including employing a high density plasma of an etchant gas.
  • an electrode layer e.g., a platinum electrode layer or an iridium electrode layer
  • the etchant gas preferably comprises a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce a semiconductor device having at least one platinum electrode.
  • the etchant gas comprises oxygen, a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce a semiconductor device having at least one iridium electrode.
  • the present invention also further broadly provides a method of etching an electrode layer (e.g.
  • a noble metal disposed on a substrate comprising the steps of: a) providing a substrate (e.g., a SiO 2 substrate) supporting an electrode layer (e.g., a noble metal including a platinum electrode layer or an iridium electrode layer), a protective layer (e.g., TiN and/or Ti) on the electrode layer, and a mask layer (e.g., BSG oxide, BPSG oxide, PSG oxide, Si 3 N 4 , TEOS, CVD SiO 2 , and mixtures thereof) on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the protective layer to expose part of the protective layer and to produce the substrate supporting the electrode layer, the protective layer on the electrode layer, a residual mask layer on the elecfrode layer, and the patterned resist layer on the residual mask layer; c) removing the patterned resist layer from
  • the exposed part of the protective layer includes a high density plasma of an etchant gas.
  • the elecfrode layer being etched comprises a platinum
  • the etchant gas comprises a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce the substrate supporting an etched platinum electrode layer having the residual protective layer on the etched platinum layer, and the residual mask layer on the residual protective layer.
  • the etchant gas comprises oxygen, a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce the subsfrate supporting an etched iridium electrode layer having the residual protective layer on the etched iridium electrode layer, and the residual mask layer on the residual protective layer.
  • a halogen gas e.g., chlorine
  • a noble gas e.g., argon
  • the electrode layer (e.g., the noble metal including a platinum elecfrode layer or an iridium electrode layer) is part of or is contained in a wafer (e.g., the noble metal including a platinum electrode wafer or an iridium elecfrode wafer).
  • the purpose of the protective layer is to ensure the adhesion between the mask layer and the elecfrode layer (e.g., the profile of a platinum electrode layer or the profile of an iridium elecfrode layer), and also to maintain the profile of the layer (e.g., a platinum electrode layer or an iridium electrode layer), especially during the etching process of the present invention.
  • the residual protective layers are removed from the etched layer (e.g., etched platinum layer and/or etched iridium layer), after the etching step (e.g., the platinum etching step or the iridium etching step).
  • the etched layer e.g., etched platinum layer and/or etched iridium layer
  • the etching step e.g., the platinum etching step or the iridium etching step.
  • one or more barrier layers may be disposed on the substrate to separate the electrode layer (e.g. a noble metal layer) from the substrate.
  • the barrier layer may include TiN and/or Ti and/or BST (barium titanate and/or strontium titanate) and/or Si 3 N 4 .
  • the barrier layer may also include two or more barrier layers such as a SiN-containing layer (e.g., Si 3 N ) disposed on the substrate and a barrier protective layer (e.g., TiN and/or Ti) disposed on the SiN-containing layer.
  • the electrode layer e.g. the noble metal layer
  • a method of etching a noble metal (Pt, Ir, Ru, Pd etc.) layer disposed on a subsfrate comprising the steps of: a) providing a substrate supporting a barrier layer (e.g., TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta), a noble metal (e.g., Pt, Ir, Pd, Ru, etc.) layer on the barrier layer, a protective layer (e.g., TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta) on the noble metal layer, a mask layer, preferably a mask layer having a thickness ranging from about 6000A to about 9,OO ⁇ A, on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of a mask etchant gas to break through and to remove the portion of the mask layer from the protective layer to expose part of
  • step (d) etching the exposed part of the noble metal layer of step (d) including employing plasma of an etchant gas selected from the group consisting of a halogen-containing gas, a noble gas, nitrogen, oxygen, and mixtures thereof, to produce the substrate supporting the barrier layer, an etched noble metal layer on the barrier layer, the residual protective layer on the etched noble metal layer, and the residual mask layer on the residual protective layer; g) removing the residual mask layer from the residual protective layer to produce the subsfrate supporting the barrier layer, the etched noble metal layer on the barrier layer, and the residual protective layer on the etched noble metal layer; and h) etching a portion of the barrier layer including employing a plasma of a barrier etchant gas to expose part of the subsfrate to produce the substrate supporting a residual barrier layer, the etched noble metal layer on the residual barrier layer, and the residual protective layer on the etched noble metal layer.
  • an etchant gas selected from the group consisting of a halogen-containing gas, a
  • the step (f) etching of the noble metal layer of step (d) additionally produces a remaining noble metal layer on the barrier layer.
  • the step (g) removing of the residual mask layer additionally produces the remaining noble metal layer on the barrier layer, and the method additionally comprises etching the remaining noble metal layer on the barrier layer prior to the step (h) etching.
  • the mask layer comprises a compound selected from the group consisting of BSG oxide, PSG oxide, Si 3 N 4 , TEOS, CVD SiO 2 , a low dielectric constant material with a dielecfric constant of less than 3.0, and mixtures thereof.
  • the foregoing method may be conducted without the protective layer.
  • the foregoing method may also be conducted by etching the barrier layer prior to removing the residual mask layer.
  • the method of etching a noble metal layer disposed on a subsfrate would comprise the following step (g) and step (h): (g) etching a portion of the barrier layer including employing a plasma of a barrier etchant gas to expose part of the substrate to produce the subsfrate supporting a residual barrier layer, the etched noble metal layer on the residual barrier layer, the residual protective layer on the etched noble metal layer, and the residual mask layer on the residual protective layer; and (h) removing the residual mask layer from the residual protective layer to produce the substrate supporting the residual barrier layer, the etched noble metal layer on the residual barrier layer, and the residual protective layer on the etched noble metal layer.
  • a method of etching a noble metal (Pt, Ir, Ru, Pd etc.) layer disposed on a substrate comprising the steps of: a) providing a subsfrate supporting an etch-stop layer (e.g., Si 3 N 4 , TiO 2 , RuO 2 , and IrO 2 ), a barrier layer on the etch-stop layer, a noble metal layer on the barrier layer, a protective layer on the noble metal layer, a mask layer, preferably a mask layer having a thickness ranging from about 6000A to about 9000A, on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of a mask etchant gas to break through and to remove the portion of the mask layer from the protective layer to expose part of the protective layer and to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, the noble metal layer on the
  • the foregoing method may be conducted without the protective layer.
  • the method of etching additionally comprises etching the exposed part of the barrier layer to expose part of the etch-stop layer to produce the substrate supporting the etch-stop layer, a residual barrier layer on the etch-stop layer, and the etched noble metal layer on the residual barrier layer.
  • a method of etching a noble metal (Pt, Ir, Ru, Pd etc.) layer disposed on a substrate comprising the steps of: a) providing a substrate supporting an etch-stop layer, a barrier layer on the etch-stop layer, a noble metal layer on the barrier layer, a mask layer on the noble metal layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including a plasma of a mask- etchant gas to break through and to remove the portion of the mask layer from the noble metal layer to expose part of the noble metal layer and to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, the noble metal layer on the barrier layer, a residual mask layer on the noble metal layer, and the patterned resist layer on the residual mask layer; c) removing the patterned resist layer from the residual mask layer of step (b) to produce the substrate supporting the etch-stop layer, the barrier layer on the a barrier layer on the barrier layer on the barrier layer
  • the method of etching additionally includes etching the exposed part of the barrier layer, preferably prior to the removing step (f), to expose part of the etch-stop layer to produce the substrate supporting the etch-stop layer, a residual barrier layer on the etch-stop layer, and the etched noble metal layer on the residual barrier layer.
  • Also provided in accordance with an embodiment of the present invention is a method of etching a noble metal layer disposed on a substrate comprising the steps of: a) providing a subsfrate supporting a barrier layer, a noble metal layer on the barrier layer, a first mask layer on the noble metal layer, a second mask layer on the first mask layer, and a patterned resist layer on the second mask layer; b) etching a portion of the second mask layer including employing a plasma of a mask etchant gas to break through and to remove the portion of the second mask layer from the first mask layer to expose part of the first mask layer and to produce the subsfrate supporting the barrier layer, the noble metal layer on the barrier layer, the first mask layer on the noble metal layer, a residual second mask layer on the first mask layer, and the patterned resist layer on the residual second mask layer; c) etching the exposed part of the first mask layer to expose part of the noble metal layer and to produce the substrate supporting the barrier layer, the noble metal layer on the barrier layer, a residual
  • the residual second mask layer in step(f) is removed and/or etched simultaneously with the step(f) etching and/or removal of the exposed part of the noble metal layer.
  • the patterned resist layer may be removed from the residual second mask layer during the etching step (c).
  • the etching step (h) additionally comprises etching into the substrate.
  • the first mask layer comprises a compound selected from the group consisting of Si 3 N , BSG, PSG, BPSG, an organic polymer, a low dielectric constant material having a dielectric constant of less than about 3.0, and mixtures thereof.
  • the second mask layer comprises a compound selected from the group consisting of CVD SiO 2 , TEOS, Si 3 N 4 , BSG, PSG, BPSG, SiC, and mixtures thereof.
  • the first mask layer has a thickness ranging from about 3000A to about 8000A, and the second mask layer has a thickness ranging from about 500A to about 4000 A.
  • etching of the platinum electrode layer to produce the platinum electrodes of the present invention is preferably performed in a high density plasma chamber.
  • the platinum etching step employs a high density plasma of an etchant gas preferably consisting of, or consisting essentially of, a halogen gas (e.g., chlorine), a noble gas (i.e., argon) and HBr and/or BC1 3 .
  • a halogen gas e.g., chlorine
  • a noble gas i.e., argon
  • BC1 3 a halogen gas
  • the high density plasma chamber possesses a separate control for ion flux and a separate control for ion energy.
  • the ion density of the high density plasma in the high density plasma chamber is greater than about 10 9 /cm 3 .
  • the high density plasma chamber for the method of manufacturing a semiconductor device and for the method of etching a platinum electrode layer disposed on a subsfrate includes a coil inductor and a wafer pedestal; and the platinum etching step in both of the methods is performed in the high density plasma chamber under the following previously mentioned process conditions:
  • Halogen Gas e.g., Cl ) about 10% to about 90% by vol.
  • Noble Gas e.g., argon
  • HBr and or BC1 3 about 4% to about 25% by vol.
  • the etching step may be performed in a low density (or high density) plasma chamber under the following process conditions:
  • Halogen Gas e.g., Cl 2
  • Cl 2 Halogen Gas
  • Noble Gas e.g., argon
  • etching of the iridium electrode layer to produce the iridium electrodes of the present invention is performed in a high density plasma chamber.
  • the iridium etching step employs a high density plasma or a low density plasma of an etchant gas preferably consisting of, or consisting essentially of, or consisting essentially of, a halogen gas (e.g., chlorine) and a noble gas (i.e., argon), more preferably a halogen gas (e.g., chlorine), a noble gas (i.e., argon) and oxygen or BC1 3 , or oxygen (O 2 ), a halogen gas (e.g., Cl 2 ), a noble gas (e.g., Ar), and HCl and/or HBr.
  • the high density plasma chamber possesses a separate control for ion flux and a separate control for ion energy.
  • the ion density of the high density plasma in the high density plasma chamber is greater than about 10 9
  • the high density plasma chamber for the method of manufacturing a semiconductor device and for the method of etching an iridium elecfrode layer disposed on a subsfrate includes a coil inductor and a wafer pedestal; and the iridium etching step in both of the methods is performed in a high density plasma chamber under the following previously mentioned process conditions:
  • Halogen Gas e.g., Cl 2 ) about 10% to about 60% by vol.
  • Iridium Electrode Wafer about 150° to about 500°C
  • the present invention also provides a method of processing a layer on a substrate comprising the steps of: a) providing a substrate; b) disposing the substrate in a reactor chamber comprising a dielectric window including a deposit-receiving surface having a peak-to- valley roughness height with an average height value of greater than about 1000 A; c) introducing a processing gas into the reactor chamber of step (b); and d) introducing processing power into the reactor chamber of step (b) to process a layer on the substrate in a plasma of the processing gas.
  • the present invention further provides a dielectric member comprising a dielectric structure including a surface finish having a peak-to-valley roughness height with an average height value of greater than about 1000 A.
  • a pedestal assembly is disposed in the processing zone.
  • the chamber assembly also comprises a processing power source; a processing gas-introducing assembly, engaged to the chamber wall, for introducing a processing gas into the processing zone of the chamber wall; and a processing power- transmitting member connected to the processing power source for transmitting power into the processing zone to aid in sustaining a plasma from a processing gas within the processing zone of the processing chamber wall.
  • the present invention yet also further broadly provides a semiconductor device, more specifically a capacitance structure, comprising a subsfrate, and at least two noble metal electrodes (e.g., platinum elecfrodes or iridium elecfrodes) supported by the substrate.
  • the electrodes have a profile equal to or greater than about 80°, such as equal to or greater than about 85°, preferably equal to or greater than about 87°, more preferably equal to or greater than about 88.5°.
  • the electrodes are separated by a distance or space having a dimension equal to or less than about 0.35 ⁇ m, preferably equal to or less than about 0.3 ⁇ m.
  • Each of the electrodes include a dimension having a value equal to or less than about 1.0 ⁇ m, preferably equal to or less than about 0.6 ⁇ m, more preferably equal to or less than about 0.35 ⁇ m, most preferably equal to or less than about 0.3 ⁇ m. More preferably, each of the elecfrodes have a width equal to or less than about 0.35 ⁇ m, preferably equal to or less than about 0.3 ⁇ m, a length equal to or less than about 1.0 ⁇ m, preferably equal to or less than about 0.6 ⁇ m, and a height equal to or less than about 0.6 ⁇ m.
  • a method of etching an iridium (i.e., a noble metal layer) layer disposed on a substrate comprising the steps of: a) providing a substrate supporting an iridium layer; b) heating the subsfrate of step (a) of a temperature greater than about 150°C; and c) etching the iridium layer including employing a plasma of an etchant gas (i.e., a low density or high density plasma of an etchant gas) comprising a halogen containing gas (e.g., chlorine) and a noble gas (e.g., argon) to produce the subsfrate supporting at least one etched iridium layer.
  • an etchant gas i.e., a low density or high density plasma of an etchant gas
  • a halogen containing gas e.g., chlorine
  • a noble gas e.g., argon
  • the etchant gas additionally comprises a gas selected from the group consisting of O 2 and BC1 3 .
  • the etchant gas additionally comprises a gas selected from the group consisting of O , HCl, HBr, and mixtures thereof.
  • the halogen containing gas comprises or consists essentially of chlorine and the noble gas comprises or consists essentially of argon.
  • the etchant gas comprises or consists essentially of chlorine, argon and O 2 .
  • the iridium layer of step (a) additionally comprises a mask layer (e.g., a TiN or Ti mask layer) disposed on a selected part of the iridium layer to selectively protect the iridium layer during the etching step (c).
  • a mask layer e.g., a TiN or Ti mask layer
  • the present invention also provides a method of etching an iridium electrode layer disposed on a substrate comprising the steps of: a) providing a substrate supporting an iridium electrode layer, a protective layer on the iridium electrode layer, a Ti mask layer on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the Ti mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the Ti mask layer from the iridium elecfrode layer to expose part of the protective layer and to produce the subsfrate supporting the iridium elecfrode layer, the protective layer on the iridium electrode layer, a residual Ti mask layer on the protective layer, and the patterned resist layer on the residual Ti mask layer; c) removing the patterned resist layer from the residual Ti mask layer of step (b) to produce the substrate supporting the iridium electrode layer, the protective layer on the iridium elecfrode layer, and the residual mask layer on
  • the present invention further also provides a method of etching an iridium electrode layer disposed on a substrate comprising the steps of: a) providing a subsfrate supporting an iridium electrode layer, a protective layer on the iridium electrode layer, a mask layer on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the iridium electrode layer to expose part of the protective layer and to produce the substrate supporting the iridium electrode layer, the protective layer on the iridium electrode layer, a residual mask layer on the protective layer, and the patterned resist layer on the residual mask layer; c) etching the exposed part of the protective layer to expose part of the iridium electrode layer and to produce the substrate supporting the iridium elecfrode layer, a residual protective layer on the iridium electrode layer, the residual mask layer on the residual protective layer, and the
  • the etchant gas of step (f) additionally comprises a gas selected from the group consisting of oxygen, HCl, HBr and mixtures thereof. More specifically the etchant gas comprises, preferably consists of or consists essentially of, oxygen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, HCl and mixtures thereof.
  • the halogen i.e., chlorine
  • the noble gas i.e., argon
  • the etchant gas more specifically comprises, or consists of or consists essentially of, from about 5%> by volume to about 20% by volume oxygen, from about 10% by volume to about 60%> by volume of the halogen gas (i.e., chlorine) and from about 30% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or HCl; preferably from about 5% by volume to about 15% by volume oxygen, from about 20% by volume to about 50% by volume of the halogen gas (i.e., chlorine) and from about 40% by volume to about 70% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15%> by volume of HBr and/or HCl; and more preferably from about 5% by volume to about 10% by volume oxygen, from about 20% by volume to about 35% by volume of the halogen gas (i.e., chlorine) and from about 40%> by volume to about 60%) by volume of the
  • the process parameters for etching an elecfrode layer in a suitable inductively coupled plasma reactor fall into the ranges as Hsted below on the basis of rates of the gases, including oxygen, the halogen gas(es) (i.e., Cl 2 ), the noble gas(ses) (i.e., Ar), and HBr and/or HCl.
  • FIG. 1 is a side elevational view of a semiconductor wafer having a semiconductor substrate, a banier layer disposed on the semiconductor substrate, a platinum elecfrode layer disposed on the barrier layer, a mask layer disposed on the platinum elecfrode layer, and a patterned resist disposed on the mask layer;
  • Fig. 2 is a side elevational view of the semiconductor wafer of Fig. 1 additionally including a protective layer disposed on the platinum electrode layer between the mask layer and the platinum elecfrode layer;
  • Fig. 3 is a vertical sectional view of a prior art plasma processing apparatus including a plasma etching reactor with an electromagnetic unit for enhancing a plasma;
  • Fig. 4 is a diagram of a flux produced by a magnetic field and illustrated as rotating around a center axis
  • Fig. 5 is a side elevational view of the semiconductor wafer of Fig. 1 after etching and removing a portion of the mask layer from the surface of the platinum elecfrode layer to expose the platinum elecfrode layer;
  • Fig. 6 is a side elevational view of the semiconductor wafer of Fig. 2 after etching and removing a portion of the mask layer from the surface of the protective layer to expose the protective layer;
  • Fig. 7 is a side elevational view of the semiconductor wafer of Fig. 5 after the patterned resist layer has been removed from a portion of the mask layer with the removed patterned resist layer being represented as broken lines;
  • Fig. 8 is a side elevational view of the semiconductor wafer of Fig. 6 after etching and removing a portion of the protective layer off of the surface of the platinum layer, and after removing the patterned resist layer from a portion of the mask layer with the removed patterned resist layer being represented as broken lines;
  • Fig. 9 is a side elevational view of the semiconductor wafer of Fig. 7 after the platinum electrode layer has been etched to produce an etched platinum electrode layer
  • Fig. 10 is a side elevational view of the semiconductor wafer of Fig. 8 after the platinum elecfrode layer has been etched to produce an etched platinum elecfrode layer;
  • Fig. 11 is a side elevational view of the semiconductor wafer of Fig. 7 after the platinum elecfrode layer has been etched to produce an etched platinum elecfrode layer with a residual mask layer on top thereof;
  • Fig. 12 is a side elevational view of the semiconductor wafer of Fig. 8 after the platinum electrode layer has been etched to produce an etched platinum electrode layer with a residual mask layer on top of the residual protective layer;
  • Fig. 13 is a side elevational view of the semiconductor wafer of Fig. 11 with the residual mask layer removed from the surface of the etched platinum elecfrode layer;
  • Fig. 14 is a side elevational view of the semiconductor wafer of Fig. 12 with the residual mask layer and the residual protective layer removed from the surface of the etched platinum electrode layer;
  • Fig. 15 is a side elevational view of semiconductor wafer of Fig. 11 after the residual mask layer has been removed from the surface of the etched platinum elecfrode layer and with the banier layer having been etched;
  • Fig. 16 is a side elevational view of semiconductor wafer of Fig. 12 after the residual mask layer and the residual protective layer have been removed from the surface of the etched platinum electrode layer and with the barrier layer having been etched;
  • Fig. 17 is a simplified cut-away view of an inductively coupled RF plasma reactor which may be employed in etching the platinum elecfrode layer to produce a semiconductor device;
  • Fig. 18 is a simplified cut-away view of another inductively coupled RF plasma reactor which may be employed in etching the platinum elecfrode layer to produce a semiconductor device;
  • Fig. 19 is a picture showing an elevational view of a test semiconductor wafer for Example I after the platinum elecfrode layer was etched in accordance with the process conditions listed in Example I;
  • Fig. 20 is a picture showing an elevational view of the test semiconductor wafer of Fig. 19 after the oxide mask was removed;
  • Fig. 21 is a drawing representing the elevational view in the picture of Fig.
  • Fig. 22 is a drawing representing the elevational view in the picture of Fig.
  • Fig. 23 is a picture showing an elevational view of a test semiconductor wafer for Example II after the platinum elecfrode layer was etched in accordance with the process conditions listed in Example II;
  • Fig. 24 is a drawing representing the elevational view on the picture of
  • Fig. 25 is a side elevational view of a semiconductor wafer having a semiconductor substrate, an etch-stop layer disposed on the semiconductor substrate, a barrier layer disposed on the etch-stop layer, a platinum elecfrode layer disposed on the barrier layer, a protective layer disposed on the platinum electrode layer and a patterned mask layer disposed on the protective layer;
  • Fig. 26 is a schematic diagram illustrating masking and etching sequences for another embodiment of the invention.
  • Fig. 27 is a schematic diagram illustrating masking and etching sequences for a further embodiment of the invention.
  • Fig. 28 is a schematic diagram illustrating masking and etching sequences for yet another embodiment of the invention.
  • Fig. 29 is a schematic diagram illustrating masking and etching sequences for yet a further embodiment of the invention.
  • Fig. 30 is a picture show the test semiconductor wafer of Example III after the TEOS mask layer was removed;
  • Fig. 31 is a picture of an elevational view of the test semiconductor wafer of Example IV after the SiLK® brand mask layer of the test semiconductor was etched in the DPSTM brand chamber;
  • Fig. 32 is a picture of an elevational view of the test semiconductor wafer of Example IN after the platinum layer and the Ti ⁇ (i.e., a barrier layer) was etched in the DPSTM brand chamber;
  • Fig. 33 is a picture of an elevational view of the test semiconductor wafer of Example IN after the SiLK® brand mask layer was removed or stripped from the etched platinum layer in an ASP chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus;
  • Fig. 34 is a top plan view picture of the etched platinum layer of Fig. 33;
  • Fig. 35 is a partial exploded sectional view of the inductively coupled RF plasma reactor of Fig. 17 illustrating the dome-shaped dielectric ceiling;
  • Fig. 36 is a partial side elevational view of a surface finish of a deposit- receiving surface of a dielectric member (i.e., a dielecfric window or the dome-shaped dielecfric ceiling);
  • Fig. 37 is a picture showing an elevational view of a test semiconductor wafer for Example N after the platinum elecfrode layer was etched in accordance with the process conditions listed in Example N;
  • Fig. 38 is a drawing representing the elevational view of the picture of Fig. 37 with the respective parts identified by reference numerals;
  • Fig. 39 is a picture showing an elevational view of a test semiconductor wafer for Example NI after the platinum elecfrode layer was etched in accordance with the process conditions listed in Example VI;
  • Fig. 40 is a drawing partially representing the elevational view of the picture of Fig. 39 with the respective parts identified by reference numerals;
  • Fig. 41 is a partial perspective view of a dome-shaped dielectric ceiling having an inside concave surface
  • Fig. 42 is a partial sectional view of the dome-shaped dielectric ceiling of Fig. 41 after its associated inside concave surface has received a deposit of by-product materials in accordance with Example VII;
  • Fig. 43 is a partial sectional view of the dome-shaped dielecfric ceiling of Fig. 41 after its associated inside concave surface has received a deposit of by-product materials in accordance with Example VIII;
  • Fig.44 is a partial exploded sectional view of a dome-shaped dielectric ceiling having a roughened inside concave surface that has received a deposit of byproduct materials in accordance with Example IX;
  • Fig. 45 is a picture showing an elevational view of a test semiconductor wafer for Example X after an iridium electrode layer was etched in accordance with the process conditions listed in Example X;
  • Fig. 46 is a drawing representing the elevational view in the picture of Fig. 45 with respective parts identified by a reference numeral;
  • Fig. 47 is a picture showing an elevational view of a test semiconductor wafer for Example XI after an iridium elecfrode layer was etched in accordance with the process conditions listed in Example XI;
  • Fig. 48 is a drawing representing the elevational view in the picture of Fig. 47 with the respective parts identified by a reference numeral.
  • a wafer generally illustrated as 10, having a semiconductor subsfrate, generally illustrated as 12.
  • the semiconductor substrate 12 preferably comprises silicon dioxide (SiO 2 ) and includes regions of circuit elements which do not appear in the drawings, but are well known to those skilled in the art.
  • the semiconductor substrate 12 comprises a compound selected from the group consisting of tetraethylorthosilicate (TEOS), silicon dioxide, and mixtures thereof.
  • TEOS tetraethylorthosilicate
  • a barrier layer 14 is disposed over the semiconductor substrate 12 and a layer (e.g., an elecfrical conductive layer, such as a noble metal layer [or an oxide or alloy of same] including a platinum layer or an iridium layer, etc.), generally illustrated as 15, is disposed over the barrier layer 14.
  • a layer e.g., an elecfrical conductive layer, such as a noble metal layer [or an oxide or alloy of same] including a platinum layer or an iridium layer, etc.
  • an etch-stop layer 17 is disposed on the semiconductor substrate 12 between the semiconductor substrate 12 and the banier layer 14.
  • the layer 15 is preferably an elecfrode layer 16 as shown in Fig. 1. Because the elecfrode layer 16 is a prefened layer 15, the remaining description of the present invention will use only the term "electrode layer 16" in describing the present invention.
  • electrode layer 16 is stated hereinafter, it is to also have the equivalence of "layer 15" for purposes of the present invention. It is also to be understood that in one prefened embodiment of the present invention "elecfrode layer 16" may be a "platinum elecfrode layer 16" or an "iridium elecfrode layer 16," unless otherwise indicated. Thus, whenever “platinum elecfrode layer 16" is stated or mentioned hereinafter for a prefened embodiment of the invention, it is to be understood that the electrode layer 16 includes platinum and the prefened embodiment of the present invention relates to etching platinum to produce the desired features of the present invention as set forth hereinafter.
  • the elecfrode layer 16 includes iridium and the prefened embodiment of the present invention relates to etching iridium to produce the desired features of the present invention as set forth hereinafter. Because the elecfrode layer 16 easily diffuses or reacts with certain elements (e.g., a poly-Si plug) within the semiconductor substrate 12, the barrier layer 14 is required between the electrode layer 16 and the semiconductor subsfrate 12. The banier layer 14 also functions as an adhesive for coupling the semiconductor subsfrate 12 to the electrode layer 16.
  • a mask 18 is disposed over the elecfrode layer 16 and a patterned resist (i.e., a photoresist), generally illustrated as 20, is selectively positioned on the mask layer 18 as best shown in Fig. 1.
  • the patterned resist 20 includes a plurality of resist members 20a, 20b, 20c, and 20d.
  • a protective layer 22 is disposed between the electrode layer 16 and the mask layer 18.
  • the barrier layer 14 may be any suitable layer which is capable of dually functioning as an adhesive and a diffusion barrier to the electrode layer 16.
  • the barrier layer 14 may be of any suitable thickness.
  • the barrier layer 14 comprises Ta and/or TaN and/or TaSiN and/or WN X and/or titanium and/or a titanium alloy, such as TiN and TiSiN, and possesses a thickness ranging from about 50 Angstroms to about 600 Angsfroms, more preferably from about 200 Angsfroms to about 400 Angsfroms, most preferably about 300 Angsfroms.
  • the barrier layer 14 comprises BST (i.e., barium titanate (BaTiO 3 ) and strontium titanate (SrTiO 3 )).
  • the barrier layer 14 may comprise PZT (Pb(Zr ⁇ - x Ti x )0 3 ) and SBT (SrBi 2 Ti 2 0 9 ).
  • the banier layer 14 functions as a dielecfric for a capacitor.
  • the banier layer 14 is preferably disposed on the semiconductor substrate 12 by the RF magnetron sputtering method.
  • the etch-stop layer 17 as best shown in Fig. 25 may be any suitable layer which is capable of functioning as an adhesive, and, optionally, in conjunction with barrier layer 14 being a diffiision barrier to the elecfrode layer 16.
  • Etch-stop layer 17 may be of any suitable thickness.
  • the etch-stop layer 17 comprises a compound selected from the group consisting of silicon nitride (Si 3 N 4 ), titanium dioxide (TiO 2 ), ruthenium dioxide (RuO 2 ), iridium dioxide (IrO 2 ), and possesses a thickness ranging from about 50 Angsfroms to about 1000 Angsfroms, more preferably from about 200 Angsfroms to about 700 Angstroms, most preferably from about 300 Angsfroms to about 500 Angsfroms, e.g., about 400 Angsfroms.
  • the etch-stop layer 17 is preferably disposed on the semiconductor subsfrate 12 by chemical vapor deposition.
  • the elecfrode layer 16 may be any suitable one or more noble metal (or oxide or alloy of same), such as platinum or iridium as one prefened elecfrode material because they are inert to oxidation which tends to occur in the subsequent high temperature processes of depositing the high dielectric constant fenoelectric materials.
  • the electrode layer 16 comprising platinum or iridium is also used as the electrode material because platinum and iridium are good electric conductors. The thickness of the electrode layer 16 would depend upon the end use of the semiconductor or capacitance device which is to contain the electrode layer 16.
  • the thickness of the elecfrode layer 16 ranges from about 500 Angstroms to about 5000 Angstroms, more preferably from about 1000 Angstroms to about 4000 Angstroms, most preferably from about 2000 Angstroms to about 3000 Angstroms, e.g., about 2000 Angstroms.
  • the electrode layer 16 is preferably disposed on the banier layer 14 by the RF magnetron sputtering method.
  • the mask layer 18 may be any suitable insulation or metallic material that is capable of being etched in accordance with the procedure described hereinafter such that all traces of the mask layer 18 are essentially removed from the surface platinum electrode layer 16 except that portion (identified as “18a,” “18b,” “18c,” and “18d” below) of the mask layer 18 remaining under the patterned resist 20.
  • the mask layer 18 may also be of any suitable thickness.
  • the mask layer 18 comprises silicon dioxide (SiO 2 ) and/or silicon nitride (Si 3 N 4 ) or any other suitable dielectric material. The thickness of the mask layer 18 would depend on constituency of the mask layer 18, as well as the constituency of the layer 15 or electrode layer 16.
  • a prefened thickness for the mask layer 18 ranges from about 1,000 Angsfroms to about 15,000 Angstroms, more preferably from about 3,000 Angsfroms to about 12,000 Angsfroms, most preferably from about 6,000 Angstroms to about 9,000 Angsfroms, e.g., about 7,000 Angstroms.
  • the ratio of the thickness of the mask layer 18 to the thickness of the layer 15, or the electrode layer 16, ranges from about 0.2 to about 5.0, preferably from about 0.5 to about 4.0, more preferably from about 1.0 to about 3.0.
  • the mask layer 18 comprises a compound selected from the group consisting of organic polymers, chemical vapor deposited (CVD) Si0 2 , doped CVD Si0 2 tefraethyorthosilicate (TEOS), CVD Si 3 N and mixtures thereof.
  • the organic polymer is a high temperature polymer capable of standing up to 400°C, such as amorphous carbon, polyamide, parylene and aromatic hydrocarbons.
  • a suitable organic polymer has been determined to be an organic polymer sold by Dow Chemical Co. of Midland, MI, under the registered trademark SiLK®.
  • the doped CVD Si0 2 is a CVD Si0 2 film having doping gases added to the CVD reactant gases, such as adding phosphorus dopant to form phosphosilicate glass (PSG), adding boron dopant to form borosilicate glass (BSG), or adding both phosphorus and boron dopants to form borophosphosilicate (BGSG).
  • the mask layer 18 is preferably disposed on the platinum elecfrode layer 16 by chemical vapor deposition. In another embodiment of the present invention, the mask layer 18 comprises
  • Ti and/or TiN preferably TiN.
  • a clean iridium surface is produced after removal of the mask layer 18 with no fence or veil formation.
  • the etch selectivity of iridium to the TiN is greater than about 8.0, preferably greater than about 10.0.
  • the spirit and scope of the present invention includes etching of a platinum electrode layer 16, or any other noble metal elecfrode layer 16, while supporting a mask layer 18 comprising TiN, with the etching of the platinum electrode layer 16 being conducted in a high density plasma of an etchant gas comprising oxygen, a halogen gas (e.g., Cl 2 ), and a noble gas (e.g., argon).
  • an etchant gas comprising oxygen, a halogen gas (e.g., Cl 2 ), and a noble gas (e.g., argon).
  • the thickness for the mask layer 18 for this embodiment of the invention ranges from about 500 Angstroms to about 9000 Angstroms, preferably from about 2000 Angsfroms to about 7000 Angstroms, more preferably about 3000 Angstroms.
  • the ratio of the thickness of the mask layer 18 to the thickness of the layer 15, or the electrode layer 16 ranges from about 0.2 to about 5.0, preferably from about 0.5 to about 4.0, more preferably from about 1.0 to about 3.0.
  • the mask layer 18 is preferably disposed on the electrode layer 16 by chemical vapor deposition.
  • the patterned resist 20 may be any suitable layer of material(s) that is capable of protecting any underlying material (e.g., the mask layer 18) from being etched during the etching process of the present invention.
  • Suitable materials for the patterned resist 20 include resist systems consisting of novolac resin and a photoactive dissolution inhibitor (all based on S ⁇ ss's discovery).
  • Other suitable materials for the resist 20 are listed in an article from the July 1996 edition of Solid State Technology entitled "Deep-UV Resists: Evolution and Status" by Hiroshi Ito.
  • the patterned resist 20 may have any suitable thickness; preferably, the thickness of the patterned resist 20 ranges from about 0.3 ⁇ m to about 1.40 ⁇ m, more preferably from about 0.5 m to about 1.2 ⁇ m, most preferably about 0.8 ⁇ m.
  • the patterned resist 20 is preferably disposed on the mask layer 18 by the spin coating method.
  • Fig. 2 is for protecting the corners (identified as “16g” below) of an etched elecfrode layer (generally identified as “16e” below) during the overetching process of the present invention.
  • Another purpose of the protective layer 22 is for providing good adhesion to the mask layer 18 and the elecfrode layer 16.
  • the protective layer 22 may comprise any suitable materials or chemicals, such as titanium and/or titanium nitride etc., and may be conveniently disposed on the surface of the electrode layer 16, such as by the RF magnetron sputtering method.
  • the thickness of the protective layer 22 may be any suitable thickness, preferably ranging from about 50 Angsfroms to about 1000 Angsfroms, more preferably ranging from about 100 Angsfroms to about 600 Angsfroms, most preferably from about 100 Angstroms to about 400 Angsfroms, e.g., about 300 Angsfroms.
  • the multilayered structure is initially placed in a suitable plasma processing apparatus to break through and remove or etch away from the surface of the electrode layer 16 the mask layer 18, except those mask layers 18a, 18b, 18c and 18d that are respectively below the resist members 20a, 20b, 20c and 20d, as best shown in Fig. 5, or as best shown in Fig. 6 if the embodiment of the invention depicted in Fig. 2 or Fig. 25 is being employed.
  • the plasma process apparatus of Fig. 3 comprises a plasma reactor, generally illustrated as 30 and including walls, generally illustrated as 31 for forming and housing a reactor chamber 32 wherein a plasma 33 of neutral (n) particles, positive (+) particles, and negative (-) particles are found.
  • Walls 31 include cylindrical wall 54 and cover 56.
  • Plasma processing gases are introduced via inlets 34 into reactor chamber 32.
  • Plasma etching gases are introduced into chamber 32 through inlets 44-44.
  • a water cooled cathode 36 is connected to an RF power supply 38 at 13.56 MHz.
  • An anode 39 is connected to the walls 31 which are grounded by line 40.
  • Helium gas is supplied through passageway 50 through cathode 36 to the space beneath wafer 10 which is supported peripherally by lip seal 52 so that the helium gas cools the wafer 10.
  • the wafer 10 is supported by a wafer support 46 that includes a plurality of clamps (not shown) which hold down the upper surface of wafer 10 at its periphery, as is well known to those skilled in the art.
  • a pair of helmholtz configured elecfromagnetic coils 42 and 43 provide north and south poles within the chamber 32 and are disposed at opposite ends of the lateral cylindrical wall 54 and the walls 31.
  • the elecfromagnetic coils 42 and 43 provide a fransverse magnetic field with the north and south poles at the left and right providing a horizontal magnetic field axis parallel to the surface of the wafer 10.
  • the transverse magnetic field is applied to slow the vertical velocity of the electrons which are accelerated radially by the magnetic field as they move towards the wafer 10. Accordingly, the quantity of electrons in the plasma 33 is increased by means of the fransverse magnetic field and the plasma 33 is enhanced as is well known to these skilled in the art.
  • the electromagnetic coils 42 and 43 which provide the magnetic field are independently controlled to produce a field intensity orientation which is uniform.
  • the field can be stepped angularly around the wafer 10 by rotating the energization of the elecfromagnetic coils 42 and 43, sequentially.
  • the fransverse magnetic field provided by the elecfromagnetic coils 42 and 43 is directed parallel to the surface of the wafer 10 being treated by the plasma 33, and the cathode 36 of the plasma reactor 30 increases ionization efficiently of the electrons in the plasma 33.
  • This provides the ability to decrease the potential drop across the sheath of the cathode 36 and to increase the ion cunent flux present on the surface of the wafer 10, thereby permitting higher rates of etching without requiring higher ion energies to achieve the result otherwise.
  • the prefened magnetic source employed to achieve magnetically enhanced reactive ion etcher (MERIE) used in practicing the present invention is a variable rotational field provided by the elecfromagnetic coils 42 and 43 ananged in a Helmholtz configuration.
  • the elecfromagnetic coils 42 and 43 are driven by 3 -phase AC cunents.
  • the magnetic field with Flux B is parallel to the wafer 10, and perpendicular to the elecfrical field as shown in Fig. 4. Refening to Fig.
  • the vector of the magnetic field H which produces flux B is rotating around the center axis of the elecfrical field by varying the phases of cunent flowing through the elecfromagnetic coils 42 and 43 at a typical rotational frequency of 0.01 to 1 Hz, particularly at 0.5 Hz.
  • the strength of the magnetic flux B typically varies from 0 Gauss to about 150 Gauss and is determined by the quantities of the cunents supplied to the elecfromagnetic coils 42 and 43. While Fig.
  • FIG. 3 illustrates one plasma processing apparatus that is suitable for removing the mask layer 18 (except mask layers 18a, 18b, 18c and 18d), it is to be understood that other plasma etchers may be employed, such as electron cyclotron resonance (ECR), helicon resonance or inductively coupled plasma (ICP), triode etchers, etc.
  • ECR electron cyclotron resonance
  • ICP inductively coupled plasma
  • triode etchers etc.
  • the plasma 33 may employ any suitable etchant gas to break through (i.e., to clean and etch away) the mask layer 18 except those mask layers 18a, 18b, 18c and 18d that are respectively below the resist members 20a, 20b, 20c and 20d, as best shown in Figs. 5 and 6.
  • suitable etchant gas(es) may be selected from the group consisting of fluorine-containing gases (e.g., CHF 3 , SF 6 , C 2 F 6 , NF 3 , etc.), bromine-containing gases (e.g., HBr, etc.), chlorine- containing gases (e.g., CHC1 3 , etc.), rare or noble gases (e.g., argon, etc.), and mixtures thereof.
  • fluorine-containing gases e.g., CHF 3 , SF 6 , C 2 F 6 , NF 3 , etc.
  • bromine-containing gases e.g., HBr, etc.
  • chlorine- containing gases e.g., CHC1 3 , etc.
  • rare or noble gases e.g., argon, etc.
  • the etchant does not include an oxidant, such as oxygen, since the purpose of this step is to remove the mask layer 18 (except those mask layers 18a, 18b, 18c and 18d which are respectively protected by resist members 20a, 20b, 20c and 20d) and not to remove the patterned resist 20.
  • the etchant gas comprises from about 20% by volume to about 40% by volume CHF 3 and from about 60% by volume to about 80% by volume argon.
  • the prefened reactor conditions for a suitable plasma processing apparatus (such as the plasma processing apparatus of Fig. 3) in removing the mask layer 18 (except mask layers 18a, 18b, 18c and 18d) are as follows:
  • the selectivity of mask layer 18 to patterned resist 20 is better than 3:1, depending on the materials employed for the mask layer 18 and the patterned resist 20.
  • the process parameters for removing the mask layer 18 in a suitable plasma process apparatus fall into ranges as listed in the following Table III and based on flow rates of the gases CHF 3 and Ar also listed in the following Table HI:
  • Ar 50 to 90 60 to 80% by vol. 60 to 80
  • suitable etchant gas(es) to break through (i.e., to clean and etch away) the Ti TiN-containing mask layer 18 except for those mask layers 18a, 18b, 18c and 18d that are respectively below the resist numbers 20a, 20b, 20c and 20d, as best shown Figs. 5 and 6, may be selected from the group consisting of a noble gas (e.g., argon), a halogen (e.g., Cl 2 ), and a gas selected from the group consisting of HBr, BC1 3 , and mixtures thereof.
  • a noble gas e.g., argon
  • a halogen e.g., Cl 2
  • the etchant gas comprises from about 10% by volume to about 30% by volume argon, from about 20% by volume to about 60% by volume chlorine, and from about 20% by volume to about 60% by volume HBr and/or BC1 3 .
  • the prefened reactor conditions for a suitable plasma processing apparatus such as the plasma processing apparatus of Fig. 3) in removing the mask layer 18 (except mask layer 18a, 18b, 18c and 18d) comprising Ti and/or TiN are as follows: Pressure 10-150 mTon
  • the selectivity of the Ti/TiN-containing mask layer 18 to patterned resist 20 is better than 3:1, depending on the materials employed for the patterned resist 20. More generally, the process parameters for removing the Ti/TiN-containing mask layer 18 in a suitable plasma process apparatus (such as the plasma processing apparatus of Fig. 3) fall into ranges as listed in the following Table IV and based on flow rates of the gases argon, chlorine and HBr and/or BC1 3 also listed in the following Table IV:
  • HBr and/or BC1 3 30 to 100 (20 to 60% by vol.) 50 to 70
  • the protective layer 22 has to be removed or etched after removal of the mask layer 18 in order to expose the platinum elecfrode layer 16.
  • the protective layer 22 may be etched and removed by any suitable manner and/or with any suitable plasma processing apparatus (such as with the plasma processing apparatus of Fig. 3) including the plasma 33 employing a suitable etchant gas to break through and etch away the protective layer 22 except those protective layers 22a, 22b, 22c and 22d (see Figs. 6 and 8) immediately below mask layers 18a, 18b, 18c and 18d, respectively.
  • suitable etchant gas(es) may be selected from the group consisting of Cl 2 , HBr, BC1 3 , noble gases (e.g., Ar), and mixtures thereof.
  • the etchant gas for breaking through and etching away the protective layer 22, except protective layers 22a, 22b, 22c and 22d comprises from about 20% by volume to about 60% by volume Cl 2 , from about 20% by volume to about 60% by volume HBr and/or BC1 3 , and from about 10% by volume to about 30% by volume of a noble gas which is preferably Ar.
  • Suitable reactor conditions for a suitable plasma processing apparatus such as the plasma processing apparatus of Fig.
  • protective layer 22 except protective layers 22a, 22b, 22c and 22d
  • protective layers 22a, 22b, 22c and 22d may be the same as those previously stated reactor conditions for the removal of the mask layer 18 (except mask layers 18a, 18b, 18c and 18d).
  • other plasma etchers may be employed to remove the protective layer 20, such as ECR, ICP, Helicon Resonance, etc.
  • the protective layers 22a, 22b, 22c and 22d are for protecting the corners (identified as "16g” below) of an etched elecfrode layer (generally identified as "16e” below) during the etching process of the present invention.
  • the protective layers 22a, 22b, 22c and 22d not only protect the corners of an etched platinum electrode layer during the etching process, but also assist in maintaining an existing profile and/or improves a profile (e.g., an etched platinum or iridium profile).
  • the protective layer 22 may be etched and removed by the high temperatures and etchant gases employed in the noble metal-etching process (e.g., platinum-etching process) of the present invention. More specifically and as will be further explained below, because the elecfrode layer 16 (e.g., platinum elecfrode layer 16) is preferably etched under the following process conditions in a high density plasma chamber containing a high density inductively coupled plasma:
  • Halogen Gas e.g., Cl 2 20% to 95% by vol.
  • Temperature (°C) of Wafer about 150 to about 500°C
  • the protective layer 22 may be etched and removed under the same foregoing conditions.
  • the same apparatus and process conditions may be employed to etch and remove selective parts of the protective layer 22, as well as to etch the electrode layer 16.
  • the protective layer 22 and the elecfrode layer 16 e.g., platinum elecfrode layer 16
  • Halogen Gas e.g., Cl 2
  • Cl 2 Halogen Gas
  • Temperature (°C) of Wafer about 150 to 500°C
  • the protective layer 22 (except protective layers 22a, 22b, 22c and 22d) may be etched by the high temperatures and etchant gases employed in the iridium-etching process of the present invention. More specifically and as will be further explained below, because the iridium electrode layer 16 is preferably etched under the following process conditions in a high density plasma chamber containing a high density inductively coupled plasma: Process Parameters
  • the protective layer 22 may be etched and removed under the same foregoing conditions.
  • the same apparatus and process conditions may be employed to etch and remove selective parts of the protective layer 22, as well as to etch the iridium electrode layer 16.
  • the protective layer 22 and the iridium electrode layer 16 may be removed and etched respectively in a high density plasma chamber containing a high density inductively coupled plasma under the following process conditions:
  • Halogen Gas e.g., Cl 2 ) 10% to 60% by vol.
  • the resist members 20a, 20b, 20c and 20d are to be removed.
  • the resist members 20a, 20b, 20c and 20d may be removed at any suitable time, preferably before the etching of the electrode layer 16 and before the heating of the semiconductor subsfrate 12 to a temperature greater than about 150° C. The same would hold true with respect to the embodiment of the invention illustrated in Figs.
  • the resist members 20a, 20b, 20c and 20d may be removed before the etching away of selective parts of the protective layer 22.
  • the resist members 20a, 20b, 20c and 20d may be removed after (or simultaneously during) the removal of selective parts of the protective layer 22 and before the heating of the semiconductor substrate 12 to a temperature greater than about 150° C for purposes of etching the elecfrode layer 16.
  • the resist members 20a, 20b, 20c and 20d would be removed while selective parts of the protective layer 22 are being etched away to expose the elecfrode layer 16 that is not superimposed by the protective layers 22a, 22b, 22c and 22d.
  • the resist members 20a, 20b, 20c and 20d may be removed in any suitable manner such as by using oxygen plasma ashing which is well known to those skilled in the art.
  • the resist members 20a, 20b, 20c and 20d may be respectively stripped from the mask layers 18a, 18b, 18c and 18d with any suitable plasma processing apparatus, such as the plasma processing apparatus shown in Fig. 3 and employing a plasma containing an etchant gas comprising oxygen.
  • the resist members 20a, 20b, 20c and 20d have been respectively removed from the mask layers 18a, 18b, 18c and 18d in an advanced strip passivation (ASP) chamber of a plasma processing apparatus sold under the frademark metal etch MxP Centura to Applied Materials, Inc.
  • ASP advanced strip passivation
  • the ASP chamber may employ microwave downstream O 2 /N 2 plasma with the following recipe: 120 seconds, 250°C, 1400W, 3000cc O 2 , 300cc N 2 and 2Ton.
  • the electrode layer 16 After the electrode layer 16 has been exposed as represented in Figs. 7 and 8, it is etched to develop a submicron pattern with a profile. As will be further stated below, before the elecfrode layer 16 is etched, the semiconductor subsfrate 12 supporting the elecfrode layer 16 is heated to a temperature greater than about 150° C, preferably greater than about 150° C up to about 500° C, more preferably from about 200° C to about 400° C, most preferably from about 250° C to about 350° C. The semiconductor substrate 12 is heated by the pedestal which supports the wafer 10 during the etching process (e.g., the noble metal etching process).
  • the etching process e.g., the noble metal etching process
  • the elecfrode layer 16 may be etched in any suitable plasma processing apparatus, such as in the reactive ion etching (RIE) plasma processing apparatus sold under the trademark AME8100 EtchTM, or under the frademark Precision Etch 5000TM, or under the frademark Precision Etch 8300TM, all trademarks owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299.
  • RIE reactive ion etching
  • Another suitable plasma processing apparatus for etching the elecfrode layer 16 is that plasma processing apparatus sold under the trademark Metal Etch DPS CenturaTM also owned by Applied Materials, Inc. It is also to be understood that other plasma etchers may be employed, such as ECR, ICP, Helicon Resonance, etc.
  • the dielectric member has an inside surface which functions as a deposit- receiving surface where noble metal by-products, such as platinum by-products, form during plasma etching.
  • the inside deposit-receiving surface of the dielectric member includes a surface finish having a peak-to valley roughness height with an average height value of more than about lOOOA; more preferably, an average height value of more than about 1800A, such as ranging from about 1800 A to about 4000A; most preferably, an average height value of more than about 4000A, such as ranging from about 4000A to about 8000A.
  • Roughness may be defined as relatively finely spaced surface irregularities. On surfaces produced by machining and abrading operations, the inegularities produced by the cutting action of tool edges and abrasive grains and by the feed of the machine tool are roughness. Roughness deviations are measured perpendicular to a nominal surface NS (see Fig. 36).
  • roughness height R H is measured from a peak P to a valley V.
  • the nominal surface NS is the surface that would result if the peaks P were leveled off to fill the valleys V.
  • the roughness height R H (sometimes designated in the art as R A ) values are average height values resulting from calculating the arithmetical average of all R H values on a deposit-receiving surface of a dielectric member obtained with a suitable instrument for measuring roughness of a surface.
  • a suitable instrument for measuring an average R H value on the deposit-receiving surface may be obtained commercially from WYKO Corporation, Arlington, AZ under model No.
  • PZ- 06-SC-SF which is a non-contact optical surface profiler that employs phase-shifting interferometry (PSI) modes for measuring smooth surfaces and vertical-scanning interferomefry (VSI) modes for measuring rough surfaces and steps.
  • PSI phase-shifting interferometry
  • VSI vertical-scanning interferomefry
  • Suitable procedures for calculating an average R H value on the deposit-receiving surface is described in a technical manual entitled WYKO Surface Profilers Technical Reference Manual, published by WYKO Corporation, and fully incorporated herein by reference thereto.
  • a prefened procedure for finishing the deposit-receiving surface to obtain desirable average roughness height values includes bead blasting with 36-grid alumina.
  • wafers 10, such as semiconductor substrates 12, are processed within a plasma processing chamber, preferably such as by plasma etching for patterning integrated circuit (TC) metal interconnect devices.
  • plasma etching is one of the prefened plasma processes for the embodiment of the invention employing a dielectric member (or window) including an inside surface (i.e., a deposit-receiving surface) having a surface finish having a peak-to-valley roughness height with an average height value of more than about 1000 A
  • plasma etching is one of the prefened plasma processes for the embodiment of the invention employing a dielectric member (or window) including an inside surface (i.e., a deposit-receiving surface) having a surface finish having a peak-to-valley roughness height with an average height value of more than about 1000 A
  • the spirit and scope of this embodiment of the invention includes other forms of processing subsfrates, such as chemical vapor deposition and physical vapor deposition.
  • processing power e.g., RF power, magnetron power, microwave power, etc.
  • a dielectric member which includes a dielectric window of a nonconductive material such as a ceramic dome, etc., and becomes coupled to a plasma of the proceeding gas.
  • metal etching of metals e.g., platinum, copper, aluminum, titanium, ruthenium, iridium, etc.
  • a deposit of materials occurs on an inside surface of the dielecfric member, as disclosed in copending patent application Serial No. 08/920,283, filed August 26, 1997, and fully incorporated herein by reference thereto.
  • the deposit is located between the plasma and the power source. If the plasma process for this embodiment of the present invention is plasma etching, the deposit results from etching a metal layer on the subsfrate; and, thus, the deposit could be electrically conductive, and includes, by way of example only, metal, metal oxide(s), metal nitride(s), etc.
  • the metal conesponds to the metal which is being etched within the process chamber and includes, also by way of example only, platinum, copper, aluminum, titanium, ruthenium, iridium, etc.
  • the deposit When the deposit is electrically conductive and is between the plasma and the power source, a decay in processing power transmission occurs and continues until the electrically conductive deposit reaches a certain thickness (i.e., skin depth), such as from about 0.001 in. to about 0.5 in., whereafter the processing power transmission becomes very low or even nil.
  • the deposit therefore, behaves as a Faraday shield to reduce the efficiency of processing power transmission into the plasma of the processing gas within the process chamber.
  • the processing e.g., the etch rate
  • the inside deposit-receiving surface of the dielectric member includes, as was more specifically discussed above, a surface finish having a peak-to-valley roughness height with an average height value of more than about 1000 A.
  • the etchant gas broadly comprises a halogen containing gas, such as a halogen gas (e.g., fluorine, chlorine, bromine, iodine, and astatine) and a noble gas such as helium, neon, argon, krypton, xenon, and radon.
  • a halogen gas e.g., fluorine, chlorine, bromine, iodine, and astatine
  • a noble gas such as helium, neon, argon, krypton, xenon, and radon.
  • the etchant gas comprises or consists of or consists essentially of a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon.
  • the noble gas is preferably argon.
  • the etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 20% by volume to about 95% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80%> by volume of the noble gas (i.e., argon); more preferably from about 40% by volume to about 80%> by volume of the halogen gas (i.e., chlorine) and from about 20% by volume to about 60% by volume of the noble gas (i.e., argon); most preferably from about 55% by volume to about 65%> by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon).
  • the etchant gas may also broadly comprise oxygen, a halogen containing gas, such as a halogen gas (e.g., fluorine, chlorine, bromine, iodine, and astatine), and a noble gas such as helium, neon, argon, krypton, xenon, and radon.
  • a halogen gas e.g., fluorine, chlorine, bromine, iodine, and astatine
  • a noble gas such as helium, neon, argon, krypton, xenon, and radon.
  • the etchant gas comprises, or consists of or consists essentially of, a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon and argon.
  • the noble gas is preferably argon.
  • the etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 5% by volume to about 40% by volume oxygen, from about 10% by volume to about 60% by volume of the halogen gas (i.e., chlorine), and from about 30% by volume to about 80%) by volume of the noble gas (i.e., argon); more preferably from about 10% by volume to about 30% by volume oxygen, from about 20% by volume to about 50% by volume of the halogen gas (i.e., chlorine), and from about 40%> by volume to about 70% of the noble gas (i.e., argon); most preferably from about 10% by volume to about 20% by volume oxygen, from about 20% by volume to about 30% by volume halogen gas (i.e., chlorine), and from about 50% by volume to about 70% by volume of noble gas (i.e., argon).
  • the etchant gas comprises, preferably consists of or consists essentially of, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, BC1 3 and mixtures thereof.
  • the halogen i.e., chlorine
  • the noble gas i.e., argon
  • the etchant gas more specifically comprises, or consists of or consists essentially of, from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 4% by volume to about 25% by volume of HBr and/or BC1 3 ; preferably from about 40% by volume to about 70% by volume of the halogen gas (i.e., chlorine) and from about 25% by volume to about 55% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or BC1 ; and more preferably from about 50%> by volume to about 60% by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or BC1 3 .
  • HBr and/or BC1 3 are for removal of residue (e.g. platinum or iridium residue) during etching of the electrode layer 16 (e.g., the platinum or iridium elecfrode layer).
  • residue e.g. platinum or iridium residue
  • the electrode layer 16 e.g., the platinum or iridium elecfrode layer.
  • Plasmas containing argon are known to have a high energetic ion concentration and are often used for physical sputtering. The sputtering effect due to the ions is a function of the accelerating potential which exist between the plasma and the sample.
  • the etchant gas comprises, preferably consists of or consists essentially of, oxygen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, HCl and mixtures thereof.
  • the halogen i.e., chlorine
  • the noble gas i.e., argon
  • the etchant gas more specifically comprises, or consists of or consists essentially of, from about 5%> by volume to about 20% by volume oxygen, from about 10% by volume to about 60%> by volume of the halogen gas (i.e., chlorine) and from about 30% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or HCl; preferably from about 5% by volume to about 15% by volume oxygen, from about 20% by volume to about 50% by volume of the halogen gas (i.e., chlorine) and from about 40% by volume to about 70% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or HCl; and more preferably from about 5% by volume to about 10% by volume oxygen, from about 20% by volume to about 35% by volume of the halogen gas (i.e., chlorine) and from about 40% by volume to about 60% by volume of the noble gas (
  • the etchant gas flow rate ranges from about 50 seem to about 500 seem.
  • the etchant gas broadly comprises nifrogen, a halogen (e.g., fluorine, chlorine, bromine, iodine, and astatine) and a noble gas such as helium, neon, argon, krypton, xenon, and radon.
  • a halogen e.g., fluorine, chlorine, bromine, iodine, and astatine
  • a noble gas such as helium, neon, argon, krypton, xenon, and radon.
  • the etchant gas comprises or consists of or consists essentially of nitrogen, a halogen (preferably chlorine) and a noble gas selected from group consisting of helium, neon, and argon.
  • the noble gas is preferably argon.
  • the etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 0.1% by volume to about 60% by volume nitrogen, from about 40% by volume to about 90%> by volume of the halogen gas (i.e., chlorine), and from about 0.1% by volume to about 40% by volume of the noble gas (i.e., argon); more preferably from about 5% by volume to about 40% by volume nifrogen, from about 50% by volume to about 80%> by volume of the halogen gas (i.e., chlorine), and from about 5% by volume to about 30% by volume of the noble gas (i.e., argon); most preferably from about 10% by volume to about 30% by volume nitrogen, from about 60% by volume to about 70% by volume of the halogen gas (i.e., chlorine), and from about 10% by volume to about 20%) by volume of the noble gas (i.e., argon).
  • the plasma of the etchant gas may be a high density plasma or a low-density
  • the etchant gas comprises, preferably consists of or consists essentially of, nitrogen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, BC1 3 , SiCL, and mixtures thereof.
  • the halogen i.e., chlorine
  • the noble gas i.e., argon
  • the etchant gas more specifically comprises, or consists of or consists essentially of, from about 0.1 % by volume to about 60% by volume nifrogen, from about 40% by volume to about 90% by volume of the halogen gas (i.e., chlorine), and from about 0.1% by volume to about 40%> by volume of the noble gas (i.e., argon), and from about 1%) by volume to about 30% by volume of HBr and/or BC1 3 and/or SiCl 4 ; preferably from about 5% by volume to about 40% by volume nifrogen, from about 50% by volume to about 80%) by volume of the halogen gas (i.e., chlorine), and from about 5% by volume to about 30%) by volume of the noble gas (i.e., argon), and from about 5% by volume to about 20% by volume of HBr and/or BC1 3 and/or SiCl 4 ; and more preferably from about 10% by volume to about 30% by volume nitrogen, from about 60% by volume to about 70% by volume of the
  • the etchant gas comprises or consists of or consists essentially of nitrogen and a halogen (preferably chlorine).
  • the etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 10% by volume to about 90%) by volume nitrogen and from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine); more preferably from about 20% by volume to about 60% by volume nifrogen and from about 40%> by volume to about 80% by volume of the halogen gas (i.e., chlorine); most preferably from about 30%> by volume to about 40% by volume nitrogen, and from about 60% by volume to about 70% by volume of the halogen gas (i.e., chlorine).
  • the plasma of the etchant gas may be a high density plasma or a low-density plasma having a density of less than about 10 1 Vcm 3 , preferably less than about 10 9 /cm 3 .
  • the reactor conditions for a suitable plasma processing apparatus such as the plasma processing apparatus of Fig. 3, in etching the elecfrode layer 16 (e.g., platinum elecfrode layer 16) are as follows: Pressure 0.1-300 mTon
  • the selectivity of elecfrode layer 16 to mask 18 is better than 2:1, depending on the materials employed for the mask layer 18.
  • the process parameters for etching the elecfrode 16 in a suitable plasma processing apparatus fall into ranges as listed in the following Table V and based on the flow rate of etchant gas as also listed in Table V below: TABLE V
  • RF Power 50 to 3000 500 to 2000 700 to 1200
  • a prefened etchant gas for etching the elecfrode layer 16 is a mixture of chlorine and argon, or a mixture of chlorine, argon and HBr and/or BC1 3 .
  • Another prefened etchant gas for etching the elecfrode layer 16 is a mixture of oxygen, chlorine and argon, or a mixture of oxygen, chlorine, argon and HBr and/or HCl.
  • the etchant gas is a mixture of chlorine and argon (i.e., from about 20% > by volume to about 95% by volume chlorine and from about 5% by volume to about 80% by volume argon), or a mixture of chlorine, argon and HBr and/or BC1 3 (i.e., from about 10% by volume to about 90%> by volume chlorine and from about 5% by volume to about 80% by volume argon and from about 4% by volume to about 25% by volume HBr and/or BC1 3 ), and if the semiconductor subsfrate 12 is heated to a temperature greater than about 150°C, preferably to a temperature ranging from about 150°C to about 500°C, the plasma processing apparatus for etching the elecfrode layer 16 (e.g., the platinum elecfrode layer 16 or the iridium elecfrode layer 16) etches the elecfrode layer 16 in a high density plasma of the etchant gas at a high etch rate (e.g., an
  • the produced elecfrodes (e.g., produced platinum electrodes) are separated by a distance or space having a dimension equal to or less than about 0.35 ⁇ m, preferably equal to or less than about 0.3 ⁇ m.
  • Each of the electrodes include a dimension having a value equal to or less than about 1.0 ⁇ m, preferably equal to or less than about 0.6 ⁇ m, more preferably equal to or less than about 0.35 ⁇ m, most preferably equal to or less than about 0.3 ⁇ m. More preferably, each of the elecfrodes (e.g., produced platinum electrodes) have a width equal to or less than about 1.0 ⁇ m, preferably equal to or less than about 0.6 ⁇ m, and a height equal to or less than about 0.6 ⁇ m.
  • the etched electrode layer 16e i.e., etched electrode layers 16a, 16b, 16c and 16d
  • the method of the present invention produces etched elecfrode layers 16a, 16b, 16c and 16d which are essentially veil-less.
  • the produced etched electrode layers 16a, 16b, 16c and 16d are essentially veil-less and have no “fences” or “rabbit ears,” they are ideally suited for receiving a dielecfric BST or PZT or SBT layer and functioning as elecfrodes in a semiconductor device (i.e., a capacitance structure).
  • the high density plasma of the present invention may be defined as a plasma of the etchant gas of the present invention having an ion density greater than about 10 9 /cm 3 , preferably greater than about 10 ⁇ /cm 3 .
  • the source of the high density plasma may be any suitable high density source, such as electron cyclotron resonance (ECR), helicon resonance or inductively coupled plasma (ICP)-type sources. All three are in use on production equipment today. The main difference is that ECR and helicon sources employ an external magnetic field to shape and contain the plasma, while ICP sources do not.
  • the high density plasma for the present invention is more preferably produced or provided by inductively coupling a plasma in a decoupled plasma source etch chamber, such as that sold under the frademark DPSTM owned by Applied Materials, Inc. which decouples or separates the ion flux to the wafer 10 and the ion acceleration energy.
  • a decoupled plasma source etch chamber such as that sold under the frademark DPSTM owned by Applied Materials, Inc. which decouples or separates the ion flux to the wafer 10 and the ion acceleration energy.
  • the design of the etch chamber provides fully independent control of ion density of an enlarged process window. This is accomplished by producing plasma via an inductive source. While a cathode within the etch chamber is still biased with RF electric fields to determine the ion acceleration energy, a second RF source (i.e., an inductive source) determines the ion flux.
  • This second RF source is not capacitive (i.e., it does not use electric fields like the cathode) since a large sheath voltage would be produced, interfering with the cathode bias and effectively coupling the ion energy and ion flux.
  • the inductive plasma source couples RF power through a dielecfric window rather than an elecfrode.
  • the power is coupled via RF magnetic fields (not electric fields) from RF current in a coil. These RF magnetic fields penetrate into the plasma and induce RF electric fields (therefore the term "inductive source") which ionize and sustain the plasma.
  • the induced elecfric fields do not produce large sheath voltages like a capacitive elecfrode and therefore the inductive source predominantly influences ion flux.
  • the cathode bias power plays little part in determining ion flux since most of the RF power (typically an order of magnitude less than the source power) is used in accelerating ions.
  • the combination of an inductive plasma source and a capacitive wafer bias allows independent control of the ion flux and ion energy reaching the wafer 10 in the etch chamber, such as the DPSTM brand etch chamber.
  • DPSTM brand etch chambers for producing the high density plasma of the present invention for etching the elecfrode layer 16 to produce the etched electrode layers 16a, 16b, 16c and 16d may be any of the DPSTM brand etch chambers of the inductively coupled plasma reactor disclosed in U.S. Patent No. 5,753,044, entitled "RF PLASMA REACTOR WITH HYBRID CONDUCTOR AND MULTI-RADIUS DOME CEILING" and assigned to the present assignee and fully incorporated herein by reference thereto as if repeated verbatim immediately hereinafter.
  • an inductively coupled RF plasma reactor generally illustrated as 90, having a reactor chamber, generally illustrated as 92, wherein a high density plasma 94 of neutral (n) particles, positive (+) particles, and negative (-) particles are found.
  • the reactor chamber 92 has a grounded conductive cylindrical sidewall 60 and a dielecfric ceiling 62 having an inside concave surface 62a which would receive deposits of by- products from plasma processing of wafers 10.
  • the inductively coupled RF plasma reactor 90 further comprises a wafer pedestal 64 for supporting the (semiconductor) wafer 10 in the center of the chamber 92, a cylindrical inductor coil 68 surrounding an upper portion of the chamber 92 beginning near the plane of the top of the wafer 10 or wafer pedestal 64 and extending upwardly therefrom toward the top of the chamber 92, an etching gas source 72 and gas inlet 74 for furnishing an etching gas into the interior of the chamber 92, and a pump 76 for controlling the pressure in the chamber 92.
  • the coil inductor 68 is energized by a plasma source power supply or RF generator 78 through a conventional active RF match network 80, the top winding of the coil inductor 68 being "hot" and the bottom winding being grounded.
  • the wafer pedestal 64 includes an interior conductive portion 82 connected to the bias RF power supply or generator 84 and an exterior grounded conductor 86 (insulated from the interior conductive portion 82).
  • the plasma source power applied to the coil inductor 68 by the RF generator 78 and the DC bias RF power applied to the wafer pedestal 64 by generator 84 are separately controlled RF supplies. Separating the bias and source power supplies facilitates independent control of ion density and ion energy, in accordance with well-known techniques.
  • the coil inductor 68 is adjacent to the chamber 92 and is connected to the RF source power supply or the RF generator 78.
  • the coil inductor 68 provides the RF power which ignites and sustains the high ion density of the high density plasma 94.
  • the geometry of the coil inductor 68 can in large part determine spatial distribution of the plasma ion density of the high density plasma 94 within the reactor chamber 92.
  • Uniformity of the plasma density spatial distribution of the high density plasma 94 across the wafer 10 is improved (relative to conical or hemispherical ceilings) by shaping the ceiling 62 in a multi-radius dome and individually determining or adjusting each one of the multiple radii of the ceiling 62.
  • the multiple-radius dome shape in the particular embodiment of Fig. 17 somewhat flattens the curvature of the ceiling 62 around the center portion of the ceiling 62, the peripheral portion of the ceiling 62 having a steeper curvature.
  • the coil inductor 68 may be coupled to the RF power source 78, 80 in a minor coil configuration that is known to those skilled in the art.
  • the RF source 78, 80 is connected to the center winding of the coil inductor 68 while the top and bottom ends of the coil inductor 68 are both grounded.
  • the minor coil configuration has the advantage of reducing the maximum potential on the coil inductor 68.
  • a semiconductor device is produced with electrodes (e.g., noble metal electrodes such as platinum elecfrodes or iridium) having a profile with an angular value which is equal to or greater than about 80 degrees (e.g., equal to greater than about 80 degrees for iridium), preferably equal to or greater than about 85 degrees (e.g., equal to or greater than 85 degrees for platinum), more preferably equal to or greater than about 87 degrees, most preferably equal to or greater than about 88.5 degrees.
  • electrodes e.g., noble metal electrodes such as platinum elecfrodes or iridium
  • the electrodes are essentially veil- less; that is, they have no "fences” or "rabbit ears.”
  • the elecfrodes are preferably separated by a distance or space having a dimension equal to or less than about 0.35 ⁇ m, preferably equal to or less than about 0.3 ⁇ m.
  • Each of the electrodes include a dimension having a value equal to or less than about 1.0 ⁇ m, preferably equal to or less than about 0.6 ⁇ m, more preferably equal to or less than about 0.35 ⁇ m, most preferably equal to or less than about 0.3 ⁇ m.
  • each of the elecfrodes have a width equal to or less than about 0.35 ⁇ m, more preferably equal to or less than about 0.3 ⁇ m, a length equal to or less than about 1.0 ⁇ m, more preferably equal to or less than about 0.6 ⁇ m, and a height equal to or less than about 0.6 ⁇ m.
  • the prefened reactor conditions for a suitable inductively coupled RF plasma reactor such as the inductively coupled RF plasma reactor 90 in Figs. 17 and 18, in etching the elecfrode layer 16 (e.g., platinum electrode layer 16) are as follows: Pressure 0.1 to 300 mTon
  • the process parameters for etching the elecfrode layer 16 e.g., platinum elecfrode layer 16
  • a suitable inductively coupled plasma reactor such as the inductively coupled plasma reactor 90 in Figs. 17 and 18, fall into ranges as listed on the basis of flow rates of the gases, including the halogen gas(es) (i.e., Cl 2 ) and the noble gas(es) (i.e., argon), as listed in Table VI below.
  • the process parameters for etching the electrode layer 16 e.g. an iridium elecfrode layer 16
  • a suitable inductively coupled plasma reactor such as the inductively coupled plasma reactor 90 in Figs. 17 and 18, fall into ranges as listed on the basis of flow rates of the gases, including oxygen, the halogen gas(es) (i.e., Cl 2 ), and the noble gas(es) (i.e., argon), as listed in Table Nil below.
  • the etchant gases are a mixture of the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or BC1 3
  • the process parameters for etching the elecfrode layer 16 e.g., platinum elecfrode layer 16
  • a suitable inductively coupled plasma reactor such as the inductively coupled plasma reactor 90 in Figs.
  • Cla 30 to 400 50 to 250 60 to 150
  • Temperature of Wafer about 150 to about 500 200 to 400 250 to 350
  • the etchant gases are a mixture of oxygen, the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or BC1 3 , the process parameters for etching elecfrode layer 16 (e.g., iridium electrode layer 16) in a suitable inductively coupled plasma reactor, such as the inductively coupled plasma reactor 90 in Figs.
  • the foregoing process conditions are preferably based on flow rates of etchant gas(es) having a flow rate value ranging from about 5 to about 500 seem.
  • the process parameters of the Tables may vary in accordance with the size of the wafer 10.
  • the etchant gas comprises or consists of or consists essentially of a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon.
  • the etchant gas comprises, or consists of or consists essentially of, oxygen, a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon.
  • the noble gas is preferably argon.
  • the etchant gas more specifically comprises or consists of or consists essentially of from about 20% by volume to about 95% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon); preferably from about 40% by volume to about 80% by volume of the halogen gas (i.e., chlorine) and from about 20%> by volume to about 60% by volume of the noble gas (i.e., argon); more preferably from about 55% by volume to about 65% by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% > by volume of the noble gas (i.e., argon).
  • the halogen gas i.e., chlorine
  • the noble gas i.e., argon
  • the etchant gas more specifically comprises, or consists of or consists essentially of, from about 5% by volume to about 40% by volume oxygen, from about 10% by volume to about 60%) by volume of the halogen gas (i.e., chlorine) and from about 30% by volume to about 80%) by volume of the noble gas (i.e., argon); preferably from about 10%) by volume to about 30% by volume oxygen, from about 20%> by volume to about 50%> by volume of the halogen gas (i.e., chlorine) and from about 40% by volume to about 70% by volume of the noble gas (i.e., argon); more preferably from about 10%> by volume to about 20% by volume oxygen, from about 20% by volume to about 30% by volume of the halogen gas (i.e., chlorine) and from about 50% by volume to about 70% by volume of the noble gas (i.e., argon).
  • the halogen gas i.e., chlorine
  • the noble gas i.e., argon
  • the etchant gas comprises, preferably consists of or consists essentially of, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group that consists of HBr, BC1 3 and mixtures thereof.
  • the etchant gas comprises, preferably consists of or consists essentially of, oxygen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group that consists of HBr, BC1 3 and mixtures thereof.
  • the etchant gas more specifically comprises, or consists of or consists essentially of from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 4% by volume to about 25%> by volume of HBr and/or BC1 3 ; preferably from about 40% by volume to about 70% by volume of the halogen gas (i.e., chlorine) and from about 25%> by volume to about 55% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20%> by volume of HBr and/or BC1 3 ; and more preferably from about 50% by volume to about 60% by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or BC1 3 .
  • the etchant gas more specifically comprises, or consists of or consists essentially of, from about 5% by volume to about 20%) by volume oxygen, from about 10%> by volume to about 60%> by volume of the halogen gas (i.e., chlorine) and from about 30% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or HCl; preferably from about 5% by volume to about 15% by volume oxygen, from about 20%) by volume to about 50% by volume of the halogen gas (i.e., chlorine), from about 40% by volume to about 70% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or HCl; and more preferably from about 5% by volume to about 10% by volume oxygen, from about 20%> by volume to about 35%> by volume of the halogen gas (i.e., chlorine) and from about 40%) by
  • the process parameters for etching the iridium electrode layer 16 in a suitable inductively coupled plasma reactor fall into ranges as listed on the basis of flow rates of the gases, including oxygen, the halogen gas(es), (i.e., Cl 2 ), and the noble gas(es) (i.e., argon), as hsted in Table X below.
  • Temperature of Wafer about 150 to about 500 200 to 400 250 to 350
  • the etchant gases are a mixture of oxygen, the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or HCl
  • the process parameters for etching iridium electrode layer 16 supporting a Ti/TiN mask layer 18 in a suitable inductively coupled plasma reactor fall into the ranges as listed on the basis of rates of the gases, including oxygen, the halogen gas(es) (i.e., Cl 2 ), the noble gas(ses) (i.e., Ar), and HBr and/or HCl, as Hsted in Table XI below:
  • the process parameters for etching in a low density (or high density) plasma the elecfrode layer 16 (e.g., platinum electrode layer 16) in a suitable inductively coupled plasma reactor fall into ranges as listed on the basis of flow rates of the gases, including nitrogen (N 2 ), the halogen gas(es) (i.e., Cl 2 ), and the noble gas(es) (i.e., argon), as hsted in Table XII below.
  • C-2 30 to 400 50 to 300 100 to 200
  • Temperature of Wafer about 150 to about 500 200 to 400 250 to 350
  • RIE reactive ion etch
  • Cl 2 30 to 400 50 to 300 100 to 200
  • Temperature of Wafer about 150 to 200 to 400 250 to 350 about 500
  • RIE reactive ion etch
  • Cl 2 30 to 600 100 to 400 150 to 200
  • the etchant gases are a mixture of nitrogen (N 2 ), the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or BC1 and/or SiCl 4
  • the process parameters for etching in a low density (or high density) plasma the electrode layer 16 (e.g., platinum electrode layer 16) in a suitable inductively coupled plasma reactor fall into the ranges as listed on the basis of flow rates of the gases, including nitrogen (N 2 ), the halogen gas(es) (i.e., Cl 2 ), the noble gas(es) (i.e., Ar), and HBr and/or BC1 3 and/or SiCl 4 , as listed in Table XV below:
  • Cl 2 30 to 400 50 to 300 100 to 200
  • RIE reactive ion etch
  • Cl 2 30 to 400 50 to 300 100 to 200
  • the foregoing process conditions are preferably based on flow rates of etchant gas(es) having a flow rate value ranging from about 5 to about 500 seem.
  • the etchant gas comprises or consists of or consists essentially of nitrogen, a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon.
  • the noble gas is preferably argon.
  • the etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 0.1 %> by volume to about 60%> by volume nitrogen, from about 40% by volume to about 90% by volume of the halogen gas (i.e., chlorine), and from about 0.1% by volume to about 40% by volume of the noble gas (i.e., argon); more preferably from about 5% by volume to about 40% by volume nitrogen, from about 50% by volume to about 80%> by volume of the halogen gas (i.e., chlorine), and from about 5% by volume to about 30% by volume of the noble gas (i.e., argon); most preferably from about 10% by volume to about 30%> by volume nifrogen, from about 60% by volume to about 70% by volume of the halogen gas (i.e., chlorine), and from about 10%) by volume to about 20% by volume of the noble gas (i.e., argon).
  • the halogen gas i.e., chlorine
  • the noble gas i.e.,
  • the etchant gas comprises or consists of or consists essentially of a nitrogen and halogen (preferably chlorine).
  • the etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 10% by volume to about 90%> by volume nifrogen and from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine); more preferably from about 20%> by volume to about 60% by volume nitrogen and from about 40% by volume to about 80% by volume of the halogen gas (i.e., chlorine); most preferably from about 30%> by volume to about 40% by volume nitrogen and from about 60% by volume to about 70%) by volume of the halogen gas (i.e., chlorine).
  • the etchant gas comprises, preferably consists of or consists essentially of, nifrogen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, BC1 3 , SiCL, and mixtures thereof.
  • the halogen i.e., chlorine
  • the noble gas i.e., argon
  • the etchant gas more specifically comprises, or consists of or consists essentially of, from about 0.1% by volume to about 60%> by volume nitrogen, from about 40% by volume to about 90% by volume of the halogen gas (i.e., chlorine), and from about 0.1% by volume to about 40% by volume of the noble gas (i.e., argon), and from about 1% by volume to about 30% by volume of HBr and/or BC1 3 and/or SiCL; preferably from about 5%> by volume to about 40% by volume nitrogen, from about 50% by volume to about 80% by volume of the halogen gas (i.e., chlorine), and from about 5% by volume to about 30% by volume of the noble gas (i.e., argon), and from about 5% by volume to about 20% by volume of HBr and/or BC1 3 and/or SiCl 4 ; and more preferably from about 10% by volume to about 30% by volume nitrogen, from about 60%> by volume to about 70% by volume of the halogen gas (i.e., chlorine), and from
  • noble metal etch by-products may become less conductive electrically, and the stability of RF power transmission through the dielectric window becomes more stable, by operating the platinum etch process in a high Cl 2 /Ar ratio and a high pressure regime.
  • the Cl 2 /Ar ratio may be any suitable elevated or high gas volume ratio, preferably a Cl 2 /Ar volume ratio of greater than 2(>2): 1 , more preferably greater than 4(>4): 1.
  • the high pressure may be any suitable elevated or high pressure, preferably greater than 10 mTon (>10 mTon), more preferably greater than 24 mTon (>24).
  • the etchant gases are a mixture of the halogen gas(es) (i.e., chlorine) and the noble gas(es) (i.e., argon)
  • the process parameters for etching the electrode layer 16 e.g., platinum electrode layer 16
  • a suitable inductively coupled plasma reactor for reducing the electrical conductivity of layer 16 by-products fall into the ranges as listed on the basis of flow rates of the gases, including the halogen gas(es) (i.e., Cl 2 ) and the noble gas(es) (i.e., Ar), as hsted in Table XVII below:
  • Halogen e.g., Cl 2
  • Noble gas e.g., Ar
  • Ar Noble gas
  • Temperature of Wafer about 150 to about 200 to 400 250 to 350 (°C) 500
  • the foregoing process conditions stated in Table XVII above may be based on the following etchant gas constituency for reducing the electrical conductivity of noble metal by-products (e.g., platinum etch by-products): preferably from about 50%> to about 96% by volume of the halogen gas(es) (i.e., chlorine) and from about 4% to about 50% by volume of the noble gas(es) (i.e., argon); more preferably from about 60% to about 90% by volume of the halogen gas(es) (i.e., chlorine) and from about 10% to about 40%> by volume of the noble gas(es) (i.e., argon); most preferably from about 70% to about 85% by volume of the halogen gas(es) (i.e., chlorine) and from about 15% to about 30% by volume of the noble gas(es).
  • noble metal by-products e.g., platinum etch by-products
  • the protective layers 22a, 22b, 22c and 22d protect the corners 16g of the etched elecfrode layers 16a, 16b, 16c and 16d during the etching process.
  • some of the mask layers 18a, 18b, 18c and 18d would be etched during the etching process, leaving residual mask layers 18r on top of etched electrode layers 16a, 16b, 16c and 16d, or on top of the protective layers 22a, 22b, 22c and 22d.
  • the protective layers 22a, 22b, 22c and 22d respectively, insure that the corners 16g of the etched electrode layers 16a, 16b, 16c and 16d are protected during etching, especially in the event that the etching process removes essentially all of the mask layers 18a, 18b, 18c and 18d. Maintaining the corners 16g of the etched elecfrode layers 16a, 16b, 16c and 16d protects the quality of the profile formed during etching of the electrode layer 16 to produce the etched electrode layers 16a, 16b, 16c and 16d.
  • the residual mask layers 18r (if not completely removed during the etching process) typically remain on top of the veil-less etched electrode layers 16a, 16b, 16c and 16d, or on top of the protective layers 22a, 22b, 22c and 22d which are respectively supported by the essentially veil-less etched electrode layers 16a, 16b, 16c and 16d, all as best shown in Figs. 11 and 12.
  • the residual mask layers 18r are to be removed by any suitable means and/or in any suitable manner, such as by CHF 3 /Ar plasma. Likewise for the embodiment of the invention depicted in Fig.
  • the protective layers 22a, 22b, 22c and 22d are to be removed after removal of the residual mask layers 18r from the protective layers 22a, 22b, 22c and 22d.
  • the protective layers 22a, 22b, 22c and 22d may be removed by any suitable means and/or in any suitable manner.
  • the protective layers 22a, 22b, 22c and 22d comprise TiN removal is by Ar/Cl 2 plasma in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following apparatus and process conditions as listed in Table XVIII below. TABLE XV ⁇ i
  • the veil-less etched elecfrode layered structure of Fig. 13 or Fig. 14 remains. It should be noted, as best shown in Figs. 15 and 16, respectively, that the barrier layer 14 could be etched simultaneously during or after removal of the residual mask layers 18r (see Fig. 15), or etched simultaneously during or after removal of the residual mask layers 18r and the protective layers 22a, 22b, 22c and 22d (see Fig. 16). It is to be understood that the patterned resist 20 (i.e., resist members 20a,
  • the patterned resist 20 i.e., resist numbers 20a, 20b, 20c and 20d
  • the mask layers 18a, 18b, 18c and 18d for the embodiment of the invention depicted in Fig. 2 may be removed at any suitable time, preferably before the etching of the electrode layer 16.
  • the protective layers 22a, 22b, 22c and 22d and/or mask layers 18a, 18b, 18c and 18d for the embodiment of the invention depicted in Fig. 2 may also be removed at any suitable time, such as during the etching process or after the etching process.
  • the wafer 10 of Fig. 2 is provided with the semiconductor substrate 12, the banier layer 14 (e.g., TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, etc.) and the protective layer 22 comprising a compound selected from the group consisting of TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, and mixtures thereof, and the mask layer 18 selected from the group consisting of CVD SiO 2 , TEOS, Si 3 N 4 , BSG, PSG, BPSG, a low dielecfric constant material with a low dielectric constant of less than about 3.0, and mixtures thereof.
  • the banier layer 14 e.g., TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, etc.
  • the protective layer 22 comprising a compound selected from the group consisting of TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, and mixtures thereof
  • the elecfrode layer 16 is a noble metal such as Pt, Ir, Pd, and Ru, or any oxide or alloy of a noble metal.
  • This multilayered structure is initially placed in a suitable plasma processing apparatus to selectively break through and etch away from the surface of the elecfrode layer 16, the mask layer 18 except those mask layers 18a, 18b, 18c and 18d that are respectively below the resist members 20a, 20b, 20c and 20d as best shown in Fig. 6.
  • the plasma for any suitable plasma processing apparatus may employ any suitable etchant gas.
  • the resist members 20a, 20b, 20c and 20d are removed in accordance with any of the previously mentioned procedures such that masking and etching sequence of Fig. 26 may be conducted.
  • the resist 20 i.e., resist members 20a, 20b, 20c and 20d
  • the protective layer 22 and the elecfrode layer 16 are etched.
  • etching continues into the barrier layer 14. Stated alternatively, etching stops in the barrier layer 14.
  • the mask layers 18a, 18b, 18c and 18d are selectively removed, preferably without etching the barrier layer 14.
  • the protective layers 22a, 22b, 22c and 22d are then removed, and the remaining part of the barrier layer 14 is thereafter etched with the etching process stopping in the subsfrate 12.
  • the protective layer 22 may be selectively etched in accordance with any of the previously mentioned procedures such as with a Cl 2 /HBr and/or BCl 3 /Ar gas chemistry in the same plasma processing apparatus that selectively etched the mask layer 18.
  • the protective layer 22 may be selectively etched in the same chamber and under the same conditions for etching the elecfrode layer 16, i.e., in a high density plasma chamber containing a high density inductively coupled plasma. Etching of the protective layer 22 produced protective layers 22a, 22b, 22c and 22d. If the protective layer 22 is etched in accordance with the same procedure(s) for etching the elecfrode layer 16, the resist members 20a, 20b, 20c and 20d are initially removed before etching because they cannot be exposed to the high temperature (i.e., > 150°C) processing conditions for etching the electrode layer 16.
  • the high temperature i.e., > 150°C
  • the exposed parts of the electrode layer 16 are etched in accordance with any of the methods (e.g., the temperature of the wafer 10 is greater than about 150°C) and any of the etchant gases of any of the embodiments of the present invention to produce elecfrode layers 16a, 16b, 16c and 16d and expose selective parts of the banier layer 14.
  • the electrode layer 16 may be etched not only in a high density plasma but also in a low density plasma.
  • the mask layers 18a, 18b, 18c and 18d are then removed in any suitable plasm processing apparatus employing a plasma of any suitable etchant gas.
  • the protective layers 22a, 22b, 22c and 22d are then removed in accordance with any suitable procedure and process conditions. Subsequently, and as best shown in Fig. 26, the barrier layer 14 is then etched through and the etching process ceases in the substrate 12.
  • the foregoing sequences may be performed on the semiconductor wafer 10 of Fig. 1 (i.e., a wafer without the protective layer 22). All reactors and process conditions for conducting the foregoing mask and etching sequence may be any suitable reactors and process conditions.
  • the etching sequence is the same as for Fig. 26 except instead of etch-stopping in the barrier layer 14 before removal of the mask layer 18, etching continues into the substrate 12. After etching into the subsfrate 12, the mask layer 18 and the protective layer 22 are respectively removed, preferably without etching any further into the substrate 12.
  • the barrier layer 14 and the protective layer 22 may be any one of the same compounds for the barrier layer 14 and the protective layer 22 for the embodiment of the invention illusfrated in Fig. 26.
  • the mask layer 18 is preferably selected from the group consisting of Si 3 N , BSG, PSG, BPSG, a low dielectric constant (k) material with a dielectric constant less than about 3.0, and mixtures thereof.
  • All reactors and process conditions for conducting the foregoing sequences may be any suitable reactors and process conditions, including the conditions where the temperature of the subsfrate 12 is greater than about 150°C and where the etchant gases may be any of the etchant gases of any of the embodiments of the present invention.
  • the foregoing sequences may be performed on the semiconductor wafer 10 of Fig. 1 (i.e., a wafer without the protective layer 22).
  • Fig. 28 for another embodiment of the present invention, there is seen the semiconductor wafer 10 of Fig. 25 having the etch-stop layer 17 (e.g., Si 3 N , TiO 2 , RuO 2 , IrO 2 ).
  • the etching sequence comprises respectively etching through the protective layer 22, the elecfrode layer 16, and the banier layer 14.
  • the etching sequence stops in the etch-stop layer 17.
  • the mask layer 18 is selectively removed, preferably without etching the etch-stop layer 17, and then the protective layer 22 is removed.
  • the etch-stop layer 17 may be left intact or etched down to the substrate 12.
  • the barrier layer 14 and the protective layer 22 may be any one of the same compounds for the barrier layer 14 and the protective layer 22 for the embodiment of the invention in Fig. 26.
  • the mask layer 18 is preferably selected from the group consisting of CVD SiO 2 , TEOS, BSG, PSG, BPSG, a low dielectric constant material with a dielecfric constant of less than about 3.0 and mixtures thereof.
  • All reactors and process conditions for conducting the foregoing sequences may be any suitable reactors and process conditions, including the conditions where the temperature of the subsfrate 12 is greater than about 150°C and where the etchant gases may be any of the etchant gases of any of the embodiments of the present invention.
  • the foregoing sequences may be performed on the semiconductor wafer 10 without the protective layer 22.
  • the semiconductor wafer 10 having mask layer 18a and mask layer 18b.
  • the ratio of the combined thicknesses of mask layer 18a and mask layer 18b (i.e., thickness of mask layer 18a plus thickness of mask layer 18b) to the thickness of the electrode layer 16 ranges from about 0.2 to about 5.0, preferably from about 0.5 to about 4.0, more preferably from about 1.0 to about 3.0.
  • the ratio (thickness of mask layer 18a plus thickness of mask layer 18b)/thickness of elecfrode layer 16 ranges from about 0.2 to about 5.0, preferably from about 0.5 to about 4.0, more preferably from about 1.0 to about 3.0.
  • Mask layer 18a is preferably composed of a compound selected from the group consisting of Si 3 N 4 , BSG, PSG, BPSG, an organic polymer, a low dielectric constant material with a dielectric constant of less than about 3.0 and mixtures thereof.
  • a suitable organic polymer has been determined to be an organic polymer sold by Dow Chemical Co. of Midland, MI, under the registered frademark SiLK®.
  • Mask layer 18b is preferably composed of a compound selected from the group consisting of CVD SiO 2 , TEOS, Si 3 N 4 , BSG, PSG, BPSG, and SiC.
  • the barrier layer 14 and the protective layer 22 may be any one of the same compounds for the banier layer 14 and the protective layer 22 for the embodiment of the invention in Fig. 26.
  • Mask layer 18b is initially removed, or optionally left in place, and the etch sequence includes: respectively etching through the protective layer 22, the electrode layer 16, and the banier layer 14. The etch sequence terminates in the subsfrate 12. Subsequently, mask layer 18b, or both mask layers 18a and 18b, are selectively removed, preferably without etching the subsfrate 12. Protective layer 22 is selectively removed from the etched elecfrode layer 22, preferably without etching subsfrate 12. The foregoing sequences may be performed on the semiconductor wafer 10 without the protective layer 22.
  • All reactors and process conditions for conducting the foregoing sequences for this embodiment of the invention may be any suitable reactor and process conditions, including the conditions where the temperature of the subsfrate 12 is greater than about 150°C and where the etchant gases may be any of the etchant gases of any of the embodiments of the present invention.
  • the etchant gases may be any of the etchant gases of any of the embodiments of the present invention.
  • electrode layer 16 would include the combination of one or more layer(s) with each layer respectively comprising a noble metal and/or an oxide(s) of one or more noble metal and/or an alloy(s) of one or more noble metal(s).
  • electrode layer 16 could comprise the combination of a layer of platinum, a layer of ruthenium disposed on the layer of platinum, and a layer of iridium oxide disposed on the layer of ruthenium.
  • the “thickness of electrode layer 16” would include the summation of the respective thicknesses of all layer(s) that form the “elecfrode layer 16.”
  • the thickness of the electrode layer 16 would be 1,000A (i.e., 30 ⁇ A + 50 ⁇ A + 200 A).
  • the invention will be illusfrated by the following set forth example which s being given to set forth the presently known best mode and by way of illusfration only and not by way of any limitation. All parameters such as concentrations, mixing proportions, temperatures, pressure, rates, compounds, etc., submitted in this example are not to be construed to unduly limit the scope of the invention.
  • Example I A test semiconductor wafer was formulated with the following film stack:
  • the feature size of the patterned PR test semiconductor wafer was 0.3 ⁇ m block and 0.25 ⁇ m spacing.
  • the oxide mask i.e., the mask layer
  • the etchant gas for opening the oxide mask comprised about 68% by volume Ar and about 32% by volume CHF 3 .
  • the reactor and process conditions were as follows: Reactor Conditions
  • the photoresist was stripped from the oxide mask in an ASP chamber of the Metal Etch MxP CenturaTM brand plasma processing apparatus under the following recipe using microwave downstream O 2 /N 2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O 2 , 300 seem N 2 , and 2 Ton.
  • the Ti protective layer was etched with Ar, Cl 2 and BC1 3 as the etchant gases and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • the platinum layer of the test semiconductor wafer was then etched with Ar and Cl 2 as the etchant gas and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • the oxide mask was then removed in a 6: 1 FJF solution to produce the veil-less test semiconductor wafer shown in Fig. 20.
  • the remaining Ti protective layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC1 3 and Cl 2 as the etchant gases and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • a test semiconductor wafer was formulated with the following film stack: 0.8 ⁇ m patterned PR (photoresist)/500 ⁇ A Oxide/60 ⁇ A TiN/200 ⁇ A Pt/300A TiN
  • the feature size of the patterned PR test semiconductor wafer was 0.25 ⁇ m block and 0.2 ⁇ m spacing.
  • the oxide mask i.e., the mask layer
  • the etchant gas for opening the oxide mask comprised about 68% by volume Ar and about 32% by volume CHF 3 .
  • the reactor and process conditions were as follows: Reactor Conditions
  • the photoresist was stripped from the oxide mask in an ASP chamber of the Metal Etch MxP CenturaTM brand plasma processing apparatus under the following recipe using microwave downstream O 2 2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O 2 , 300 seem N 2 , and 2 Ton.
  • the TiN protective layer was etched with Ar, Cl 2 and BC1 3 as the etchant gases and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • the platinum layer of the test semiconductor wafer was then etched with Ar and Cl 2 and BC1 3 as the etchant gas and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • the oxide mask could have been removed in a 6: 1 HF solution to produce a veil-less test semiconductor wafer similar to the one shown in Fig. 20.
  • the remaining TiN protective layer could have been removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC1 3 and Cl 2 as the etchant gases and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
  • Example III A test semiconductor wafer was formulated with the following film stack:
  • the feature size of the patterned PR test semiconductor wafer was 0.35 ⁇ m line and 0.35 ⁇ m spacing.
  • the TEOS mask i.e., the mask layer
  • the etchant gas for opening the TEOS mask comprised about 68% by volume Ar and about 32% by volume CHF 3 .
  • the reactor and process conditions were as follows: Reactor Conditions
  • the photoresist was stripped from the TEOS mask in an ASP chamber of the Metal Etch MxP CenturaTM brand plasma processing apparatus under the following recipe using microwave downstream O 2 /N 2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O 2 , 300 seem N 2 , and 2 Ton.
  • the TiN protective layer was etched with Ar, Cl 2 and BC1 3 as the etchant gases and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
  • the platinum layer of the test semiconductor wafer was then etched with Ar, Cl 2 , BC1 3 and N 2 as the etchant gas and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • the TiN layer underneath the platinum layer was then etched with Ar, BC1 2 and N 2 as the etchant gas and in a DPTTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • the TEOS mark was then removed in a 6:1 HF solution to produce a veil- free test semiconductor wafer shown in the picture of Fig. 30.
  • the remaining TiN protective layer on the etched platinum layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC1 3 and Cl 2 as the etchant gases and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • Example IN A test semiconductor wafer was formulated with the following film stack: 1.2 ⁇ m patterned PR (photoresist)/200 ⁇ A TEOS/8000A SiLK ® /200 ⁇ A Pt/30 ⁇ A Ti ⁇ /SiO 2 substrate.
  • the feature size of the patterned PR test semiconductor wafer was 0.35 ⁇ m line and 0.35 ⁇ m spacing.
  • SiLK ® is a registered frademark of Dow Chemical Co. of Midland, Michigan 48674. It is a high temperature organic polymer. It is disposed on the Pt layer by the spin coating method.
  • the TEOS mask i.e., the first mask layer was etched with Ar, CF 4 and
  • the SiLK brand layer (i.e., the second mask layer) of the test semiconductor wafer was then etched (which also completely etched away the patterned PR) with NH 3 as the etchant gas in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • the TiN layer (i.e., a barrier layer) underneath the Pt layer is also etched with the same etchant gases and in the same DPS chamber and same reactor and process conditions after Pt etching. The result is shown in Figure 32.
  • Fig. 33 shows the final result of etching Pt layer after the SiLK ® brand mask was removed.
  • Fig. 34 is a top plan view picture of the etched platinum layer of Fig. 33.
  • Example V A test semiconductor wafer was formulated with the following film stack: 0.8 ⁇ m PR (photoresist)/700 ⁇ A Oxide/20 ⁇ A Ti/300 ⁇ A Pt/30 ⁇ A TiN/Si 3 N 4
  • the feature size of the formulated test semiconductor wafer was 0.27 ⁇ m block and 0.13 ⁇ m spacing.
  • the oxide hard mask i.e., the insulation layer
  • the etchant gas for opening up the oxide hard mask comprised about 68% by volume Ar and about 32% by volume CHF 3 .
  • the reactor and process conditions were as follows:
  • the photoresist was stripped from the oxide hard mask in an ASP chamber of the Metal Etch MxP CenturaTM brand plasma processing apparatus under the following recipe using microwave downstream O 2 /N 2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O 2 , 300 seem N 2 , and 2 Ton.
  • the Ti protective layer was etched with Ar, Cl 2 and BC1 3 as the etchant gases and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions:
  • CenturaTM brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
  • Fig. 37 The resulting etched platinum layer of the test semiconductor wafer is shown in the photograph picture of Fig. 37 wherein a platinum profile of about 88 degrees is shown.
  • Fig. 38 is a drawing representing the photograph of Fig. 37 with the respective parts identified by a reference numeral.
  • the oxide hard mask could have been removed in a 6:1 HF solution to produce the veil-less test semiconductor wafer similar to the one shown in Fig. 20.
  • the remaining Ti protective layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC1 3 and Cl 2 as the etchant gases and in a DPSTM brand chamber of the Metal Etch DPS CenturaTM brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
  • a test semiconductor wafer was formulated with the following film stack: 0.8 ⁇ m PR (photoresist)/500 ⁇ A Oxide/IOOA TiN/150 ⁇ A Pt 30 ⁇ A TiN/Si 3 N 4
  • the feature size of the formulated test semiconductor wafer was 0.3 ⁇ m block and 0.2 ⁇ m spacing.
  • the oxide hard mask i.e., the insulation layer
  • the etchant gas for opening up the oxide hard mask comprised about 68% by volume Ar and about 32% by volume CHF 3 .
  • the reactor and process conditions were as follows:

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Abstract

A method of etching a noble metal electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.35 νm and having a noble metal profile equal to or greater than about 80°. The method comprises heating the substrate to a temperature greater than about 150°C, and etching the noble metal electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising a gas selected from the group consisting of nitrogen, oxygen, a halogen (e.g., chlorine), argon, and a gas selected from the group consisting of BCl3, HRBr, and SiCl4 mixtures thereof. A semiconductor device having a substrate and a plurality of noble metal electrodes supported by the substrate. The noble metal electrodes have a dimension (e.g., a width) which include a value equal to or less than about 0.3 νm and a platinum profile equal to or greater than about 85°. Masking methods and etching sequences for patterning high density RAM capacitors are also provided. The substrate may be heated by a pedestal in a reactor chamber having a dielectric window including a deposit-receiving surface having a surface finish comprising a peak-to-valley roughness height with an average height value of greater than about 1,000Å.

Description

IMPROVED MASKING METHODS AND ETCHING SEQUENCES FOR PATTERNING ELECTRODES OF HIGH DENSITY RAM
CAPACITORS
This is a continuation-in-part patent application of copending patent application entitled "MASKING METHODS AD ETCHING SEQUENCES FOR PATTERNING ELECTRODES OF HIGH DENSITY RAM CAPACITORS," Serial No. 09/251,588, filed February 17, 1999. Copending patent application SerialNo. 09/251,588 is a continuation-in-part patent application of copending patent application entitled "ETCHING METHODS FOR ANISOTROPIC PLATINUM PROFILE," Serial No. 09/006,092, filed January 13, 1998.
This is also a continuation-in-part application of copending patent application entitled "IMPROVED ETCHING METHOD FOR ANISOTROPIC PLATINUM PROFILE," Serial o. 09/251,826, filed February 17, 1999. Copending patent application Serial No. 09/251 ,826 is a continuation-in-part patent application of copending patent application entitled "ETCHING METHODS FOR ANISOTROPIC PLATINUM PROFILE," Serial No. 09/006,092, filed January 13, 1998. This is also a continuation-in-part application of copending patent application entitled "IRIDIUM ETCHING METHODS FOR ANISOTROPIC PROFILE," Serial No. 09/251,633, filed February 17, 1999. Copending patent application Serial No. 09/251,633 is a continuation-in-part patent application of copending patent application entitled "ETCHING METHODS FOR ANISOTROPIC PLATINUM PROFILE, Serial No. 009/006,092, filed January 13, 1998. Benefit of all earlier filing dates with respect to all common subject matter is claimed.
Field of the Invention This invention relates to plasma etching of a noble metal (e.g., Pt, Ir, Ru, Pd, etc.). More specifically, this invention provides masking methods and etching sequences for plasma etching of a noble metal, such as platinum and/or iridium, for producing semiconductor integrated circuits containing noble metal (e.g., platinum, iridium, or an oxide or alloy of platinum and/or iridium) electrodes. BACKGROUND OF THE INVENTION Description of the Prior Art The implementation of digital information storage and retrieval is a common application of modern digital electronics. Memory size and access time serve as a measure of progress in computer technology. Quite often storage capacitors are employed as memory array elements. As the state of the art has advanced, small-feature- size high density dynamic random access memory (DRAM) devices require storage capacitors of larger capacitance having high dielectric constant materials. The high dielectric constant materials or ferroelectric materials are made primarily of sintered metal oxide and contain a substantial amount of very reactive oxygen. In the formation of capacitors with such ferroelectric materials or films, the electrodes must be composed of materials with least reactivity to prevent oxidation of the electrodes which would decrease the capacitance of storage capacitors. Therefore, precious metals, such as platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), etc., are preferred metals used in the manufacture of capacitors for high density DRAM.
Among the possible precious metals for capacitor electrodes, platinum and iridium have emerged as an attractive candidate because they are inert to oxidation and are known to have a leakage current (<10"9 amps/cm2) lower than other electrodes such as Ru0 and Pd. Platinum and iridium also are good conductors.
In the prior art, platinum and iridium etching has been conducted by means of isotropic etching, such as wet etching with aqua regia, or by anisotropic etching, such as ion milling with Ar gas or by other means. Because of the nature of isotropic etching, using wet etching with aqua regia causes deteriorated processing accuracy. The grade of precision in isotropic etching is not high enough for fine pattern processing. Therefore, it is difficult to perform submicron patterning of platinum electrodes due to its isotropic property. Furthermore, a problem with ion milling (i.e., anisotropic etching) occurs because the etching speed on platinum and iridium, which is to form the electrode, is too slow for mass production. In order to increase processing accuracy in etching platinum and iridium, research and development has been quite active, particularly in the area of etching platinum and iridium by means of a dry etching process where etchant gases (e.g., Cl2, HBr, O2, etc.) are used. The following prior art is representative of the state of art with respect to etching platinum and iridium with a plasma of etching gases.
U.S. Patent No. 5,492,855 to Matsumoto et al. discloses a semiconductor device manufacturing method, wherein an insulation layer, a bottom electrode Pt layer, a dielectric film and a top electrode Pt layer are provided on top of a substrate having already-completed circuit elements and wiring, and then, a capacitor is formed by selectively dry etching the bottom electrode Pt layer after selectively dry etching the top electrode Pt layer and the dielectric film. The manufacturing method uses a gas containing an S component as etching gas for Pt etching, or an etching gas containing S component as an additive gas; and also it implants S into the Pt layer before the Pt dry etching process by means of ion implantation to compose a S and Pt compound, and then dry etches the Pt compound thus composed.
U.S. Patent No. 5,527,729 to Matsumoto et al. discloses process steps to form on a substrate in which circuit elements and wirings, etc., are already shaped, an insulation layer, a first metal layer, a dielectric film and a second metal layer. A top electrode and a capacitance film are formed by dry etching the second metal layer and the dielectric film. A bottom electrode is formed by dry etching the first metal layer. The etching gas for dry etching the second metal layer is a mixed gas containing hydrogen halide (e.g., HBr) and oxygen, having a ratio of oxygen against the total of hydrogen halide and oxygen set at about 10%-35%. The etching gas is also taught as a gas containing hydrocarbon, such as chloroform. Matsumoto et al. employs a silicon oxide layer as the insulation layer on the substrate, and a platinum layer or palladium layer as the first and second metal layers. Dry etching of the second metal layer and dielectric film is conducted in a low pressure region not higher than about 5 Pa, where the etching speed is high. Matsumoto et al. further teaches that where a mixed gas of hydrogen halide and oxygen is used as the etching gas, the etching speed on the silicon oxide layer can be made sufficiently low relative to that on the second metal layer made of a platinum layer or a palladium layer; in this way, the excessive etching of the silicon oxide layer underlying the first metal layer is avoided, and damage to the circuit elements and wiring, etc. underneath the silicon oxide layer can be prevented. Furthermore according to Matsumoto et al, the ratio of etching speed of the platinum and dielectric material to the resist can be increased by lowering the etching speed on the resist. Therefore, etching of the platinum and dielectric material may be conducted by using a mask of normal lay- thickness resist (generally speaking, about 1.2 μm to about 2.0 μm thick), instead of using a conventional thick-layer resist (about 3 μm and thicker).
Chou et al. in an article entitled "Platinum Metal Etching in a Microwave Oxygen Plasma", J. Appl. Phys. 68 (5), 1 September 1990, pages 2415-2423, discloses a study to understand the etching of metals in both plasma and chemical systems. The study found that the etching of platinum foils in an oxygen plasma generated in a flow- type microwave system and that very rapid etching (~6A/s) took place even at low power inputs (200 W). The principal plasma parameters, including oxygen atom concentration, ion concentration, and electron temperature, were measured by Chou et al. as a function of distance below the microwave coupler. These were correlated to the rate of foil etching, which decreased with increasing distance from the coupler. On the basis of these correlations Chou et al. formulated a simple mechanistic model. The study by Chou et al. further found that the etching of platinum in an oxygen plasma jet results from the concomitant action of oxygen atoms and high energy electrons.
Nishikawa et al. in an article entitled "Platinum Etching and Plasma Characteristics in RF Magnetron and Electron Cyclotron Resonance Plasmas", Jpn. J. Appl. Phys., Vol. 34 (1995), pages 767-770, discloses a study wherein the properties of platinum etching were investigated using both RF magnetron and electron cyclotron resonance (ECR) plasmas, together with measurement of the plasma parameters (neutral concentration, plasma density, etc.). Nishikawa et al. performed experiments in Cl2 plasmas over a pressure ranging from 0.4 to 50 mTorr. In RF magnetron plasmas, the etch rate of Pt was constant at the substrate temperature of from 20 to 160°C. The etch rate and the plasma electron density increased with gas pressure decreasing from 50 to 5 mTorr. In ECR plasmas for RF power of 300 W, Nishikawa et al. found that the etch rate of Pt was almost constant (~100 nm/min) with gas pressure decreasing from 5 to 0.4 mTorr, while the plasma electron density gradually increased with decreasing gas pressure. The study by Nishikawa et al. discusses these experimental results with respect to the relationship between the etch yield and the ratio of neutral Cl2 flux and ion flux incident on the substrate.
Yokoyama et al. in an article entitled "High-Temperature Etching of PZT/Pt/TiN Structure by High-Density ECR Plasma", Jpn. J. Appl. Phys., Vol. 34 (1995), pages 767-770, discloses a study wherein micron patterning technologies for the
PZT/Pt/TiN/Ti structure with a spin on glass (SOG) mask are demonstrated using a high- density electron cyclotron resonance (ECR) plasma and a high substrate temperature above 300°C. A 30%-Cl2/Ar gas was used to etch a lead zirconate titanate (PZT) film. No deposits remained, which resulted in an etched profile of more than 80°. A 40%- O2/Cl2 gas was used to etch a Pt film. The etching was completely stopped at the Ti layer. 30-nm-thick deposits remained on the sidewall. They were removed by Yokoyama et al. after dipping in hydrochloric acid. The etched profile of a Pt film was more than 80°. The Ti/TiN/Ti layer was etched with pure Cl2 gas. The size shift from the SOG mask was less than 0.1 μm. Yokoyama et al. did not detect any interdiffusion between SOG and PZT by transmission electron microscopy and energy dispersive x-ray spectroscopy (TEM-EDX) analysis.
Yoo et al. in an article entitled "Control of Etch Slope During Etching of Pt in Ar/Cl2/O2 Plasmas", Jpn. J. Appl. Phys., Vol. 35 (1996), pages 2501-2504, teaches etching of Pt patterns of the 0.25 μm design rule at 20°C using a magnetically enhanced reactive ion etcher (MERIE). Yoo et al. found that a major problem of etching with a MERIE was the redeposition of the etch products onto the pattern sidewall, making it difficult to reduce the pattern size. In both cases separately using a photoresist mask and an oxide mask, the redeposits of the etch products onto the sidewall were reduced by the addition of Cl to Ar, although the etched slope was lowered to 45°. The redeposits were removed by an HCl cleaning process.
Kotecki in an article entitled "High-K Dielectric Materials for DRAM Capacitors", Semiconductor International, November 1996, pages 109-116, the potential advantages of incorporating high-dielectric materials into a storage capacitor of a dynamic random access memory (DRAM) are described and the requirements of the high dielectric layer are reviewed as they relate to use in a simple stack capacitor structure suitable for the gigabit generation. Kotecki teaches that when considering the use of high-dielectric materials in a stack capacitor structure, the following issues need to be addressed: electrode patterning, high-dielectric material/barrier interaction, electrode/high-dielectric material interaction, surface roughness (e.g., hilocking, etc.), step coverage, high-dielectric material uniformity (e.g., thickness, composition, grain size/orientation, etc.), and barrier (e.g., O2 and Si diffusion, conductivity, contact resistance and interactions, etc.). Various materials and combinations of materials were studied by Kotecki for use with perovskite dielectrics including the noble metals (i.e., Pt, Ir, Pd) and conductive metal oxides (i.e., IrO2 and RuO ). The work function of these materials, their ability to be patterned by dry etching, the stability of the surface with regards to surface roughening and their suitability in a semiconductor fabricator are listed by Kotecki in the following Table I:
TABLE I
Figure imgf000007_0001
Kotecki further teaches in the article entitled "High-K Dielectric Materials for DRAM Capacitors" that one of the major problems which needs to be overcome with respect to the manufacturing of DRAM chips using capacitors is the problem of electrode patterning. There are minimal volatile species produced during the dry etching of the noble metal electrodes such as Pt, Ru, Pd and Ir. Since the etch mechanism is primarily by physical sputtering, even during a RIE process, fences are typically formed on the sides of the photoresist. To eliminate the problem of fencing, it is possible to etch the fence layer and erode the sides of the photoresist during the etch process which leads to "clean" metal structures but with sloping sidewall angles and a loss of control over critical feature sizes. As the dimension of the feature shrinks to 0.18 μm or below, only limited tapering of the sidewall angle can be tolerated. Kotecki presents in the following Table II some of the high-dielectric materials which have been considered for use in a DRAM capacitor, the various methods which can be used to form the films, and the range of reported permittivites:
TABLE II
Figure imgf000009_0001
Milkove et al. reported in a paper entitled "New Insight into the Reactive Ion Etching of Fence-Free Patterned Platinum Structures" at the 43rd Symposium of AVS, October 1996, Philadelphia, PA, that an investigation was undertaken to characterize the time progression of the Pt etch process during the reactive ion etching (RIE) offence-free patterned structures. The experiment by Milkove et al. consisted of coprocessing two oxidized Si wafers possessing identical 2500 A thick Pt film layers, but different photoresist (PR) mask thicknesses. Etching was suspended at 20, 40, 60 and 80%) of the full etch process in order to cleave off small pieces of wafer for analysis by a scanning electron microscopy (SEM). Using Cl2-based RIE conditions known to produce fence-free etching for 2500 A thick film layers, Milkove et al. discovered that a severe fence actually coats the PR mask during the first 20% of the etch process. As the etch continues the fence structure evolves, achieving a maximum height and width followed by progressive recession until disappearing completely prior to process endpoint. The data from Milkove et al. shows that the final profile of an etched Pt structure possess a functional dependence on the initial thickness and slope of the PR mask, as well as on the initial thickness of the Pt layer. Milkove et al. further reported in the paper entitled "New Insight Into The Reactive Ion Etching of Fence-free Patterned Platinum Structures" that the observed behavior of the transient fence provides the strongest evidence to date supporting the existence of a chemically assisted physical sputtering component associated with the RIE of Pt films in halogen-based plasmas.
Keil et al. teaches in an article entitled "The Etching of Platinum Electrodes for PZT Based Ferroelectric Devices", Electrochemical Society Proceedings, Vol. 96-12 (1996), pages 515-520, that the technical difficulties of fabricating capacitors employing platinum Pt etching is most often dominated by sputtering processes. While oxygen and/or various gaseous chlorides or fluorides are used to chemically enhance the etch process, the products of both etch mechanisms are usually of low volatility and tend to redeposit on the wafer. After etching, large wall-like structures extend up from the edges of the Pt region. These wall-like structures are frequently referred to as "veils" or "fences" or "rabbit ears" and can reach lengths which are more than double the thickness of the Pt film to which they are attached. The existence of such structures makes useful deposition of the PZT layer impossible. Keil et al. further teaches that even when one is able to attenuate redeposition to the point where only small "nub" like features are present, the high electric fields which will form at such "nubs" enhances the likelihood for dielectric breakdown. Although process conditions can be found which result in either low redeposition or even no redeposition, they most often also give an unacceptably tapered platinum profile angle. Keil et al. observed that redeposition becomes more severe as process conditions are pushed toward those which give increasingly vertical sidewalls. While a post etch wet clean in a solvent bath is frequently used, the heavy redeposition which attends the pursuit of vertical sidewalls regularly renders this approach minimally effective.
The foregoing prior art illustrates that generally a clean vertical dense area profile and CD (critical dimension) control of the etch profiles are critical factors for successful plasma etching of 1-Gbit (and beyond) DRAM ferroelectric devices possessing platinum electrodes. Redeposition and profile control are found to be strongly interlinked. Optimization of both profile angle and redeposition requires a tradeoff between the two. Where as vigorous post etch cleaning (e.g., wet cleaning with acid, mechanical polishing, etc.) can relieve some of the need to achieve a deposition free plasma etch, such post etch cleaning does not possess the accuracy that is desired as the platinum electrode itself is typically eroded and/or deteriorated by currently known post etch cleaning methods.
Therefore, what is needed and what has been invented is a method for etching a noble metal (e.g., platinum, iridium, ruthenium, etc. and oxides and/or alloys of noble metals) electrode layer to produce a high density integrated circuit semiconductor device having noble metal (e.g., platinum, iridium, ruthenium, etc. and oxides and/or alloys of noble metals) electrodes with a high degree (i.e., ≥ 85°) of noble metal (e.g., platinum or iridium) profile anisotropy. Masking methods and etching sequences are provided to assist for plasma etching of noble metal. What is further needed and what has been invented is a semiconductor device including a plurality of platinum or iridium electrodes having a platinum or iridium profile equal to or greater than about 85° and separated by a distance equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm, with each electrode having a critical dimension (e.g., a width) equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm.
SUMMARY OF THE INVENTION The present invention broadly provides a method of etching a platinum layer disposed on a substrate comprising the steps of: a) providing a substrate supporting a platinum layer; b) heating the substrate (such as with a pedestal supporting the substrate) of step (a) to a temperature greater than about 150°C; and c) etching the platinum layer including employing a high density plasma of an etchant gas comprising a halogen-containing gas (e.g., a halogen such as chlorine) and a noble gas (e.g., argon) to produce the substrate supporting at least one etched platinum layer.
In another embodiment of the present invention, the present invention broadly provides: a) providing a substrate supporting an iridium layer; b) heating the substrate of step (a) to a temperature greater than about 150°C; and c) etching the iridium layer including employing a high density plasma of an etchant gas comprising a halogen-containing gas, and a noble gas to produce said substrate supporting at least one etched iridium layer. The etchant gas may additionally include a gas selected from the group consisting of O2 and BC13. Alternatively, the etchant gas may additionally include a gas selected from the group consisting of O2, HCl, HBr, and mixtures thereof. The substrate of step (a) may be heated by heating the pedestal supporting the substrate to a sufficient temperature to cause the substrate to possess a temperature greater than about 150°C.
In the foregoing methods, the platinum layers are preferably a platinum electrode layer and an iridium electrode layer, respectively. The high density plasma of an etchant gas is a plasma of an etchant gas having an ion density greater than about 109/cm3, preferably greater than about 10π/cm3. The etchant gas may also include a gas selected from the group consisting of BC13, HBr, SiC-U and mixtures thereof. The platinum layer and the iridium layer may each additionally comprise a mask layer disposed on a selected part of the particular respective layer to selectively protect the particular respective layer during the etching step above. In the embodiment of the present invention for etching iridium, if the mask layer is a hard mask layer comprising Ti and/or TiN, the etchant gas having Ar/Cl2/O chemistry with high O concentration produces an iridium to Ti and/or TiN selectivity of greater than about 8 (preferably greater than about 10) during etching of iridium. The platinum layer and the iridium layer may each also additionally comprise a protective layer disposed on the selected part of the particular respective layer between the mask layer and the particular respective layer. The mask layer may be removed during or after the etching step. Similarly, the protective layer may be removed during or after the etching step.
The platinum layer is part of or is contained in a platinum wafer, and the method of etching a platinum layer additionally comprises disposing the platinum wafer including the platinum layer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step in the high density plasma chamber under the following process conditions:
Process Parameters
Etchant Gas Flow 50 to 500 seem
Halogen Gas (e.g., Cl2) 20% to 95% by vol.
Noble Gas (e.g., Ar) 5% to 80% by vol.
Pressure, mTorr 0.1 to 300 milliTorr RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts
Temperature (° C) of Platinum Wafer 150° to 500° C
Platinum Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of
Coil Inductor 100 K to 300 MHz
RF Frequency of Wafer Pedestal 100 K to 300 MHz In another embodiment of the present invention, there is broadly provided a method of etching a platinum electrode layer disposed on a substrate comprising the steps of:
(a) providing a substrate supporting a platinum electrode layer;
(b) heating said substrate of step (a) to a temperature greater than about 150°C; and
(c) etching said platinum electrode layer in a plasma of an etchant gas comprising nitrogen and a halogen (e.g., chlorine) to produce said substrate supporting at least one etched platinum electrode layer. The plasma may be a low density plasma or a high density plasma and the etchant gas may additionally comprise a gas selected from the group consisting of a noble gas (e.g., argon), HBr, BC13, SiCL, and mixtures thereof.
In another embodiment of the present invention, the etching step (c) may be performed in a low density (or high density) plasma chamber under the following process conditions:
Process Parameters
Etchant Gas Flow 50 to 500 seem
Halogen Gas (e.g., Cl) 40% to 90% by vol.
Noble Gas (e.g., Ar) 0.1% to 40% by vol.
Nitrogen gas 0.1% to 60% by vol.
Pressure, mTorr 0.1 to 500 milliTorr
RF Power (watts) of Coil Inductor* 0 to 5000 watts
RF Power (watts) of Wafer Pedestal 100 to 5000 watts
Platinum Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of
Coil Inductor 100Kto 300 MHz
RF Frequency of
Wafer Pedestal 100K to 300 MHz
*If 0 watts is employed or indicated for the coil inductor, 0 watts indicates that an RIE chamber is being used. The etched platinum layer includes a platinum profile equal to or greater than about 80°, preferably equal to or greater than about 85°, more preferably equal to or greater than about 87°, most preferably equal to or greater than about 88.5°. In one embodiment of the invention, the etchant gas for the process conditions immediately above may alternatively comprise from about 10% to about 90% by vol. of a halogen (e.g., Cl2), from about 5% to about 80% by vol. of a noble gas (e.g., argon), and from about 4% to about 25%) by vol. HBr and/or BC13. In another embodiment of the invention, the etchant gas may alternatively comprise from about 0.1% to about 60% by volume nitrogen, from about 40% to about 90% by volume of a halogen (e.g., Cl2), from about 0.1% to about 40% by volume of a noble gas (e.g., argon), and from about 1% to about 30%) by volume of a gas selected from the group of combining HBr, BC13, SiCl4, and mixtures thereof.
The iridium layer is part of or is contained in an iridium wafer, and the method of etching an iridium layer additionally comprises disposing the iridium wafer including the iridium layer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following process conditions:
Process Parameters
Etchant Gas Flow 50 to 500 seem
Halogen Gas (e.g., Cl2) 10% to 60% by vol.
Noble Gas (e.g., Ar) 30% to about 80%) by vol.
Oxygen 5% to 40% by vol.
Pressure, mTorr 0.1 to 300 milliTorr
RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts
Iridium Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of Coil Inductor 100 Kto 300 MHz
RF Frequency of Wafer Pedestal 100 Kto 300 MHz The etched iridium layer includes an iridium profile equal to or greater than about 80°, more preferably equal to or greater than about 82°, most preferably equal to or greater than about 85.0°. The etchant gas for the process conditions immediately above may alternatively comprise from about 5% to about 20%> by vol. oxygen, from about 10%> to about 60%) by vol. of a halogen (e.g., Cl2), from about 30% to about 80% by vol. of a noble gas (e.g., argon), and from about 5% to about 20% by vol. HBr and/or HCl.
The present invention also broadly provides a method for producing a capacitance structure including an electrode (i.e., a platinum electrode or an iridium electrode layer) comprising the steps of: a) providing a substrate supporting a layer (i.e., a platinum electrode layer or an iridium electrode layer), and at least one mask layer disposed on a selected part of said layer; b) heating the substrate of step (a) to a temperature greater than about 150°C; and c) . etching the layer including employing a plasma of an etchant gas comprising a halogen (e.g., chlorine) and a noble gas (e.g., argon) to produce a capacitance structure having at least one electrode (i.e., the platinum electrode or iridium electrode). The etchant gas may also comprise nitrogen.
The at least one mask layer is removed during or after the etching step (c) immediately above. The layer of step (a) immediately above may additionally comprise a protective layer disposed on the selected part of the layer between the mask layer and the layer. The etched layer (i.e., the etched platinum layer or the etched iridium layer) produced by the etching step (c) immediately above includes a profile (i.e., a platinum profile or an iridium profile) equal to or greater than about.80° (particularly for iridium), preferable equal to or greater than about 85°, more preferably equal to or greater than about 87°, most preferably equal to or greater than about 88.5°. In one embodiment of the invention, the etchant gas of the plasma of step (c) more specifically includes a halogen (e.g., chlorine), a noble gas (e.g., argon), and a gas selected from the group consisting of HBr, BC13 and mixtures thereof. Alternatively, the etchant gas of the plasma of step (c) includes nitrogen (N ) and a halogen (e.g., chlorine). In another embodiment of the invention, the etchant gas of the plasma of step (c) more specifically includes nitrogen (N2), a halogen (e.g., chlorine), a noble gas (e.g., argon), and a gas selected from the group consisting of HBr, BC13, SiCl , and mixtures thereof. The platinum electrode layer is part of or is contained in a platinum electrode wafer, and the method for producing a capacitance structure including a platinum electrode layer additionally comprises disposing, prior to the etching step (c), the platinum electrode wafer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following previously indicated process conditions:
Process Parameters Etchant Gas Flow 50 to 500 seem
Halogen Gas (e.g., Cl2) about 10% to about 90% by vol.
Noble Gas (e.g., Ar) about 5% to about 80% by vol.
HBr and or BC13 about 4% to about 25% by vol.
Pressure, mTorr 0.1 to 300 milliTorr RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts
Temperature (° C) of Platinum Electrode Wafer about 150° to about 500° C
Platinum Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of
Coil Inductor 100 K to 300 MHz
RF Frequency of Wafer Pedestal 100 K to 300 MHz
The produced platinum electrodes are separated by a distance or space having a dimension equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm. Each of the platinum electrodes include a dimension having a value equal to or less than about 0.6 μm, preferably equal to or less than about 0.35 μm, more preferably equal to or less than about 0.3 μm. More preferably, each of the platinum electrodes have a width equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm, a length equal to or less than about 1.0 μm, preferably equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm. The plasma of the etchant gas for etching any of the metals of any of the embodiments of the present invention comprises a high density inductively coupled plasma. The etchant gas preferably comprises a noble gas selected from the group consisting of helium, neon, argon, krypton, xenon, radon, and mixtures thereof. More preferably, the noble gas is selected from the group consisting of helium, neon, argon, and mixtures thereof. Most preferably, the noble gas is argon. As was previously indicated, the etchant gas of the high density inductively coupled plasma most preferably comprises, or preferably consists of or consists essentially of, chlorine, argon, and BC13 and/or HBr.
In a preferred embodiment of the invention for etching iridium, the etchant gas of the plasma of step (c) more specifically includes oxygen, a halogen (e.g., chlorine), a noble gas (e.g., argon), and a gas selected from the group consisting of HBr, HCl and mixtures thereof. The iridium electrode layer is part of or is contained in an iridium electrode wafer, and the method for producing a capacitance structure including an iridium electrode layer additionally comprises disposing, prior to the etching step (c), the iridium electrode wafer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following previously indicated process conditions:
Process Parameters
Etchant Gas Flow 50 to 500 seem
Oxygen about 5% to about 20% by vol.
Halogen Gas (e.g., Cl ) about 10% to about 60% by vol.
Noble Gas (e.g., Ar) about 30% to about 80% by vol.
HBr and/or HCl about 5% to about 20% by vol.
Pressure, mTorr 0.1 to 300 milliTorr
RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts Temperature (° C) of
Iridium Electrode Wafer about 150° to about 500° C
Iridium Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of
Coil Inductor 100 K to 300 MHz
RF Frequency of
Wafer Pedestal 100 K to 300 MHz
The plasma of the etchant gas for etching iridium comprises a high density inductively coupled plasma. The etchant gas preferably comprises a noble gas selected from the group consisting of helium, neon, argon, krypton, xenon, radon, and mixtures thereof. More preferably, the noble gas is selected from the group consisting of helium, neon, argon, and mixtures thereof. Most preferably, the noble gas is argon. As was previously indicated, the etchant gas of the high density inductively coupled plasma for etching iridium most preferably comprises, or preferably consists of or consists essentially of, chlorine, argon, and oxygen or BC13; alternatively, oxygen, chlorine, argon, and HCl and/or HBr.
The present invention further broadly provides a method of manufacturing a semiconductor device comprising the steps of: a) forming a patterned resist layer, a mask layer and an electrode layer (e.g., a platinum electrode layer or an iridium electrode layer) on a substrate having circuit elements formed thereon; b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the electrode layer to produce the substrate supporting the patterned resist layer, a residual mask layer, and the electrode layer; c) removing the resist layer of step (b) to produce the substrate supporting the residual mask layer and the electrode layer; d) heating the substrate of step (c) to a temperature greater than about 150° C; and e) etching the electrode layer of step (d) including employing a high density plasma of an etchant gas. In the embodiment of the invention for etching a platinum layer, the etchant gas preferably comprises a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce a semiconductor device having at least one platinum electrode. In the embodiment of the invention for etching an iridium layer, the etchant gas comprises oxygen, a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce a semiconductor device having at least one iridium electrode. The present invention also further broadly provides a method of etching an electrode layer (e.g. a noble metal) disposed on a substrate comprising the steps of: a) providing a substrate (e.g., a SiO2 substrate) supporting an electrode layer (e.g., a noble metal including a platinum electrode layer or an iridium electrode layer), a protective layer (e.g., TiN and/or Ti) on the electrode layer, and a mask layer (e.g., BSG oxide, BPSG oxide, PSG oxide, Si3N4, TEOS, CVD SiO2, and mixtures thereof) on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the protective layer to expose part of the protective layer and to produce the substrate supporting the electrode layer, the protective layer on the electrode layer, a residual mask layer on the elecfrode layer, and the patterned resist layer on the residual mask layer; c) removing the patterned resist layer from the residual mask layer of step (b) to produce the substrate supporting the electrode layer, the protective layer on the electrode layer, and the residual mask layer on the protective layer; d) heating the substrate of step (c) to a temperature greater than about
150° C; e) etching the exposed part of the protective layer to expose part of the electrode layer and to produce the substrate supporting the electrode layer, a residual protective layer on the elecfrode layer, and the residual mask layer on the residual protective layer; and f) etching the exposed part of the electrode layer of step (e) including employing a high density plasma of an etchant gas. If the elecfrode layer being etched comprises a platinum, the etchant gas comprises a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce the substrate supporting an etched platinum electrode layer having the residual protective layer on the etched platinum layer, and the residual mask layer on the residual protective layer. If the electrode layer being etched includes iridium, the etchant gas comprises oxygen, a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce the subsfrate supporting an etched iridium electrode layer having the residual protective layer on the etched iridium electrode layer, and the residual mask layer on the residual protective layer. The patterned resist layer is removed from the residual mask layer before heating the subsfrate to a temperature greater than about 150° C because such high temperatures would destroy the resist layer. The residual mask layer may be removed from the electrode layer either before or after heating of the subsfrate to a temperature greater than about 150° C, and during or after the etching step. The electrode layer (e.g., the noble metal including a platinum elecfrode layer or an iridium electrode layer) is part of or is contained in a wafer (e.g., the noble metal including a platinum electrode wafer or an iridium elecfrode wafer). The purpose of the protective layer is to ensure the adhesion between the mask layer and the elecfrode layer (e.g., the profile of a platinum electrode layer or the profile of an iridium elecfrode layer), and also to maintain the profile of the layer (e.g., a platinum electrode layer or an iridium electrode layer), especially during the etching process of the present invention. Preferably, the residual protective layers are removed from the etched layer (e.g., etched platinum layer and/or etched iridium layer), after the etching step (e.g., the platinum etching step or the iridium etching step).
In another embodiment of the present invention, one or more barrier layers may be disposed on the substrate to separate the electrode layer (e.g. a noble metal layer) from the substrate. The barrier layer may include TiN and/or Ti and/or BST (barium titanate and/or strontium titanate) and/or Si3N4. The barrier layer may also include two or more barrier layers such as a SiN-containing layer (e.g., Si3N ) disposed on the substrate and a barrier protective layer (e.g., TiN and/or Ti) disposed on the SiN-containing layer. Optionally, the electrode layer (e.g. the noble metal layer) may not have a protective layer disposed thereon but may directly support and contact a mask layer, such as a SiN- containing layer (e.g., Si3N4).
In another embodiment of the present invention there is provided a method of etching a noble metal (Pt, Ir, Ru, Pd etc.) layer disposed on a subsfrate comprising the steps of: a) providing a substrate supporting a barrier layer (e.g., TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta), a noble metal (e.g., Pt, Ir, Pd, Ru, etc.) layer on the barrier layer, a protective layer (e.g., TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta) on the noble metal layer, a mask layer, preferably a mask layer having a thickness ranging from about 6000A to about 9,OOθA, on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of a mask etchant gas to break through and to remove the portion of the mask layer from the protective layer to expose part of the protective layer and to produce the substrate supporting the barrier layer, the noble metal layer on the barrier layer, the protective layer on the noble metal layer, a residual mask layer on the protective layer, and the patterned resist layer on the residual mask layer; c) removing the patterned resist layer from the residual mask layer of step (b) to produce the substrate supporting the barrier layer, the noble metal layer on the barrier layer, the protective layer on the noble metal layer, and the residual mask layer on the residual protective layer; d) etching the exposed part of the protective layer to expose part of the noble metal layer and to produce the subsfrate supporting the barrier layer, the noble metal layer on the barrier layer, a residual protective layer on the noble metal layer, and the residual mask layer on the residual protective layer; e) heating the substrate of step (d) to a temperature greater than about
150°C; f) etching the exposed part of the noble metal layer of step (d) including employing plasma of an etchant gas selected from the group consisting of a halogen-containing gas, a noble gas, nitrogen, oxygen, and mixtures thereof, to produce the substrate supporting the barrier layer, an etched noble metal layer on the barrier layer, the residual protective layer on the etched noble metal layer, and the residual mask layer on the residual protective layer; g) removing the residual mask layer from the residual protective layer to produce the subsfrate supporting the barrier layer, the etched noble metal layer on the barrier layer, and the residual protective layer on the etched noble metal layer; and h) etching a portion of the barrier layer including employing a plasma of a barrier etchant gas to expose part of the subsfrate to produce the substrate supporting a residual barrier layer, the etched noble metal layer on the residual barrier layer, and the residual protective layer on the etched noble metal layer. The step (f) etching of the noble metal layer of step (d) additionally produces a remaining noble metal layer on the barrier layer. The step (g) removing of the residual mask layer additionally produces the remaining noble metal layer on the barrier layer, and the method additionally comprises etching the remaining noble metal layer on the barrier layer prior to the step (h) etching. The mask layer comprises a compound selected from the group consisting of BSG oxide, PSG oxide, Si3N4, TEOS, CVD SiO2, a low dielectric constant material with a dielecfric constant of less than 3.0, and mixtures thereof. The foregoing method may be conducted without the protective layer. The foregoing method may also be conducted by etching the barrier layer prior to removing the residual mask layer. Thus, after etching step (f) wherein the exposed part of the noble metal layer of step (d) is etched, the method of etching a noble metal layer disposed on a subsfrate would comprise the following step (g) and step (h): (g) etching a portion of the barrier layer including employing a plasma of a barrier etchant gas to expose part of the substrate to produce the subsfrate supporting a residual barrier layer, the etched noble metal layer on the residual barrier layer, the residual protective layer on the etched noble metal layer, and the residual mask layer on the residual protective layer; and (h) removing the residual mask layer from the residual protective layer to produce the substrate supporting the residual barrier layer, the etched noble metal layer on the residual barrier layer, and the residual protective layer on the etched noble metal layer.
Thus further, in another embodiment of the present invention there is provided a method of etching a noble metal (Pt, Ir, Ru, Pd etc.) layer disposed on a substrate comprising the steps of: a) providing a subsfrate supporting an etch-stop layer (e.g., Si3N4, TiO2, RuO2, and IrO2), a barrier layer on the etch-stop layer, a noble metal layer on the barrier layer, a protective layer on the noble metal layer, a mask layer, preferably a mask layer having a thickness ranging from about 6000A to about 9000A, on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of a mask etchant gas to break through and to remove the portion of the mask layer from the protective layer to expose part of the protective layer and to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, the noble metal layer on the barrier layer, the protective layer on the noble metal layer, a residual mask layer on the protective layer, and the patterned resist on the residual mask layer; c) etching the exposed part of the protective layer to expose part of the noble metal layer and to produce the subsfrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, the noble metal layer on the barrier layer, a residual protective layer on the noble metal layer, the residual mask layer on the residual protective layer, and the patterned resist layer on the residual mask layer; d) removing the patterned resist layer from the residual mask layer of step (c) to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, the noble metal layer on the barrier layer, the residual protective layer on the noble metal layer, and the residual mask layer on the residual protective layer; e) heating the subsfrate of step (d) to a temperature greater than about 150°C; f) etching the exposed part of the noble metal layer of step (d) including employing a plasma of an etchant gas selected from the group consisting of a halogen-containing gas, a noble gas, nifrogen, oxygen, and mixtures thereof, to expose part of the barrier layer and to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, an etched noble metal layer on the barrier layer, the residual protective layer on the etched noble metal layer, and the residual mask layer on the residual protective layer; g) removing the residual mask layer from the residual protective layer to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, the etched noble metal layer on the barrier layer and the residual protective layer on the etched noble metal layer; and h) etching the residual protective layer for removing the residual protective layer from the etched noble metal layer to produce the subsfrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, and the etched noble metal layer on the barrier layer. The foregoing method may be conducted without the protective layer. The method of etching additionally comprises etching the exposed part of the barrier layer to expose part of the etch-stop layer to produce the substrate supporting the etch-stop layer, a residual barrier layer on the etch-stop layer, and the etched noble metal layer on the residual barrier layer.
In another embodiment of the present invention, there is further provided a method of etching a noble metal (Pt, Ir, Ru, Pd etc.) layer disposed on a substrate comprising the steps of: a) providing a substrate supporting an etch-stop layer, a barrier layer on the etch-stop layer, a noble metal layer on the barrier layer, a mask layer on the noble metal layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including a plasma of a mask- etchant gas to break through and to remove the portion of the mask layer from the noble metal layer to expose part of the noble metal layer and to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, the noble metal layer on the barrier layer, a residual mask layer on the noble metal layer, and the patterned resist layer on the residual mask layer; c) removing the patterned resist layer from the residual mask layer of step (b) to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, the noble metal layer on the barrier layer, the residual mask layer on the noble metal layer; d) heating the substrate of step (c) to a temperature greater than about 150°C; e) etching the exposed part of the noble metal layer of step (b) including employing a plasma of an etchant gas selected from the group consisting of a halogen-containing gas, a noble gas, N2, O2, and mixtures thereof, to expose part of the barrier layer and to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, an etched noble metal layer on the barrier layer, and the residual mask layer on the etched noble metal layer; and f) removing the residual mask layer from the etched noble metal layer to produce the substrate supporting the etch-stop layer, the barrier layer on the etch-stop layer, and the etched noble metal layer on the barrier layer. The method of etching additionally includes etching the exposed part of the barrier layer, preferably prior to the removing step (f), to expose part of the etch-stop layer to produce the substrate supporting the etch-stop layer, a residual barrier layer on the etch-stop layer, and the etched noble metal layer on the residual barrier layer.
Also provided in accordance with an embodiment of the present invention is a method of etching a noble metal layer disposed on a substrate comprising the steps of: a) providing a subsfrate supporting a barrier layer, a noble metal layer on the barrier layer, a first mask layer on the noble metal layer, a second mask layer on the first mask layer, and a patterned resist layer on the second mask layer; b) etching a portion of the second mask layer including employing a plasma of a mask etchant gas to break through and to remove the portion of the second mask layer from the first mask layer to expose part of the first mask layer and to produce the subsfrate supporting the barrier layer, the noble metal layer on the barrier layer, the first mask layer on the noble metal layer, a residual second mask layer on the first mask layer, and the patterned resist layer on the residual second mask layer; c) etching the exposed part of the first mask layer to expose part of the noble metal layer and to produce the substrate supporting the barrier layer, the noble metal layer on the barrier layer, a residual first mask layer on the noble metal layer, the residual second mask layer on the residual first mask layer, and the patterned resist layer on the residual second mask layer; d) removing the patterned resist layer from the residual second mask layer of step (c) to produce the substrate supporting the barrier layer, the noble metal layer on the barrier layer, and the residual first mask layer on the noble metal layer, and the residual second mask layer on the first residual mask layer; e) heating the substrate of step (d) to a temperature greater than about 150°C; f) etching the exposed part of the noble metal layer and said residual second mask layer of step (d) including employing a plasma of an etchant gas selected from the group consisting of a halogen containing gas, a noble gas, nitrogen, oxygen, and mixtures thereof, to produce the substrate supporting the barrier layer, an etched noble metal layer on the barrier layer, and the residual first mask layer on the etched noble metal layer; g) etching the barrier layer to remove a portion of the barrier layer from the subsfrate to produce the substrate supporting a residual barrier layer, the etched noble metal layer on the residual barrier layer, and the residual first mask layer on the etched noble metal; and h) removing the residual first mask layer from the etched noble metal layer to produce the substrate supporting the residual barrier layer, and the etched noble metal layer on the residual barrier layer. Preferably, the residual second mask layer in step(f) is removed and/or etched simultaneously with the step(f) etching and/or removal of the exposed part of the noble metal layer. The patterned resist layer may be removed from the residual second mask layer during the etching step (c). The etching step (h) additionally comprises etching into the substrate. The first mask layer comprises a compound selected from the group consisting of Si3N , BSG, PSG, BPSG, an organic polymer, a low dielectric constant material having a dielectric constant of less than about 3.0, and mixtures thereof. The second mask layer comprises a compound selected from the group consisting of CVD SiO2, TEOS, Si3N4, BSG, PSG, BPSG, SiC, and mixtures thereof. The first mask layer has a thickness ranging from about 3000A to about 8000A, and the second mask layer has a thickness ranging from about 500A to about 4000 A.
As previously indicated, etching of the platinum electrode layer to produce the platinum electrodes of the present invention is preferably performed in a high density plasma chamber. The platinum etching step employs a high density plasma of an etchant gas preferably consisting of, or consisting essentially of, a halogen gas (e.g., chlorine), a noble gas (i.e., argon) and HBr and/or BC13. The high density plasma chamber possesses a separate control for ion flux and a separate control for ion energy. As previously indicated, the ion density of the high density plasma in the high density plasma chamber is greater than about 109/cm3.
The high density plasma chamber for the method of manufacturing a semiconductor device and for the method of etching a platinum electrode layer disposed on a subsfrate includes a coil inductor and a wafer pedestal; and the platinum etching step in both of the methods is performed in the high density plasma chamber under the following previously mentioned process conditions:
Process Parameters
Etchant Gas Flow 50 to 500 seem
Halogen Gas (e.g., Cl ) about 10% to about 90% by vol.
Noble Gas (e.g., argon) about 5% to about 80% by vol.
HBr and or BC13 about 4% to about 25% by vol.
Pressure, mTorr 0.1 to 300 milliTorr
RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts
Temperature (° C) of Platinum Electrode Wafer about 150° to about 500° C Platinum Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of Coil Inductor 100 K to 300 MHz
RF Frequency of Wafer Pedestal 100 K to 300 MHz
In another embodiment of the present invention, the etching step may be performed in a low density (or high density) plasma chamber under the following process conditions:
Process Parameters
Etchant Gas Flow 35 to 900 seem
Halogen Gas (e.g., Cl2) 10% to 90% by vol.
Noble Gas (e.g., argon) 0% to 20% by vol.
Nitrogen gas 10% to 80% by vol.
HBr and/or BC13 and/or SiCL 0% to 25% by vol.
Pressure, mTorr 0.1 to 2000 milliTorr
RF Power (watts)* of Coil Inductor 0 to 5000 watts
RF Power (watts) of Wafer Pedestal 100 to 5000 watts
Platinum Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of
Coil Inductor 100Kto 300 MHz
RF Frequency of
Wafer Pedestal 100K to 300 MHz * If 0 watts is used for coil inductor, it implies an RIE chamber.
As further previously indicated, etching of the iridium electrode layer to produce the iridium electrodes of the present invention is performed in a high density plasma chamber. The iridium etching step employs a high density plasma or a low density plasma of an etchant gas preferably consisting of, or consisting essentially of, or consisting essentially of, a halogen gas (e.g., chlorine) and a noble gas (i.e., argon), more preferably a halogen gas (e.g., chlorine), a noble gas (i.e., argon) and oxygen or BC13, or oxygen (O2), a halogen gas (e.g., Cl2), a noble gas (e.g., Ar), and HCl and/or HBr. The high density plasma chamber possesses a separate control for ion flux and a separate control for ion energy. As previously indicated, the ion density of the high density plasma in the high density plasma chamber is greater than about 109/cm3.
The high density plasma chamber for the method of manufacturing a semiconductor device and for the method of etching an iridium elecfrode layer disposed on a subsfrate includes a coil inductor and a wafer pedestal; and the iridium etching step in both of the methods is performed in a high density plasma chamber under the following previously mentioned process conditions:
Process Parameters
Etchant Gas Flow 50 to 500 seem
Oxygen 5% to 20% by volume
Halogen Gas (e.g., Cl2) about 10% to about 60%) by vol.
Noble Gas (e.g., argon) about 30%) to about 80% by vol.
HBr and/or HCl about 5% to about 20%) by vol.
Pressure, mTorr 0.1 to 300 milliTorr
RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts
Temperature (°C) of
Iridium Electrode Wafer about 150° to about 500°C
Iridium Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of Coil Inductor 100 Kto 300 MHz
RF Frequency of Wafer Pedestal 100 Kto 300 MHz
The present invention also provides a method of processing a layer on a substrate comprising the steps of: a) providing a substrate; b) disposing the substrate in a reactor chamber comprising a dielectric window including a deposit-receiving surface having a peak-to- valley roughness height with an average height value of greater than about 1000 A; c) introducing a processing gas into the reactor chamber of step (b); and d) introducing processing power into the reactor chamber of step (b) to process a layer on the substrate in a plasma of the processing gas.
The present invention further provides a dielectric member comprising a dielectric structure including a surface finish having a peak-to-valley roughness height with an average height value of greater than about 1000 A. A pedestal assembly is disposed in the processing zone. The chamber assembly also comprises a processing power source; a processing gas-introducing assembly, engaged to the chamber wall, for introducing a processing gas into the processing zone of the chamber wall; and a processing power- transmitting member connected to the processing power source for transmitting power into the processing zone to aid in sustaining a plasma from a processing gas within the processing zone of the processing chamber wall.
The present invention yet also further broadly provides a semiconductor device, more specifically a capacitance structure, comprising a subsfrate, and at least two noble metal electrodes (e.g., platinum elecfrodes or iridium elecfrodes) supported by the substrate. The electrodes have a profile equal to or greater than about 80°, such as equal to or greater than about 85°, preferably equal to or greater than about 87°, more preferably equal to or greater than about 88.5°. The electrodes are separated by a distance or space having a dimension equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm. Each of the electrodes include a dimension having a value equal to or less than about 1.0 μm, preferably equal to or less than about 0.6 μm, more preferably equal to or less than about 0.35 μm, most preferably equal to or less than about 0.3 μm. More preferably, each of the elecfrodes have a width equal to or less than about 0.35μm, preferably equal to or less than about 0.3 μm, a length equal to or less than about 1.0 μm, preferably equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm.
In another preferred embodiment of the present invention, there is provided a method of etching an iridium (i.e., a noble metal layer) layer disposed on a substrate comprising the steps of: a) providing a substrate supporting an iridium layer; b) heating the subsfrate of step (a) of a temperature greater than about 150°C; and c) etching the iridium layer including employing a plasma of an etchant gas (i.e., a low density or high density plasma of an etchant gas) comprising a halogen containing gas (e.g., chlorine) and a noble gas (e.g., argon) to produce the subsfrate supporting at least one etched iridium layer. In one embodiment of the invention, the etchant gas additionally comprises a gas selected from the group consisting of O2 and BC13. In another embodiment of the invention, the etchant gas additionally comprises a gas selected from the group consisting of O , HCl, HBr, and mixtures thereof. The halogen containing gas comprises or consists essentially of chlorine and the noble gas comprises or consists essentially of argon. Optionally, the etchant gas comprises or consists essentially of chlorine, argon and O2. The iridium layer of step (a) additionally comprises a mask layer (e.g., a TiN or Ti mask layer) disposed on a selected part of the iridium layer to selectively protect the iridium layer during the etching step (c).
The present invention also provides a method of etching an iridium electrode layer disposed on a substrate comprising the steps of: a) providing a substrate supporting an iridium electrode layer, a protective layer on the iridium electrode layer, a Ti mask layer on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the Ti mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the Ti mask layer from the iridium elecfrode layer to expose part of the protective layer and to produce the subsfrate supporting the iridium elecfrode layer, the protective layer on the iridium electrode layer, a residual Ti mask layer on the protective layer, and the patterned resist layer on the residual Ti mask layer; c) removing the patterned resist layer from the residual Ti mask layer of step (b) to produce the substrate supporting the iridium electrode layer, the protective layer on the iridium elecfrode layer, and the residual mask layer on the protective layer; d) heating the substrate of step (c) to a temperature greater than about 150°C; e) etching the exposed part of the protective layer to expose part of the iridium electrode layer and to produce the substrate supporting the iridium electrode layer, a residual protective layer on the iridium electrode layer, and the residual mask layer on the residual protective layer; and f) etching the exposed part of the iridium electrode layer of step (e) including employing a plasma (e.g., a high density or low density plasma) of an etchant gas comprising oxygen, chlorine and argon to produce the substrate supporting an etched iridium electrode layer having the residual protective layer on the etched iridium electrode layer, and the residual Ti mask layer on the residual protective layer.
The present invention further also provides a method of etching an iridium electrode layer disposed on a substrate comprising the steps of: a) providing a subsfrate supporting an iridium electrode layer, a protective layer on the iridium electrode layer, a mask layer on the protective layer, and a patterned resist layer on the mask layer; b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the iridium electrode layer to expose part of the protective layer and to produce the substrate supporting the iridium electrode layer, the protective layer on the iridium electrode layer, a residual mask layer on the protective layer, and the patterned resist layer on the residual mask layer; c) etching the exposed part of the protective layer to expose part of the iridium electrode layer and to produce the substrate supporting the iridium elecfrode layer, a residual protective layer on the iridium electrode layer, the residual mask layer on the residual protective layer, and the patterned resist layer on the residual mask layer; d) removing the patterned resist layer from the residual mask layer of step (c) to produce the substrate supporting the iridium electrode layer, the residual protective layer on the iridium electrode layer, and the residual mask layer on the residual protective layer; e) heating the substrate of step (d) to a temperature greater than about 150°C ; and f) etching the exposed part of the iridium electrode layer of step (d) including employing a high density plasma (e.g., a low density or high density plasma) of an etchant gas comprising chlorine and a noble gas to produce the subsfrate supporting an etched iridium elecfrode layer having the residual protective layer on the etched iridium electrode layer, and the residual mask layer on the residual protective layer. The etchant gas of step (f) additionally comprises a gas selected from the group consisting of oxygen, HCl, HBr and mixtures thereof. More specifically the etchant gas comprises, preferably consists of or consists essentially of, oxygen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, HCl and mixtures thereof. The etchant gas more specifically comprises, or consists of or consists essentially of, from about 5%> by volume to about 20% by volume oxygen, from about 10% by volume to about 60%> by volume of the halogen gas (i.e., chlorine) and from about 30% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or HCl; preferably from about 5% by volume to about 15% by volume oxygen, from about 20% by volume to about 50% by volume of the halogen gas (i.e., chlorine) and from about 40% by volume to about 70% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15%> by volume of HBr and/or HCl; and more preferably from about 5% by volume to about 10% by volume oxygen, from about 20% by volume to about 35% by volume of the halogen gas (i.e., chlorine) and from about 40%> by volume to about 60%) by volume of the noble gas (i.e., argon) and from about 5% by volume to about 10% by volume of HBr and/or HCl. The etchant gas flow rate ranges from about 50 seem to about 500 seem.
When the etchant gases are a mixture of oxygen, the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or BC13, the process parameters for etching an elecfrode layer in a suitable inductively coupled plasma reactor fall into the ranges as Hsted below on the basis of rates of the gases, including oxygen, the halogen gas(es) (i.e., Cl2), the noble gas(ses) (i.e., Ar), and HBr and/or HCl.
Process Broad Preferred Optimum
Gas Flow, seem
O2 10 to 60 10 to 40 15 to 30
Cl2 30 to 100 30 to 70 50 to 70
Ar 50 to 250 100 to 200 100 to 150
HBr and/or HCl 10 to 60 10 to 40 15 to 30
Pressure, mT 0.1 to 300 10 to 100 10 to 40
RF Power of Coil 100 to 5000 650 to 2000 750 to 1000
Inductor (Watts)
RF Power of Wafer 50 to 3000 100 to 1000 150 to 600
Pedestal (Watts)
Temperature of about 150 to about 200 to 400 250 to 350
Wafer (°C) 500
Etch Rate (A/min) 200 to 6000 500 to 3000 500 to 2000
RF Frequency of 100 K to 300 MHz 400 K to 20 MHz 2 to 13.5 MHz
Coil Inductor
RF Frequency of 100 Kto 300 MHz 400 K to 20 MHz 400 Kto 13.5 MHz
Wafer Pedestal
The foregoing provisions along with various ancillary provisions and features which will become apparent to those skilled in the art as the following description proceeds, are attained by the practice of the present invention, a prefened embodiment thereof shown with reference to the accompanying drawings, by way of example only, wherein: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a side elevational view of a semiconductor wafer having a semiconductor substrate, a banier layer disposed on the semiconductor substrate, a platinum elecfrode layer disposed on the barrier layer, a mask layer disposed on the platinum elecfrode layer, and a patterned resist disposed on the mask layer;
Fig. 2 is a side elevational view of the semiconductor wafer of Fig. 1 additionally including a protective layer disposed on the platinum electrode layer between the mask layer and the platinum elecfrode layer;
Fig. 3 is a vertical sectional view of a prior art plasma processing apparatus including a plasma etching reactor with an electromagnetic unit for enhancing a plasma;
Fig. 4 is a diagram of a flux produced by a magnetic field and illustrated as rotating around a center axis;
Fig. 5 is a side elevational view of the semiconductor wafer of Fig. 1 after etching and removing a portion of the mask layer from the surface of the platinum elecfrode layer to expose the platinum elecfrode layer;
Fig. 6 is a side elevational view of the semiconductor wafer of Fig. 2 after etching and removing a portion of the mask layer from the surface of the protective layer to expose the protective layer; Fig. 7 is a side elevational view of the semiconductor wafer of Fig. 5 after the patterned resist layer has been removed from a portion of the mask layer with the removed patterned resist layer being represented as broken lines;
Fig. 8 is a side elevational view of the semiconductor wafer of Fig. 6 after etching and removing a portion of the protective layer off of the surface of the platinum layer, and after removing the patterned resist layer from a portion of the mask layer with the removed patterned resist layer being represented as broken lines;
Fig. 9 is a side elevational view of the semiconductor wafer of Fig. 7 after the platinum electrode layer has been etched to produce an etched platinum electrode layer; Fig. 10 is a side elevational view of the semiconductor wafer of Fig. 8 after the platinum elecfrode layer has been etched to produce an etched platinum elecfrode layer;
Fig. 11 is a side elevational view of the semiconductor wafer of Fig. 7 after the platinum elecfrode layer has been etched to produce an etched platinum elecfrode layer with a residual mask layer on top thereof;
Fig. 12 is a side elevational view of the semiconductor wafer of Fig. 8 after the platinum electrode layer has been etched to produce an etched platinum electrode layer with a residual mask layer on top of the residual protective layer; Fig. 13 is a side elevational view of the semiconductor wafer of Fig. 11 with the residual mask layer removed from the surface of the etched platinum elecfrode layer;
Fig. 14 is a side elevational view of the semiconductor wafer of Fig. 12 with the residual mask layer and the residual protective layer removed from the surface of the etched platinum electrode layer;
Fig. 15 is a side elevational view of semiconductor wafer of Fig. 11 after the residual mask layer has been removed from the surface of the etched platinum elecfrode layer and with the banier layer having been etched;
Fig. 16 is a side elevational view of semiconductor wafer of Fig. 12 after the residual mask layer and the residual protective layer have been removed from the surface of the etched platinum electrode layer and with the barrier layer having been etched;
Fig. 17 is a simplified cut-away view of an inductively coupled RF plasma reactor which may be employed in etching the platinum elecfrode layer to produce a semiconductor device;
Fig. 18 is a simplified cut-away view of another inductively coupled RF plasma reactor which may be employed in etching the platinum elecfrode layer to produce a semiconductor device;
Fig. 19 is a picture showing an elevational view of a test semiconductor wafer for Example I after the platinum elecfrode layer was etched in accordance with the process conditions listed in Example I; Fig. 20 is a picture showing an elevational view of the test semiconductor wafer of Fig. 19 after the oxide mask was removed;
Fig. 21 is a drawing representing the elevational view in the picture of Fig.
19 » wwiitthh 1 the respective parts identified by a reference numeral;
Fig. 22 is a drawing representing the elevational view in the picture of Fig.
20 ) with the respective parts identified by a reference numeral;
Fig. 23 is a picture showing an elevational view of a test semiconductor wafer for Example II after the platinum elecfrode layer was etched in accordance with the process conditions listed in Example II; Fig. 24 is a drawing representing the elevational view on the picture of
Fig. 23 with the respective parts identified by a reference numeral;
Fig. 25 is a side elevational view of a semiconductor wafer having a semiconductor substrate, an etch-stop layer disposed on the semiconductor substrate, a barrier layer disposed on the etch-stop layer, a platinum elecfrode layer disposed on the barrier layer, a protective layer disposed on the platinum electrode layer and a patterned mask layer disposed on the protective layer;
Fig. 26 is a schematic diagram illustrating masking and etching sequences for another embodiment of the invention;
Fig. 27 is a schematic diagram illustrating masking and etching sequences for a further embodiment of the invention;
Fig. 28 is a schematic diagram illustrating masking and etching sequences for yet another embodiment of the invention;
Fig. 29 is a schematic diagram illustrating masking and etching sequences for yet a further embodiment of the invention; Fig. 30 is a picture show the test semiconductor wafer of Example III after the TEOS mask layer was removed;
Fig. 31 is a picture of an elevational view of the test semiconductor wafer of Example IV after the SiLK® brand mask layer of the test semiconductor was etched in the DPS™ brand chamber; Fig. 32 is a picture of an elevational view of the test semiconductor wafer of Example IN after the platinum layer and the TiΝ (i.e., a barrier layer) was etched in the DPS™ brand chamber;
Fig. 33 is a picture of an elevational view of the test semiconductor wafer of Example IN after the SiLK® brand mask layer was removed or stripped from the etched platinum layer in an ASP chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus;
Fig. 34 is a top plan view picture of the etched platinum layer of Fig. 33;
Fig. 35 is a partial exploded sectional view of the inductively coupled RF plasma reactor of Fig. 17 illustrating the dome-shaped dielectric ceiling;
Fig. 36 is a partial side elevational view of a surface finish of a deposit- receiving surface of a dielectric member (i.e., a dielecfric window or the dome-shaped dielecfric ceiling);
Fig. 37 is a picture showing an elevational view of a test semiconductor wafer for Example N after the platinum elecfrode layer was etched in accordance with the process conditions listed in Example N;
Fig. 38 is a drawing representing the elevational view of the picture of Fig. 37 with the respective parts identified by reference numerals;
Fig. 39 is a picture showing an elevational view of a test semiconductor wafer for Example NI after the platinum elecfrode layer was etched in accordance with the process conditions listed in Example VI;
Fig. 40 is a drawing partially representing the elevational view of the picture of Fig. 39 with the respective parts identified by reference numerals;
Fig. 41 is a partial perspective view of a dome-shaped dielectric ceiling having an inside concave surface;
Fig. 42 is a partial sectional view of the dome-shaped dielectric ceiling of Fig. 41 after its associated inside concave surface has received a deposit of by-product materials in accordance with Example VII;
Fig. 43 is a partial sectional view of the dome-shaped dielecfric ceiling of Fig. 41 after its associated inside concave surface has received a deposit of by-product materials in accordance with Example VIII; Fig.44 is a partial exploded sectional view of a dome-shaped dielectric ceiling having a roughened inside concave surface that has received a deposit of byproduct materials in accordance with Example IX;
Fig. 45 is a picture showing an elevational view of a test semiconductor wafer for Example X after an iridium electrode layer was etched in accordance with the process conditions listed in Example X;
Fig. 46 is a drawing representing the elevational view in the picture of Fig. 45 with respective parts identified by a reference numeral;
Fig. 47 is a picture showing an elevational view of a test semiconductor wafer for Example XI after an iridium elecfrode layer was etched in accordance with the process conditions listed in Example XI; and
Fig. 48 is a drawing representing the elevational view in the picture of Fig. 47 with the respective parts identified by a reference numeral.
DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION
Referring in detail now to the drawings wherein similar parts of the present invention are identified by like reference numerals, there is seen in Fig. 1 a wafer, generally illustrated as 10, having a semiconductor subsfrate, generally illustrated as 12. The semiconductor substrate 12 preferably comprises silicon dioxide (SiO2) and includes regions of circuit elements which do not appear in the drawings, but are well known to those skilled in the art. In another embodiment of the present invention, the semiconductor substrate 12 comprises a compound selected from the group consisting of tetraethylorthosilicate (TEOS), silicon dioxide, and mixtures thereof. A barrier layer 14 is disposed over the semiconductor substrate 12 and a layer (e.g., an elecfrical conductive layer, such as a noble metal layer [or an oxide or alloy of same] including a platinum layer or an iridium layer, etc.), generally illustrated as 15, is disposed over the barrier layer 14. In another embodiment of the present invention as best shown in Fig. 25, an etch-stop layer 17 is disposed on the semiconductor substrate 12 between the semiconductor substrate 12 and the banier layer 14. The layer 15 is preferably an elecfrode layer 16 as shown in Fig. 1. Because the elecfrode layer 16 is a prefened layer 15, the remaining description of the present invention will use only the term "electrode layer 16" in describing the present invention. However, it is to be understood that wherever "elecfrode layer 16" is stated hereinafter, it is to also have the equivalence of "layer 15" for purposes of the present invention. It is also to be understood that in one prefened embodiment of the present invention "elecfrode layer 16" may be a "platinum elecfrode layer 16" or an "iridium elecfrode layer 16," unless otherwise indicated. Thus, whenever "platinum elecfrode layer 16" is stated or mentioned hereinafter for a prefened embodiment of the invention, it is to be understood that the electrode layer 16 includes platinum and the prefened embodiment of the present invention relates to etching platinum to produce the desired features of the present invention as set forth hereinafter. Similarly, whenever "iridium elecfrode layer 16" is stated or mentioned hereinafter for another prefened embodiment of the present invention, it is to be understood that the elecfrode layer 16 includes iridium and the prefened embodiment of the present invention relates to etching iridium to produce the desired features of the present invention as set forth hereinafter. Because the elecfrode layer 16 easily diffuses or reacts with certain elements (e.g., a poly-Si plug) within the semiconductor substrate 12, the barrier layer 14 is required between the electrode layer 16 and the semiconductor subsfrate 12. The banier layer 14 also functions as an adhesive for coupling the semiconductor subsfrate 12 to the electrode layer 16. A mask 18 is disposed over the elecfrode layer 16 and a patterned resist (i.e., a photoresist), generally illustrated as 20, is selectively positioned on the mask layer 18 as best shown in Fig. 1. As best shown in Fig. 1, the patterned resist 20 includes a plurality of resist members 20a, 20b, 20c, and 20d. In another prefened embodiment of the invention as shown in Fig. 2, a protective layer 22 is disposed between the electrode layer 16 and the mask layer 18.
1
The barrier layer 14 may be any suitable layer which is capable of dually functioning as an adhesive and a diffusion barrier to the electrode layer 16. The barrier layer 14 may be of any suitable thickness. Preferably, the barrier layer 14 comprises Ta and/or TaN and/or TaSiN and/or WNX and/or titanium and/or a titanium alloy, such as TiN and TiSiN, and possesses a thickness ranging from about 50 Angstroms to about 600 Angsfroms, more preferably from about 200 Angsfroms to about 400 Angsfroms, most preferably about 300 Angsfroms. In another embodiment of the present invention, the barrier layer 14 comprises BST (i.e., barium titanate (BaTiO3) and strontium titanate (SrTiO3)). Alternatively, the barrier layer 14 may comprise PZT (Pb(Zrι-xTix)03) and SBT (SrBi2Ti209). In this alternate prefened embodiment of the invention, the banier layer 14 functions as a dielecfric for a capacitor. The banier layer 14 is preferably disposed on the semiconductor substrate 12 by the RF magnetron sputtering method.
The etch-stop layer 17 as best shown in Fig. 25 may be any suitable layer which is capable of functioning as an adhesive, and, optionally, in conjunction with barrier layer 14 being a diffiision barrier to the elecfrode layer 16. Etch-stop layer 17 may be of any suitable thickness. Preferably, the etch-stop layer 17 comprises a compound selected from the group consisting of silicon nitride (Si3N4), titanium dioxide (TiO2), ruthenium dioxide (RuO2), iridium dioxide (IrO2), and possesses a thickness ranging from about 50 Angsfroms to about 1000 Angsfroms, more preferably from about 200 Angsfroms to about 700 Angstroms, most preferably from about 300 Angsfroms to about 500 Angsfroms, e.g., about 400 Angsfroms. The etch-stop layer 17 is preferably disposed on the semiconductor subsfrate 12 by chemical vapor deposition.
The elecfrode layer 16 may be any suitable one or more noble metal (or oxide or alloy of same), such as platinum or iridium as one prefened elecfrode material because they are inert to oxidation which tends to occur in the subsequent high temperature processes of depositing the high dielectric constant fenoelectric materials. The electrode layer 16 comprising platinum or iridium is also used as the electrode material because platinum and iridium are good electric conductors. The thickness of the electrode layer 16 would depend upon the end use of the semiconductor or capacitance device which is to contain the electrode layer 16. Typically, the thickness of the elecfrode layer 16 ranges from about 500 Angstroms to about 5000 Angstroms, more preferably from about 1000 Angstroms to about 4000 Angstroms, most preferably from about 2000 Angstroms to about 3000 Angstroms, e.g., about 2000 Angstroms. The electrode layer 16 is preferably disposed on the banier layer 14 by the RF magnetron sputtering method. The mask layer 18 may be any suitable insulation or metallic material that is capable of being etched in accordance with the procedure described hereinafter such that all traces of the mask layer 18 are essentially removed from the surface platinum electrode layer 16 except that portion (identified as "18a," "18b," "18c," and "18d" below) of the mask layer 18 remaining under the patterned resist 20. The mask layer 18 may also be of any suitable thickness. Preferably, the mask layer 18 comprises silicon dioxide (SiO2) and/or silicon nitride (Si3N4) or any other suitable dielectric material. The thickness of the mask layer 18 would depend on constituency of the mask layer 18, as well as the constituency of the layer 15 or electrode layer 16. A prefened thickness for the mask layer 18 ranges from about 1,000 Angsfroms to about 15,000 Angstroms, more preferably from about 3,000 Angsfroms to about 12,000 Angsfroms, most preferably from about 6,000 Angstroms to about 9,000 Angsfroms, e.g., about 7,000 Angstroms. The ratio of the thickness of the mask layer 18 to the thickness of the layer 15, or the electrode layer 16, ranges from about 0.2 to about 5.0, preferably from about 0.5 to about 4.0, more preferably from about 1.0 to about 3.0. In another embodiment of the present invention, the mask layer 18 comprises a compound selected from the group consisting of organic polymers, chemical vapor deposited (CVD) Si02, doped CVD Si02 tefraethyorthosilicate (TEOS), CVD Si3N and mixtures thereof. The organic polymer is a high temperature polymer capable of standing up to 400°C, such as amorphous carbon, polyamide, parylene and aromatic hydrocarbons. A suitable organic polymer has been determined to be an organic polymer sold by Dow Chemical Co. of Midland, MI, under the registered trademark SiLK®. The doped CVD Si02 is a CVD Si02 film having doping gases added to the CVD reactant gases, such as adding phosphorus dopant to form phosphosilicate glass (PSG), adding boron dopant to form borosilicate glass (BSG), or adding both phosphorus and boron dopants to form borophosphosilicate (BGSG). The mask layer 18 is preferably disposed on the platinum elecfrode layer 16 by chemical vapor deposition. In another embodiment of the present invention, the mask layer 18 comprises
Ti and/or TiN, preferably TiN. As will be further explained below, it has been discovered that etching of an iridium electrode layer 16 superimposed with a mask layer 18 comprising TiN, and in a high density plasma of an etchant gas comprising oxygen, a halogen gas (e.g., Cl2), and a noble gas (e.g., argon), etched iridium electrodes are produced having an iridium profile where the angle _ of the associated sidewalls with respect to a horizontal plane is equal to greater than about 80 degrees. A clean iridium surface is produced after removal of the mask layer 18 with no fence or veil formation. It has been further discovered that during etching of the iridium elecfrode layer 16 in a high density plasma of the etchant gas having a gas chemistry of O2/halogen gas(es)/noble gas(es), with the iridium electrode layer 16 supporting the mask layer 18 comprising TiN, the etch selectivity of iridium to the TiN is greater than about 8.0, preferably greater than about 10.0. It is to be understood that the spirit and scope of the present invention includes etching of a platinum electrode layer 16, or any other noble metal elecfrode layer 16, while supporting a mask layer 18 comprising TiN, with the etching of the platinum electrode layer 16 being conducted in a high density plasma of an etchant gas comprising oxygen, a halogen gas (e.g., Cl2), and a noble gas (e.g., argon). The thickness for the mask layer 18 for this embodiment of the invention ranges from about 500 Angstroms to about 9000 Angstroms, preferably from about 2000 Angsfroms to about 7000 Angstroms, more preferably about 3000 Angstroms. The ratio of the thickness of the mask layer 18 to the thickness of the layer 15, or the electrode layer 16 (e.g. iridium or platinum elecfrode layer 16), ranges from about 0.2 to about 5.0, preferably from about 0.5 to about 4.0, more preferably from about 1.0 to about 3.0. The mask layer 18 is preferably disposed on the electrode layer 16 by chemical vapor deposition.
The patterned resist 20 (i.e., the photoresist 20, including resist members 20a, 20b, 20c and 20d ) may be any suitable layer of material(s) that is capable of protecting any underlying material (e.g., the mask layer 18) from being etched during the etching process of the present invention. Suitable materials for the patterned resist 20 include resist systems consisting of novolac resin and a photoactive dissolution inhibitor (all based on Sύss's discovery). Other suitable materials for the resist 20 are listed in an article from the July 1996 edition of Solid State Technology entitled "Deep-UV Resists: Evolution and Status" by Hiroshi Ito. The patterned resist 20 may have any suitable thickness; preferably, the thickness of the patterned resist 20 ranges from about 0.3 μm to about 1.40 μm, more preferably from about 0.5 m to about 1.2 μm, most preferably about 0.8 μm. The patterned resist 20 is preferably disposed on the mask layer 18 by the spin coating method. The protective layer 22 in the embodiment of the invention depicted in
Fig. 2 is for protecting the corners (identified as "16g" below) of an etched elecfrode layer (generally identified as "16e" below) during the overetching process of the present invention. Another purpose of the protective layer 22 is for providing good adhesion to the mask layer 18 and the elecfrode layer 16. The protective layer 22 may comprise any suitable materials or chemicals, such as titanium and/or titanium nitride etc., and may be conveniently disposed on the surface of the electrode layer 16, such as by the RF magnetron sputtering method. The thickness of the protective layer 22 may be any suitable thickness, preferably ranging from about 50 Angsfroms to about 1000 Angsfroms, more preferably ranging from about 100 Angsfroms to about 600 Angsfroms, most preferably from about 100 Angstroms to about 400 Angsfroms, e.g., about 300 Angsfroms.
In order to form or produce a semiconductor or capacitance device from the multilayered structure of Fig. 1 or Fig. 2 or Fig. 25, the multilayered structure is initially placed in a suitable plasma processing apparatus to break through and remove or etch away from the surface of the electrode layer 16 the mask layer 18, except those mask layers 18a, 18b, 18c and 18d that are respectively below the resist members 20a, 20b, 20c and 20d, as best shown in Fig. 5, or as best shown in Fig. 6 if the embodiment of the invention depicted in Fig. 2 or Fig. 25 is being employed.
A suitable prior art plasma processing apparatus is shown in Fig. 3 and described in U.S. Patent No. 5,188,704 to Babie et al, fully incorporated herein by reference thereto as if repeated verbatim immediately hereinafter. The plasma process apparatus of Fig. 3 comprises a plasma reactor, generally illustrated as 30 and including walls, generally illustrated as 31 for forming and housing a reactor chamber 32 wherein a plasma 33 of neutral (n) particles, positive (+) particles, and negative (-) particles are found. Walls 31 include cylindrical wall 54 and cover 56. Plasma processing gases are introduced via inlets 34 into reactor chamber 32. Plasma etching gases are introduced into chamber 32 through inlets 44-44. A water cooled cathode 36 is connected to an RF power supply 38 at 13.56 MHz. An anode 39 is connected to the walls 31 which are grounded by line 40. Helium gas is supplied through passageway 50 through cathode 36 to the space beneath wafer 10 which is supported peripherally by lip seal 52 so that the helium gas cools the wafer 10. The wafer 10 is supported by a wafer support 46 that includes a plurality of clamps (not shown) which hold down the upper surface of wafer 10 at its periphery, as is well known to those skilled in the art. A pair of helmholtz configured elecfromagnetic coils 42 and 43 provide north and south poles within the chamber 32 and are disposed at opposite ends of the lateral cylindrical wall 54 and the walls 31. The elecfromagnetic coils 42 and 43 provide a fransverse magnetic field with the north and south poles at the left and right providing a horizontal magnetic field axis parallel to the surface of the wafer 10. The transverse magnetic field is applied to slow the vertical velocity of the electrons which are accelerated radially by the magnetic field as they move towards the wafer 10. Accordingly, the quantity of electrons in the plasma 33 is increased by means of the fransverse magnetic field and the plasma 33 is enhanced as is well known to these skilled in the art.
The electromagnetic coils 42 and 43 which provide the magnetic field are independently controlled to produce a field intensity orientation which is uniform. The field can be stepped angularly around the wafer 10 by rotating the energization of the elecfromagnetic coils 42 and 43, sequentially. The fransverse magnetic field provided by the elecfromagnetic coils 42 and 43 is directed parallel to the surface of the wafer 10 being treated by the plasma 33, and the cathode 36 of the plasma reactor 30 increases ionization efficiently of the electrons in the plasma 33. This provides the ability to decrease the potential drop across the sheath of the cathode 36 and to increase the ion cunent flux present on the surface of the wafer 10, thereby permitting higher rates of etching without requiring higher ion energies to achieve the result otherwise.
The prefened magnetic source employed to achieve magnetically enhanced reactive ion etcher (MERIE) used in practicing the present invention is a variable rotational field provided by the elecfromagnetic coils 42 and 43 ananged in a Helmholtz configuration. The elecfromagnetic coils 42 and 43 are driven by 3 -phase AC cunents. The magnetic field with Flux B is parallel to the wafer 10, and perpendicular to the elecfrical field as shown in Fig. 4. Refening to Fig. 4, the vector of the magnetic field H which produces flux B is rotating around the center axis of the elecfrical field by varying the phases of cunent flowing through the elecfromagnetic coils 42 and 43 at a typical rotational frequency of 0.01 to 1 Hz, particularly at 0.5 Hz. The strength of the magnetic flux B typically varies from 0 Gauss to about 150 Gauss and is determined by the quantities of the cunents supplied to the elecfromagnetic coils 42 and 43. While Fig. 3 illustrates one plasma processing apparatus that is suitable for removing the mask layer 18 (except mask layers 18a, 18b, 18c and 18d), it is to be understood that other plasma etchers may be employed, such as electron cyclotron resonance (ECR), helicon resonance or inductively coupled plasma (ICP), triode etchers, etc.
The plasma 33 may employ any suitable etchant gas to break through (i.e., to clean and etch away) the mask layer 18 except those mask layers 18a, 18b, 18c and 18d that are respectively below the resist members 20a, 20b, 20c and 20d, as best shown in Figs. 5 and 6. For example, if the mask layer 18 contains silicon oxide, suitable etchant gas(es) may be selected from the group consisting of fluorine-containing gases (e.g., CHF3, SF6, C2F6, NF3, etc.), bromine-containing gases (e.g., HBr, etc.), chlorine- containing gases (e.g., CHC13, etc.), rare or noble gases (e.g., argon, etc.), and mixtures thereof. Preferably, and in one embodiment of the present invention, the etchant does not include an oxidant, such as oxygen, since the purpose of this step is to remove the mask layer 18 (except those mask layers 18a, 18b, 18c and 18d which are respectively protected by resist members 20a, 20b, 20c and 20d) and not to remove the patterned resist 20. More preferably, the etchant gas comprises from about 20% by volume to about 40% by volume CHF3 and from about 60% by volume to about 80% by volume argon. The prefened reactor conditions for a suitable plasma processing apparatus (such as the plasma processing apparatus of Fig. 3) in removing the mask layer 18 (except mask layers 18a, 18b, 18c and 18d) are as follows:
Pressure 10-150 mTon
RF Power 500-1500 watts
Rotational Magnetic Field 25-70 Gauss
Temperature of Wafer 25-100°C Mask Layer 18 Etch Rate 2000- 10,000 Angstroms/min
The selectivity of mask layer 18 to patterned resist 20 is better than 3:1, depending on the materials employed for the mask layer 18 and the patterned resist 20.
More generally, the process parameters for removing the mask layer 18 in a suitable plasma process apparatus (such as the plasma processing apparatus of Fig. 3) fall into ranges as listed in the following Table III and based on flow rates of the gases CHF3 and Ar also listed in the following Table HI:
TABLE in
Process Broad Preferred
Gas Flow, seem
CHFj 10 to 50 (20 to 40% by vol.) 20 to 40
Ar 50 to 90 (60 to 80% by vol.) 60 to 80
Pressure, mT 10 to 250 10 to 150
13.56 MHz
RF Power (Watts) 500 to 2500 500 to 1500
Temperature (°C) of Wafer 10 to 120 25 to 100
Magnetic Field Gauss 10 to 120 25 to 70
In another prefened embodiment of the invention, when the mask layer 18 comprises Ti and/or TiN (preferably TiN), suitable etchant gas(es) to break through (i.e., to clean and etch away) the Ti TiN-containing mask layer 18 except for those mask layers 18a, 18b, 18c and 18d that are respectively below the resist numbers 20a, 20b, 20c and 20d, as best shown Figs. 5 and 6, may be selected from the group consisting of a noble gas (e.g., argon), a halogen (e.g., Cl2), and a gas selected from the group consisting of HBr, BC13, and mixtures thereof. Preferably, the etchant gas comprises from about 10% by volume to about 30% by volume argon, from about 20% by volume to about 60% by volume chlorine, and from about 20% by volume to about 60% by volume HBr and/or BC13. The prefened reactor conditions for a suitable plasma processing apparatus (such as the plasma processing apparatus of Fig. 3) in removing the mask layer 18 (except mask layer 18a, 18b, 18c and 18d) comprising Ti and/or TiN are as follows: Pressure 10-150 mTon
RF Power 500-1500 watts
Rotational Magnetic Field 25-70 Gauss
Temperature of Wafer 25-100°C
Mask Layer 18 Etch Rate 2000-10,000 Angstroms/min
The selectivity of the Ti/TiN-containing mask layer 18 to patterned resist 20 is better than 3:1, depending on the materials employed for the patterned resist 20. More generally, the process parameters for removing the Ti/TiN-containing mask layer 18 in a suitable plasma process apparatus (such as the plasma processing apparatus of Fig. 3) fall into ranges as listed in the following Table IV and based on flow rates of the gases argon, chlorine and HBr and/or BC13 also listed in the following Table IV:
TABLE IV
Process Broad Preferred
Gas Flow, seem
Argon 10 to 50 (10 to 30% by vol.) 30 to 40
Chlorine 30 to 100 (20 to 60% by vol.) 60 to 80
HBr and/or BC13 30 to 100 (20 to 60% by vol.) 50 to 70
Pressure, mT 10 to 250 10 to 150
13.56 MHz
RF Power (Watts) 500 to 2500 500 to 1500
Temperature (°C) of Wafer 10 to 120 25 to 100
Magnetic Field Gauss 10 to 120 25 to 70
For the embodiment of the invention depicted in Fig. 2 wherein the protective layer 22 is disposed on the elecfrode layer 16 between the mask layer 18 and the elecfrode layer 16, the protective layer 22 has to be removed or etched after removal of the mask layer 18 in order to expose the platinum elecfrode layer 16. The protective layer 22 may be etched and removed by any suitable manner and/or with any suitable plasma processing apparatus (such as with the plasma processing apparatus of Fig. 3) including the plasma 33 employing a suitable etchant gas to break through and etch away the protective layer 22 except those protective layers 22a, 22b, 22c and 22d (see Figs. 6 and 8) immediately below mask layers 18a, 18b, 18c and 18d, respectively. For example, if TiN is used as the protective layer 22, suitable etchant gas(es) may be selected from the group consisting of Cl2, HBr, BC13, noble gases (e.g., Ar), and mixtures thereof. Preferably and in one embodiment of the present invention, the etchant gas for breaking through and etching away the protective layer 22, except protective layers 22a, 22b, 22c and 22d, comprises from about 20% by volume to about 60% by volume Cl2, from about 20% by volume to about 60% by volume HBr and/or BC13, and from about 10% by volume to about 30% by volume of a noble gas which is preferably Ar. Suitable reactor conditions for a suitable plasma processing apparatus (such as the plasma processing apparatus of Fig. 3) to remove the protective layer 22 (except protective layers 22a, 22b, 22c and 22d) may be the same as those previously stated reactor conditions for the removal of the mask layer 18 (except mask layers 18a, 18b, 18c and 18d). It is to be understood that other plasma etchers may be employed to remove the protective layer 20, such as ECR, ICP, Helicon Resonance, etc. As will be further explained below, the protective layers 22a, 22b, 22c and 22d are for protecting the corners (identified as "16g" below) of an etched elecfrode layer (generally identified as "16e" below) during the etching process of the present invention. It is believed that the protective layers 22a, 22b, 22c and 22d not only protect the corners of an etched platinum electrode layer during the etching process, but also assist in maintaining an existing profile and/or improves a profile (e.g., an etched platinum or iridium profile).
In another embodiment of the present invention, the protective layer 22 (except protective layers 22a, 22b, 22c and 22d) may be etched and removed by the high temperatures and etchant gases employed in the noble metal-etching process (e.g., platinum-etching process) of the present invention. More specifically and as will be further explained below, because the elecfrode layer 16 (e.g., platinum elecfrode layer 16) is preferably etched under the following process conditions in a high density plasma chamber containing a high density inductively coupled plasma:
Process Parameters
Etchant Gas flow 50 to 500 seem
Halogen Gas (e.g., Cl2) 20% to 95% by vol.
Noble Gas (e.g., Ar) 5% to 80% by vol.
Pressure, mTon 0.1 to 300 milliTon
RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts
Temperature (°C) of Wafer about 150 to about 500°C
Layer 16 Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of Coil Inductor 100 Kto 300 MHz
RF Frequency of Wafer Pedestal 100 Kto 300 MHz
the protective layer 22 may be etched and removed under the same foregoing conditions. Thus, the same apparatus and process conditions may be employed to etch and remove selective parts of the protective layer 22, as well as to etch the electrode layer 16. In another prefened embodiment of the present invention and as will be also further explained below, the protective layer 22 and the elecfrode layer 16 (e.g., platinum elecfrode layer 16) may be removed and etched respectively in a high density plasma chamber containing a high density inductively coupled plasma under the following process conditions: Process Parameters
Etchant Gas flow 50 to 500 seem
Halogen Gas (e.g., Cl2) 10% to 90% by vol.
Noble Gas (e.g., Ar) 5% to 80% by vol.
HBr and/or BC13 4% to 25% by vol.
Pressure, mTon 0.1 to 300 milliTon
RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts
Temperature (°C) of Wafer about 150 to 500°C
Layer 16 Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of Coil Inductor 100 Kto 300 MHz
RF Frequency of Wafer Pedestal 100 Kto 300 MHz
In another embodiment of the present invention for etching an iridium electrode layer 16, the protective layer 22 (except protective layers 22a, 22b, 22c and 22d) may be etched by the high temperatures and etchant gases employed in the iridium-etching process of the present invention. More specifically and as will be further explained below, because the iridium electrode layer 16 is preferably etched under the following process conditions in a high density plasma chamber containing a high density inductively coupled plasma: Process Parameters
Etchant Gas flow 50 to 500 seem Halogen Gas (e.g., Cl2) 10% to 60% by vol. Noble Gas (e.g., Ar) 30% to 80%) by vol. Pressure, mTorr 0.1 to 300 milliTorr RF Power (watts) of Coil Inductor 100 to 5000 watts RF Power (watts) of Wafer Pedestal 50 to 3000 watts Temperature (°C) of Iridium Electrode Wafer about 150 to about 500°C Iridium Etch Rate (A/min) 200 to 6000 A/min RF Frequency of Coil Inductor 100 K to 300 MHz RF Frequency of Wafer Pedestal 100 K to 300 MHz
The protective layer 22 may be etched and removed under the same foregoing conditions. Thus, the same apparatus and process conditions may be employed to etch and remove selective parts of the protective layer 22, as well as to etch the iridium electrode layer 16. In another prefened embodiment of the present invention and as will be also further explained below, the protective layer 22 and the iridium electrode layer 16 may be removed and etched respectively in a high density plasma chamber containing a high density inductively coupled plasma under the following process conditions:
Process Parameters
Etchant Gas flow 50 to 500 seem
Oxygen 5% to 20% by vol.
Halogen Gas (e.g., Cl2) 10% to 60% by vol.
Noble Gas (e.g., Ar) 30% to 80% by vol.
HBr and/or HCl 5% to 20% by vol.
Pressure, mTorr 0.1 to 300 milliTorr
RF Power (watts) of Coil Inductor 100 to 5000 watts
RF Power (watts) of Wafer Pedestal 50 to 3000 watts
Temperature (°C) of Iridium Electrode Wafer about 150 to 500°C
Iridium Etch Rate (A/min) 200 to 6000 A/min
RF Frequency of Coil Inductor 100 Kto 300 MHz
RF Frequency of Wafer Pedestal 100 Kto 300 MHz
After selective parts of the mask layer 18 have been etched away from the surface of the elecfrode layer 16 to expose the latter and such that the only remnants of the mask layer 18 are the mask layers 18a, 18b, 18c and 18d situated immediately below the resist members 20a, 20b, 20c, and 20d, respectively, the resist members 20a, 20b, 20c and 20d are to be removed. The resist members 20a, 20b, 20c and 20d may be removed at any suitable time, preferably before the etching of the electrode layer 16 and before the heating of the semiconductor subsfrate 12 to a temperature greater than about 150° C. The same would hold true with respect to the embodiment of the invention illustrated in Figs. 2, 6 and 8 in that after selective parts of the protective layer 22 have been etched away from the surface of the elecfrode layer 16 to expose the latter and such that the only remnants of the protective layer 22 are the protective layers 22a, 22b, 22c and 22d situated respectively immediately below the mask layers 18a, 18b, 18c and 18d, the resist members 20a, 20b, 20c and 20d are to be removed. However, with respect to this embodiment of the present invention, the resist members 20a, 20b, 20c and 20d may be removed before the etching away of selective parts of the protective layer 22. Alternatively, the resist members 20a, 20b, 20c and 20d may be removed after (or simultaneously during) the removal of selective parts of the protective layer 22 and before the heating of the semiconductor substrate 12 to a temperature greater than about 150° C for purposes of etching the elecfrode layer 16. Typically, at least a portion of the resist members 20a, 20b, 20c and 20d would be removed while selective parts of the protective layer 22 are being etched away to expose the elecfrode layer 16 that is not superimposed by the protective layers 22a, 22b, 22c and 22d.
The resist members 20a, 20b, 20c and 20d may be removed in any suitable manner such as by using oxygen plasma ashing which is well known to those skilled in the art. The resist members 20a, 20b, 20c and 20d may be respectively stripped from the mask layers 18a, 18b, 18c and 18d with any suitable plasma processing apparatus, such as the plasma processing apparatus shown in Fig. 3 and employing a plasma containing an etchant gas comprising oxygen. The resist members 20a, 20b, 20c and 20d have been respectively removed from the mask layers 18a, 18b, 18c and 18d in an advanced strip passivation (ASP) chamber of a plasma processing apparatus sold under the frademark metal etch MxP Centura to Applied Materials, Inc. 3050 Bowers Avenue, Santa Clara, CA 95054-3299. In stripping the resist members 20a, 20b, 20c and 20d from the mask layers 18a, 18b, 18c and 18d, respectively, the ASP chamber may employ microwave downstream O2/N2 plasma with the following recipe: 120 seconds, 250°C, 1400W, 3000cc O2, 300cc N2 and 2Ton.
After the electrode layer 16 has been exposed as represented in Figs. 7 and 8, it is etched to develop a submicron pattern with a profile. As will be further stated below, before the elecfrode layer 16 is etched, the semiconductor subsfrate 12 supporting the elecfrode layer 16 is heated to a temperature greater than about 150° C, preferably greater than about 150° C up to about 500° C, more preferably from about 200° C to about 400° C, most preferably from about 250° C to about 350° C. The semiconductor substrate 12 is heated by the pedestal which supports the wafer 10 during the etching process (e.g., the noble metal etching process).
The elecfrode layer 16 may be etched in any suitable plasma processing apparatus, such as in the reactive ion etching (RIE) plasma processing apparatus sold under the trademark AME8100 Etch™, or under the frademark Precision Etch 5000™, or under the frademark Precision Etch 8300™, all trademarks owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. Another suitable plasma processing apparatus for etching the elecfrode layer 16 is that plasma processing apparatus sold under the trademark Metal Etch DPS Centura™ also owned by Applied Materials, Inc. It is also to be understood that other plasma etchers may be employed, such as ECR, ICP, Helicon Resonance, etc.
Most of the foregoing suitable plasma processing apparatuses employ a dielectric member. In a prefened embodiment of the present invention and in order to decrease the electrical conductivity of any process-by-product deposits as will be further explained below, the dielectric member has an inside surface which functions as a deposit- receiving surface where noble metal by-products, such as platinum by-products, form during plasma etching. The inside deposit-receiving surface of the dielectric member includes a surface finish having a peak-to valley roughness height with an average height value of more than about lOOOA; more preferably, an average height value of more than about 1800A, such as ranging from about 1800 A to about 4000A; most preferably, an average height value of more than about 4000A, such as ranging from about 4000A to about 8000A. Roughness may be defined as relatively finely spaced surface irregularities. On surfaces produced by machining and abrading operations, the inegularities produced by the cutting action of tool edges and abrasive grains and by the feed of the machine tool are roughness. Roughness deviations are measured perpendicular to a nominal surface NS (see Fig. 36). As best shown in Fig. 36, roughness height RH is measured from a peak P to a valley V. As further best shown in Fig. 36, the nominal surface NS is the surface that would result if the peaks P were leveled off to fill the valleys V. For the present invention, the roughness height RH (sometimes designated in the art as RA) values are average height values resulting from calculating the arithmetical average of all RH values on a deposit-receiving surface of a dielectric member obtained with a suitable instrument for measuring roughness of a surface. A suitable instrument for measuring an average RH value on the deposit-receiving surface may be obtained commercially from WYKO Corporation, Tucson, AZ under model No. PZ- 06-SC-SF, which is a non-contact optical surface profiler that employs phase-shifting interferometry (PSI) modes for measuring smooth surfaces and vertical-scanning interferomefry (VSI) modes for measuring rough surfaces and steps. Suitable procedures for calculating an average RH value on the deposit-receiving surface is described in a technical manual entitled WYKO Surface Profilers Technical Reference Manual, published by WYKO Corporation, and fully incorporated herein by reference thereto. A prefened procedure for finishing the deposit-receiving surface to obtain desirable average roughness height values includes bead blasting with 36-grid alumina.
As previously indicated and in accordance with the present invention, wafers 10, such as semiconductor substrates 12, are processed within a plasma processing chamber, preferably such as by plasma etching for patterning integrated circuit (TC) metal interconnect devices. It is to be understood that while plasma etching is one of the prefened plasma processes for the embodiment of the invention employing a dielectric member (or window) including an inside surface (i.e., a deposit-receiving surface) having a surface finish having a peak-to-valley roughness height with an average height value of more than about 1000 A, the spirit and scope of this embodiment of the invention includes other forms of processing subsfrates, such as chemical vapor deposition and physical vapor deposition. As further previously indicated, during plasma processing of wafers 10, processing power (e.g., RF power, magnetron power, microwave power, etc.) passes through a dielectric member, which includes a dielectric window of a nonconductive material such as a ceramic dome, etc., and becomes coupled to a plasma of the proceeding gas. If the plasma process is plasma etching, metal etching of metals (e.g., platinum, copper, aluminum, titanium, ruthenium, iridium, etc.) is conducted while being supported by substrates. Also during the plasma process, a deposit of materials occurs on an inside surface of the dielecfric member, as disclosed in copending patent application Serial No. 08/920,283, filed August 26, 1997, and fully incorporated herein by reference thereto. The deposit is located between the plasma and the power source. If the plasma process for this embodiment of the present invention is plasma etching, the deposit results from etching a metal layer on the subsfrate; and, thus, the deposit could be electrically conductive, and includes, by way of example only, metal, metal oxide(s), metal nitride(s), etc. The metal conesponds to the metal which is being etched within the process chamber and includes, also by way of example only, platinum, copper, aluminum, titanium, ruthenium, iridium, etc. When the deposit is electrically conductive and is between the plasma and the power source, a decay in processing power transmission occurs and continues until the electrically conductive deposit reaches a certain thickness (i.e., skin depth), such as from about 0.001 in. to about 0.5 in., whereafter the processing power transmission becomes very low or even nil. The deposit, therefore, behaves as a Faraday shield to reduce the efficiency of processing power transmission into the plasma of the processing gas within the process chamber. When processing power transmission through the dielectric member and into the process chamber commences to decline, the processing (e.g., the etch rate) of the metal layer supported by the substrate starts to decline. In order to maintain a generally more stable processing power transmission through the dielectric member and into the process chamber, and thus maintain and/or extend the time for stable processing of metal layers (e.g., the etch rate on metal layers) supported by substrates, the inside deposit-receiving surface of the dielectric member includes, as was more specifically discussed above, a surface finish having a peak-to-valley roughness height with an average height value of more than about 1000 A. By employing such a surface finish on the dielectric member or ceiling, a larger surface area is provided for receiving the by- products from the plasma process, which would decrease the thickness or skin depth of a given volume of by-products. For any given volume of by-product deposits, the smaller the surface area supporting the by-product deposits, the thicker or greater is the skin depth, and vice versa. As the thickness or skin depth of a given volume of by-products from the plasma process increases, the more electrically conductive the by-product deposits become. A suitable plasma processing apparatus for etching the electrode layer 16
(e.g., a platinum electrode layer 16) employs a plasma of an etchant gas, which is capable of producing good profiles (e.g., profiles, such as platinum or iridium profiles, equal to or greater than about 85 degrees, preferably equal to or greater than about 87 degrees, more preferably equal to or greater than about 88.5 degrees). The etchant gas broadly comprises a halogen containing gas, such as a halogen gas (e.g., fluorine, chlorine, bromine, iodine, and astatine) and a noble gas such as helium, neon, argon, krypton, xenon, and radon. Preferably, the etchant gas comprises or consists of or consists essentially of a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon. The noble gas is preferably argon. The etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 20% by volume to about 95% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80%> by volume of the noble gas (i.e., argon); more preferably from about 40% by volume to about 80%> by volume of the halogen gas (i.e., chlorine) and from about 20% by volume to about 60% by volume of the noble gas (i.e., argon); most preferably from about 55% by volume to about 65%> by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon).
The etchant gas may also broadly comprise oxygen, a halogen containing gas, such as a halogen gas (e.g., fluorine, chlorine, bromine, iodine, and astatine), and a noble gas such as helium, neon, argon, krypton, xenon, and radon. Preferably, the etchant gas comprises, or consists of or consists essentially of, a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon and argon. The noble gas is preferably argon. The etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 5% by volume to about 40% by volume oxygen, from about 10% by volume to about 60% by volume of the halogen gas (i.e., chlorine), and from about 30% by volume to about 80%) by volume of the noble gas (i.e., argon); more preferably from about 10% by volume to about 30% by volume oxygen, from about 20% by volume to about 50% by volume of the halogen gas (i.e., chlorine), and from about 40%> by volume to about 70% of the noble gas (i.e., argon); most preferably from about 10% by volume to about 20% by volume oxygen, from about 20% by volume to about 30% by volume halogen gas (i.e., chlorine), and from about 50% by volume to about 70% by volume of noble gas (i.e., argon).
In another prefened embodiment of the invention, the etchant gas comprises, preferably consists of or consists essentially of, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, BC13 and mixtures thereof. The etchant gas more specifically comprises, or consists of or consists essentially of, from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 4% by volume to about 25% by volume of HBr and/or BC13; preferably from about 40% by volume to about 70% by volume of the halogen gas (i.e., chlorine) and from about 25% by volume to about 55% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or BC1 ; and more preferably from about 50%> by volume to about 60% by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or BC13. The etchant gas flow rate ranges from about 50 seem to about 500 seem. HBr and/or BC13 are for removal of residue (e.g. platinum or iridium residue) during etching of the electrode layer 16 (e.g., the platinum or iridium elecfrode layer). Plasmas containing argon are known to have a high energetic ion concentration and are often used for physical sputtering. The sputtering effect due to the ions is a function of the accelerating potential which exist between the plasma and the sample. In a further prefened embodiment of the invention, the etchant gas comprises, preferably consists of or consists essentially of, oxygen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, HCl and mixtures thereof. The etchant gas more specifically comprises, or consists of or consists essentially of, from about 5%> by volume to about 20% by volume oxygen, from about 10% by volume to about 60%> by volume of the halogen gas (i.e., chlorine) and from about 30% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or HCl; preferably from about 5% by volume to about 15% by volume oxygen, from about 20% by volume to about 50% by volume of the halogen gas (i.e., chlorine) and from about 40% by volume to about 70% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or HCl; and more preferably from about 5% by volume to about 10% by volume oxygen, from about 20% by volume to about 35% by volume of the halogen gas (i.e., chlorine) and from about 40% by volume to about 60% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 10% by volume of HBr and/or HCl. The etchant gas flow rate ranges from about 50 seem to about 500 seem. fri also another prefened embodiment of the invention, the etchant gas broadly comprises nifrogen, a halogen (e.g., fluorine, chlorine, bromine, iodine, and astatine) and a noble gas such as helium, neon, argon, krypton, xenon, and radon. Preferably, the etchant gas comprises or consists of or consists essentially of nitrogen, a halogen (preferably chlorine) and a noble gas selected from group consisting of helium, neon, and argon. The noble gas is preferably argon. The etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 0.1% by volume to about 60% by volume nitrogen, from about 40% by volume to about 90%> by volume of the halogen gas (i.e., chlorine), and from about 0.1% by volume to about 40% by volume of the noble gas (i.e., argon); more preferably from about 5% by volume to about 40% by volume nifrogen, from about 50% by volume to about 80%> by volume of the halogen gas (i.e., chlorine), and from about 5% by volume to about 30% by volume of the noble gas (i.e., argon); most preferably from about 10% by volume to about 30% by volume nitrogen, from about 60% by volume to about 70% by volume of the halogen gas (i.e., chlorine), and from about 10% by volume to about 20%) by volume of the noble gas (i.e., argon). For this embodiment of the invention, the plasma of the etchant gas may be a high density plasma or a low-density plasma having a density of less than about 10 /cm , preferably less than about 10 /cm .
In yet another prefened embodiment of the invention, the etchant gas comprises, preferably consists of or consists essentially of, nitrogen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, BC13, SiCL, and mixtures thereof. The etchant gas more specifically comprises, or consists of or consists essentially of, from about 0.1 % by volume to about 60% by volume nifrogen, from about 40% by volume to about 90% by volume of the halogen gas (i.e., chlorine), and from about 0.1% by volume to about 40%> by volume of the noble gas (i.e., argon), and from about 1%) by volume to about 30% by volume of HBr and/or BC13 and/or SiCl4; preferably from about 5% by volume to about 40% by volume nifrogen, from about 50% by volume to about 80%) by volume of the halogen gas (i.e., chlorine), and from about 5% by volume to about 30%) by volume of the noble gas (i.e., argon), and from about 5% by volume to about 20% by volume of HBr and/or BC13 and/or SiCl4; and more preferably from about 10% by volume to about 30% by volume nitrogen, from about 60% by volume to about 70% by volume of the halogen gas (i.e., chlorine), and from about 10% by volume to about 20% by volume of the noble gas (i.e., argon), and from about 1%> by volume to about 10% by volume of HBr and/or BC13 and/or SiCL- For this embodiment of the invention, the plasma of the etchant gas may be a high density plasma or a low density plasma having a density of less than about 10π/cm3, preferably less than about lθ7cm3. Alternatively, the etchant gas comprises or consists of or consists essentially of nitrogen and a halogen (preferably chlorine). The etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 10% by volume to about 90%) by volume nitrogen and from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine); more preferably from about 20% by volume to about 60% by volume nifrogen and from about 40%> by volume to about 80% by volume of the halogen gas (i.e., chlorine); most preferably from about 30%> by volume to about 40% by volume nitrogen, and from about 60% by volume to about 70% by volume of the halogen gas (i.e., chlorine). For this embodiment of the invention, the plasma of the etchant gas may be a high density plasma or a low-density plasma having a density of less than about 101 Vcm3, preferably less than about 109/cm3.
The reactor conditions for a suitable plasma processing apparatus, such as the plasma processing apparatus of Fig. 3, in etching the elecfrode layer 16 (e.g., platinum elecfrode layer 16) are as follows: Pressure 0.1-300 mTon
RF Power 100-5000 watts
Rotational Magnetic Field 20-100 Gauss
Temperature of Wafer about 150-about 500°C
Layer 16 Etch Rate 200-6000 Angstroms/min
The selectivity of elecfrode layer 16 to mask 18 is better than 2:1, depending on the materials employed for the mask layer 18.
More generally, the process parameters for etching the elecfrode 16 in a suitable plasma processing apparatus, such as the plasma processing apparatus of Fig. 3, fall into ranges as listed in the following Table V and based on the flow rate of etchant gas as also listed in Table V below: TABLE V
Process Broad Preferred Optimum
Gas Flow, seem
Etchant Gas 35 to 500 75 to 250 100 to 200
Pressure, mT 20 to 2000 30 to 300 50 to 150
13.56 MHz
RF Power (Watts) 50 to 3000 500 to 2000 700 to 1200
Temperature (°C) of Wafer 150 to 500 200 to 400 250 to 350
Magnetic Field Gauss 0 to 140 20 to 100 60 to 80
As previously indicated, a prefened etchant gas for etching the elecfrode layer 16 (e.g., the platinum elecfrode layer 16) is a mixture of chlorine and argon, or a mixture of chlorine, argon and HBr and/or BC13. Another prefened etchant gas for etching the elecfrode layer 16 is a mixture of oxygen, chlorine and argon, or a mixture of oxygen, chlorine, argon and HBr and/or HCl. If the etchant gas is a mixture of chlorine and argon (i.e., from about 20%> by volume to about 95% by volume chlorine and from about 5% by volume to about 80% by volume argon), or a mixture of chlorine, argon and HBr and/or BC13 (i.e., from about 10% by volume to about 90%> by volume chlorine and from about 5% by volume to about 80% by volume argon and from about 4% by volume to about 25% by volume HBr and/or BC13), and if the semiconductor subsfrate 12 is heated to a temperature greater than about 150°C, preferably to a temperature ranging from about 150°C to about 500°C, the plasma processing apparatus for etching the elecfrode layer 16 (e.g., the platinum elecfrode layer 16 or the iridium elecfrode layer 16) etches the elecfrode layer 16 in a high density plasma of the etchant gas at a high etch rate (e.g., an etch rate higher than 70θA/min for iridium, and an etch rate higher than 1000 A/min for platinum) and produces an etched elecfrode layer, generally illustrated as 16e (as best shown in Figs. 9 and 10). The etched electrode layer 16e (e.g., etched platinum elecfrode layer 16e or etched platinum elecfrode layer 16e) includes etched elecfrode - layers 16a, 16b, 16c and 16d (e.g., etched platinum or iridium layers) having corners 16g and sidewalls 16s and an excellent profile (e.g., an excellent platinum or iridium profile); that is, a profile where the angle °= of the sidewalls 16s (as also best shown in Figs. 9 and 10) with respect to a horizontal plane is equal to or greater than about 80 degrees (e.g., especially equal to or greater than 80 degrees for iridium), such as equal to or greater than about 85 degrees (e.g., especially equal to or greater than 85 degrees for platinum), preferably equal to or greater than about 87°, and more preferably equal to or greater than about 88.5°. The produced elecfrodes (e.g., produced platinum electrodes) are separated by a distance or space having a dimension equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm. Each of the electrodes (e.g., produced platinum electrodes) include a dimension having a value equal to or less than about 1.0 μm, preferably equal to or less than about 0.6 μm, more preferably equal to or less than about 0.35 μm, most preferably equal to or less than about 0.3 μm. More preferably, each of the elecfrodes (e.g., produced platinum electrodes) have a width equal to or less than about 1.0 μm, preferably equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm.
It has also been discovered that the etched electrode layer 16e (i.e., etched electrode layers 16a, 16b, 16c and 16d) has essentially no wall-like structures extending up from the edges of the platinum region. These wall-like structures are frequently refened to as "veils" or "fences" or "rabbit ears." Therefore, the method of the present invention produces etched elecfrode layers 16a, 16b, 16c and 16d which are essentially veil-less. Because the produced etched electrode layers 16a, 16b, 16c and 16d are essentially veil-less and have no "fences" or "rabbit ears," they are ideally suited for receiving a dielecfric BST or PZT or SBT layer and functioning as elecfrodes in a semiconductor device (i.e., a capacitance structure).
The high density plasma of the present invention may be defined as a plasma of the etchant gas of the present invention having an ion density greater than about 109/cm3, preferably greater than about 10π/cm3. The source of the high density plasma may be any suitable high density source, such as electron cyclotron resonance (ECR), helicon resonance or inductively coupled plasma (ICP)-type sources. All three are in use on production equipment today. The main difference is that ECR and helicon sources employ an external magnetic field to shape and contain the plasma, while ICP sources do not. The high density plasma for the present invention is more preferably produced or provided by inductively coupling a plasma in a decoupled plasma source etch chamber, such as that sold under the frademark DPS™ owned by Applied Materials, Inc. which decouples or separates the ion flux to the wafer 10 and the ion acceleration energy. The design of the etch chamber provides fully independent control of ion density of an enlarged process window. This is accomplished by producing plasma via an inductive source. While a cathode within the etch chamber is still biased with RF electric fields to determine the ion acceleration energy, a second RF source (i.e., an inductive source) determines the ion flux. This second RF source is not capacitive (i.e., it does not use electric fields like the cathode) since a large sheath voltage would be produced, interfering with the cathode bias and effectively coupling the ion energy and ion flux.
The inductive plasma source couples RF power through a dielecfric window rather than an elecfrode. The power is coupled via RF magnetic fields (not electric fields) from RF current in a coil. These RF magnetic fields penetrate into the plasma and induce RF electric fields (therefore the term "inductive source") which ionize and sustain the plasma. The induced elecfric fields do not produce large sheath voltages like a capacitive elecfrode and therefore the inductive source predominantly influences ion flux. The cathode bias power plays little part in determining ion flux since most of the RF power (typically an order of magnitude less than the source power) is used in accelerating ions. The combination of an inductive plasma source and a capacitive wafer bias allows independent control of the ion flux and ion energy reaching the wafer 10 in the etch chamber, such as the DPS™ brand etch chamber.
DPS™ brand etch chambers for producing the high density plasma of the present invention for etching the elecfrode layer 16 to produce the etched electrode layers 16a, 16b, 16c and 16d may be any of the DPS™ brand etch chambers of the inductively coupled plasma reactor disclosed in U.S. Patent No. 5,753,044, entitled "RF PLASMA REACTOR WITH HYBRID CONDUCTOR AND MULTI-RADIUS DOME CEILING" and assigned to the present assignee and fully incorporated herein by reference thereto as if repeated verbatim immediately hereinafter. Referring now to Figs. 17 and 18 for two (2) embodiments of an inductively coupled plasma reactor from U.S. Patent No.
5,753,044 there is seen an inductively coupled RF plasma reactor generally illustrated as 90, having a reactor chamber, generally illustrated as 92, wherein a high density plasma 94 of neutral (n) particles, positive (+) particles, and negative (-) particles are found. The reactor chamber 92 has a grounded conductive cylindrical sidewall 60 and a dielecfric ceiling 62 having an inside concave surface 62a which would receive deposits of by- products from plasma processing of wafers 10. The inductively coupled RF plasma reactor 90 further comprises a wafer pedestal 64 for supporting the (semiconductor) wafer 10 in the center of the chamber 92, a cylindrical inductor coil 68 surrounding an upper portion of the chamber 92 beginning near the plane of the top of the wafer 10 or wafer pedestal 64 and extending upwardly therefrom toward the top of the chamber 92, an etching gas source 72 and gas inlet 74 for furnishing an etching gas into the interior of the chamber 92, and a pump 76 for controlling the pressure in the chamber 92. The coil inductor 68 is energized by a plasma source power supply or RF generator 78 through a conventional active RF match network 80, the top winding of the coil inductor 68 being "hot" and the bottom winding being grounded. The wafer pedestal 64 includes an interior conductive portion 82 connected to the bias RF power supply or generator 84 and an exterior grounded conductor 86 (insulated from the interior conductive portion 82). Thus, the plasma source power applied to the coil inductor 68 by the RF generator 78 and the DC bias RF power applied to the wafer pedestal 64 by generator 84 are separately controlled RF supplies. Separating the bias and source power supplies facilitates independent control of ion density and ion energy, in accordance with well-known techniques. To produce high density plasma 94 as an inductively coupled plasma, the coil inductor 68 is adjacent to the chamber 92 and is connected to the RF source power supply or the RF generator 78. The coil inductor 68 provides the RF power which ignites and sustains the high ion density of the high density plasma 94. The geometry of the coil inductor 68 can in large part determine spatial distribution of the plasma ion density of the high density plasma 94 within the reactor chamber 92.
Uniformity of the plasma density spatial distribution of the high density plasma 94 across the wafer 10 is improved (relative to conical or hemispherical ceilings) by shaping the ceiling 62 in a multi-radius dome and individually determining or adjusting each one of the multiple radii of the ceiling 62. The multiple-radius dome shape in the particular embodiment of Fig. 17 somewhat flattens the curvature of the ceiling 62 around the center portion of the ceiling 62, the peripheral portion of the ceiling 62 having a steeper curvature.
As illustrated in Fig. 18 the coil inductor 68 may be coupled to the RF power source 78, 80 in a minor coil configuration that is known to those skilled in the art. In the minor coil configuration of Fig. 18, the RF source 78, 80 is connected to the center winding of the coil inductor 68 while the top and bottom ends of the coil inductor 68 are both grounded. The minor coil configuration has the advantage of reducing the maximum potential on the coil inductor 68.
It has been discovered that by employing a high density plasma, such as the high density plasma 94 illustrated in Figs. 17 and 18, for etching the elecfrode layer 16 (e.g., a platinum elecfrode layer 16 or an iridium elecfrode layer 16), and by heating the semiconductor subsfrate 12 to a temperature greater than about 150°C before conducting the etching operation under process parameters which are stated below, a semiconductor device is produced with electrodes (e.g., noble metal electrodes such as platinum elecfrodes or iridium) having a profile with an angular value which is equal to or greater than about 80 degrees (e.g., equal to greater than about 80 degrees for iridium), preferably equal to or greater than about 85 degrees (e.g., equal to or greater than 85 degrees for platinum), more preferably equal to or greater than about 87 degrees, most preferably equal to or greater than about 88.5 degrees. The electrodes are essentially veil- less; that is, they have no "fences" or "rabbit ears." The elecfrodes are preferably separated by a distance or space having a dimension equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm. Each of the electrodes include a dimension having a value equal to or less than about 1.0 μm, preferably equal to or less than about 0.6 μm, more preferably equal to or less than about 0.35 μm, most preferably equal to or less than about 0.3 μm. More preferably, each of the elecfrodes have a width equal to or less than about 0.35μm, more preferably equal to or less than about 0.3 μm, a length equal to or less than about 1.0 μm, more preferably equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm.
The prefened reactor conditions for a suitable inductively coupled RF plasma reactor, such as the inductively coupled RF plasma reactor 90 in Figs. 17 and 18, in etching the elecfrode layer 16 (e.g., platinum electrode layer 16) are as follows: Pressure 0.1 to 300 mTon
RF Power to Coil Inductor 100 to 5000 watts
RF Power to Wafer Pedestal 50 to 3000 watts
RF Frequency in Coil Inductor 100K to 300 MHz
RF Frequency in Wafer Pedestal 100K to 300 MHz
Temperature of Wafer 150 to 500° C
Layer 16 Etch Rate 200 to 6000 Angstrom/min
More generally, the process parameters for etching the elecfrode layer 16 (e.g., platinum elecfrode layer 16) in a suitable inductively coupled plasma reactor, such as the inductively coupled plasma reactor 90 in Figs. 17 and 18, fall into ranges as listed on the basis of flow rates of the gases, including the halogen gas(es) (i.e., Cl2) and the noble gas(es) (i.e., argon), as listed in Table VI below.
TABLE VI
Process Broad Preferred Optimum
Gas Flow, seem
C-2 30 to 400 50 to 250 60 to 150
Ar 20 to 300 30 to 200 40 to 100
Pressure, mT 0.1 to 300 10 to 100 10 to 40
RF Power of Coil
Inductor (Watts) 100 to 5000 650 to 2000 900 to 1500
RF Power of Wafer
Pedestal (Watts) 50 to 3000 100 to 1000 150 to 400
Temperature of Wafer
(°C) about 150 to about 500 200 to 400 250 to 350
Layer 16 Etch Rate
(A/min) 200 to 6000 500 to 3000 1000 to 2000
RF Frequency of Coil
Inductor 100 Kto 300 MHz 400 Kto 20 MHz 2 to 13.5 MHz
RF Frequency of Wafer
Pedestal 100 K to 300 MHz 400 K to 20 MHz 400 K to 13.5 MHz Also generally, the process parameters for etching the electrode layer 16 (e.g. an iridium elecfrode layer 16) in a suitable inductively coupled plasma reactor, such as the inductively coupled plasma reactor 90 in Figs. 17 and 18, fall into ranges as listed on the basis of flow rates of the gases, including oxygen, the halogen gas(es) (i.e., Cl2), and the noble gas(es) (i.e., argon), as listed in Table Nil below.
TABLE π
Process Broad Preferred Optimum
Gas Flow, seem
C-2 10 to 60 10 to 40 15 to 30
C-2 30 to 100 30 to 70 50 to 70
Ar 50 to 250 100 to 200 100 to 150
Pressure, mT 0.1 to 300 10 to 100 10 to 40
RF Power of Coil
Inductor (Watts)
100 to 5000 650 to 2000 900 to 1500
RF Power of Wafer
Pedestal (Watts)
50 to 3000 100 to 1000 150 to 600
Temperature of Wafer
(°C) about 150 to about 500 200 to 400 250 to 350
Etch Rate (A/min) 200 to 6000 500 to 3000 500 to 2000
RF Frequency of Coil
Inductor
100 Kto 300 MHz 400 Kto 20 MHz 2 to 13.5 MHz
RF Frequency of Wafer
Pedestal
100 K to 300 MHz 400 K to 20 MHz 400 K to 13.5 MHz
Also, more generally further, and when the etchant gases are a mixture of the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or BC13, the process parameters for etching the elecfrode layer 16 (e.g., platinum elecfrode layer 16) in a suitable inductively coupled plasma reactor, such as the inductively coupled plasma reactor 90 in Figs. 17 and 18, fall into the ranges as listed on the basis of flow rates of the gases, including the halogen gas(es) (i.e., Cl2) and the noble gas(es) (i.e., Ar) and HBr and/or BC13, as listed in Table VHI below: TABLE VIII
Process Broad Preferred Optimum
Gas Flow, seem
Cla 30 to 400 50 to 250 60 to 150
Ar 20 to 300 30 to 200 40 to 100
HBr and/or BC13 5 to 70 5 to 40 5 to 20
Pressure, mT 0.1 to 300 10 to 100 10 to 40
RF Power of Coil Inductor (Watts) 100 to 5000 650 to 2000 750 to 1000
RF Power of Wafer Pedestal (Watts) 50 to 3000 100 to 1000 150 to 400
Temperature of Wafer (°C) about 150 to about 500 200 to 400 250 to 350
Layer 16 Etch Rate (A/min) 200 to 6000 500 to 3000 1000 to 2000
RF Frequency of Coil Inductor 100 Kto 300 MHz 400 Kto 20 MHz 2 to 13.5 MHz
RF Frequency of Wafer Pedestal 100 Kto 300 MHz 400 K to 20 MHz 400 Kto 13.5 MHz
Also more generally further, and when the etchant gases are a mixture of oxygen, the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or BC13, the process parameters for etching elecfrode layer 16 (e.g., iridium electrode layer 16) in a suitable inductively coupled plasma reactor, such as the inductively coupled plasma reactor 90 in Figs. 17 and 18, fall into the ranges as listed on the basis of rates of the gases, including oxygen, the halogen gas(es) (i.e., Cl2), the noble gas(ses) (i.e., Ar), and HBr and/or HCl, as listed in Table IX below:
TABLE IX
Process Broad Preferred Optimum
Gas Flow, seem
Figure imgf000072_0001
Ck 30 to 100 30 to 70 50 to 70
Ar 50 to 250 100 to 200 100 to 150
HBr and/or HCl 10 to 60 10 to 40 15 to 30
Pressure, Mt 0.1 to 300 10 to 100 10 to 40
RF Power of Coil
Inductor (Watts)
100 to 5000 650 to 2000 750 to 1000
RF Power of Wafer
Pedestal (Watts)
50 to 3000 100 to 1000 150 to 600
Temperature of Wafer about 150 to about 500
(°C) 200 to 400 250 to 350
Etch Rate (A/min) 200 to 6000 500 to 3000 500 to 2000
RF Frequency of Coil
Inductor
100 Kto 300 MHz 400 K to 20 MHz 2 to 13.5 MHz
RF Frequency of Wafer
Pedestal
100 Kto 300 MHz 400 K to 20 MHz 400 Kto 13.5 MHz
Therefore, the foregoing process conditions are preferably based on flow rates of etchant gas(es) having a flow rate value ranging from about 5 to about 500 seem. It will be appreciated by those skilled in the art that the process parameters of the Tables, previously mentioned and mentioned hereinafter, may vary in accordance with the size of the wafer 10. As was previously mentioned, the etchant gas comprises or consists of or consists essentially of a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon. In another prefened embodiment of the invention, the etchant gas comprises, or consists of or consists essentially of, oxygen, a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon. The noble gas is preferably argon. As was also previously mentioned, the etchant gas more specifically comprises or consists of or consists essentially of from about 20% by volume to about 95% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon); preferably from about 40% by volume to about 80% by volume of the halogen gas (i.e., chlorine) and from about 20%> by volume to about 60% by volume of the noble gas (i.e., argon); more preferably from about 55% by volume to about 65% by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45%> by volume of the noble gas (i.e., argon). As was further previously mentioned, the etchant gas more specifically comprises, or consists of or consists essentially of, from about 5% by volume to about 40% by volume oxygen, from about 10% by volume to about 60%) by volume of the halogen gas (i.e., chlorine) and from about 30% by volume to about 80%) by volume of the noble gas (i.e., argon); preferably from about 10%) by volume to about 30% by volume oxygen, from about 20%> by volume to about 50%> by volume of the halogen gas (i.e., chlorine) and from about 40% by volume to about 70% by volume of the noble gas (i.e., argon); more preferably from about 10%> by volume to about 20% by volume oxygen, from about 20% by volume to about 30% by volume of the halogen gas (i.e., chlorine) and from about 50% by volume to about 70% by volume of the noble gas (i.e., argon). In yet another prefened embodiment of the invention and as was previously mentioned, the etchant gas comprises, preferably consists of or consists essentially of, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group that consists of HBr, BC13 and mixtures thereof. In also yet another prefened embodiment of the invention and as was previously mentioned, the etchant gas comprises, preferably consists of or consists essentially of, oxygen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group that consists of HBr, BC13 and mixtures thereof. The etchant gas more specifically comprises, or consists of or consists essentially of from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine) and from about 5% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 4% by volume to about 25%> by volume of HBr and/or BC13; preferably from about 40% by volume to about 70% by volume of the halogen gas (i.e., chlorine) and from about 25%> by volume to about 55% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20%> by volume of HBr and/or BC13; and more preferably from about 50% by volume to about 60% by volume of the halogen gas (i.e., chlorine) and from about 35% by volume to about 45% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or BC13. As was also yet further previously mentioned, the etchant gas more specifically comprises, or consists of or consists essentially of, from about 5% by volume to about 20%) by volume oxygen, from about 10%> by volume to about 60%> by volume of the halogen gas (i.e., chlorine) and from about 30% by volume to about 80% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 20% by volume of HBr and/or HCl; preferably from about 5% by volume to about 15% by volume oxygen, from about 20%) by volume to about 50% by volume of the halogen gas (i.e., chlorine), from about 40% by volume to about 70% by volume of the noble gas (i.e., argon) and from about 5% by volume to about 15% by volume of HBr and/or HCl; and more preferably from about 5% by volume to about 10% by volume oxygen, from about 20%> by volume to about 35%> by volume of the halogen gas (i.e., chlorine) and from about 40%) by volume to about 60%> by volume of the noble gas (i.e., argon) and from about 5 by volume to about 10% by volume of HBr and/or HCl. Thus, the foregoing process conditions stated in previously mentioned Tables may be based on such etchant gas constituency and on such percent (%) by volume value(s).
In the prefened embodiment of the present invention where the mask layers 18a, 18b, 18c and 18d comprise Ti and/or TiN, preferably TiNi, and the elecfrode layer 16 is an iridium elecfrode layer 16, the process parameters for etching the iridium electrode layer 16 in a suitable inductively coupled plasma reactor fall into ranges as listed on the basis of flow rates of the gases, including oxygen, the halogen gas(es), (i.e., Cl2), and the noble gas(es) (i.e., argon), as hsted in Table X below.
TABLE X
Process Broad Preferred Optimum
Gas Flow, seem
C-2 10 to 60 10 to 40 15 to 30
Cl2 30 to 100 30 to 70 50 to 70
Ar 50 to 250 100 to 200 100 to 150
Pressure, mT 0.1 to 300 10 to 100 10 to 40
RF Power of Coil 100 to 5000 650 to 2000 750 to 1000
Inductor (Watts)
RF Power of Wafer 50 to 3000 100 to 1000 150 to 600
Pedestal (Watts)
Temperature of Wafer about 150 to about 500 200 to 400 250 to 350
(°C) Iridium (Ir) Etch Rate 200 to 6000 500 to 3000 500 to 2000 (A/min)
Selectively of Ir to Ti or 0.2 to 50 l to 20 6 to 10 TiN of Mask Layers
RF Frequency of Coil 100 Kto 300 MHz 400 Kto 20 MHz 2 to 13.5 MHz Inductor
RF Frequency of Wafer 100 Kto 300 MHz 400 Kto 20 MHz 400 K to 13.5 MHz Pedestal
When the etchant gases are a mixture of oxygen, the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or HCl, the process parameters for etching iridium electrode layer 16 supporting a Ti/TiN mask layer 18 in a suitable inductively coupled plasma reactor fall into the ranges as listed on the basis of rates of the gases, including oxygen, the halogen gas(es) (i.e., Cl2), the noble gas(ses) (i.e., Ar), and HBr and/or HCl, as Hsted in Table XI below:
TABLE XI
Process Broad Preferred Optimum
Gas Flow, seem o2 10 to 60 10 to 40 15 to 30
Cl2 30 to 100 30 to 70 50 to 70
Ar 50 to 250 100 to 200 100 to 150
HBr and/or HCl 10 to 60 10 to 40 15 to 30
Pressure, mT 0.1 to 300 10 to 100 10 to 40
RF Power of Coil Inductor (Watts)
100 to 5000 650 to 2000 750 to 1000
RF Power of Wafer Pedestal (Watts)
50 to 3000 100 to 1000 150 to 600
Temperature of Wafer
(°C) about 150 to about 500 200 to 400 250 to 350
Iridium Etch Rate
(A/min)
200 to 6000 500 to 3000 500 to 2000
Selectivity of Ir to Ti or TiN of Mask Layers
0.2 to 50 l to 20 6 to 10
RF Frequency of Coil
Inductor
100 Kto 300 MHz 400 Kto 20 MHz 2 to 13.5 MHz
RF Frequency of Wafer
Pedestal
100 Kto 300 MHz 400 Kto 20 MHz 400 Kto 13.5 MHz
More generally further, the process parameters for etching in a low density (or high density) plasma the elecfrode layer 16 (e.g., platinum electrode layer 16) in a suitable inductively coupled plasma reactor fall into ranges as listed on the basis of flow rates of the gases, including nitrogen (N2), the halogen gas(es) (i.e., Cl2), and the noble gas(es) (i.e., argon), as hsted in Table XII below.
TABLE Xπ
Process Broad Preferred Optimum
Gas Flow, seem
N2 5 to 200 10 to 150 10 to 50
C-2 30 to 400 50 to 300 100 to 200
Ar 0 to 200 10 to 100 10 to 50
Pressure, mT 0.1 to 300 10 to 100 10 to 50
RF Power of Coil Inductor 100 to 5000 500 to 3000 750 to 1500 (Watts)
RF Power of Wafer 50 to 3000 100 to 1000 150 to 400 Pedestal (Watts)
Temperature of Wafer (°C) about 150 to about 500 200 to 400 250 to 350
Layer 16 Etch Rate (A/min) 200 to 6000 500 to 3000 1000 to 2000
RF Frequency of Coil 100K to 300 MHz 400Kto 20 MHz 2 to 13.5 MHz Inductor
RF Frequency of Wafer 100K to 300 MHz 400Kto 20 MHz 400Kto 13.5 MHz Pedestal
If a reactive ion etch (RIE) plasma processing apparatus is employed for etching the elecfrode layer 16 (e.g., platinum elecfrode layer 16) in a low density plasma of the etchant gas(es), the process parameters for etching fall into ranges as hsted on the basis of flow rates of the gases, including nitrogen (N2), the halogen gas(es) (i.e., Cl2), and the noble gas(es) (i.e., argon), as listed in Table XIII below.
TABLE Xm
Process Broad Preferred Optimum
Gas Flow, seem
N2 5 to 200 30 to 200 60 to 120
Cl2 30 to 400 50 to 300 100 to 200
Ar 0 to 200 10 to 100 10 to 50
Pressure, mT 0.1 to 2000 50 to 400 100 to 200
RF Power of Wafer Pedestal 100 to 5000 300 to 2500 500 to 1200 (Watts)
Temperature of Wafer (°C) about 150 to 200 to 400 250 to 350 about 500
Layer 16 Etch Rate (A/min) 200 to 6000 500 to 3000 1000 to 2000
RF Frequency of Wafer 100 Kto 300 400 K to 20 400K to l3.5 MHz Pedestal MHz MHz
Alternatively, if a reactive ion etch (RIE) plasma processing apparatus is employed for etching the electrode layer 16 (e.g., platinum electrode layer 16) in a low density plasma of the etchant gas(es), the process parameters for etching fall into ranges as listed on the basis of flow rates of the gases, including nifrogen (N2) and the halogen gas(es) (i.e., Cl2), as listed in Table XIV below. TABLE XIV
Process Broad Preferred Optimum
Gas Flow, seem
N2 5 to 300 40 to 200 70 to 90
Cl2 30 to 600 100 to 400 150 to 200
Pressure, mT 0.1 to 2000 50 to 400 100 to 200
RF Power of Wafer 100 to 5000 300 to 2500 500 to 1200 Pedestal (Watts)
Temperature of about 150 to about 200 to 400 250 to 350 Wafer (°C) 500
Layer 16 Etch Rate 200 to 6000 500 to 3000 1000 to 2000 (A/min)
RF Frequency of 100K to 300 MHz 400K to 20 MHz 400K to 13.5 MHz Wafer Pedestal
Also more generally further, and when the etchant gases are a mixture of nitrogen (N2), the halogen gas(es) (i.e., chlorine), the noble gas(es) (i.e., argon), and HBr and/or BC1 and/or SiCl4, the process parameters for etching in a low density (or high density) plasma the electrode layer 16 (e.g., platinum electrode layer 16) in a suitable inductively coupled plasma reactor fall into the ranges as listed on the basis of flow rates of the gases, including nitrogen (N2), the halogen gas(es) (i.e., Cl2), the noble gas(es) (i.e., Ar), and HBr and/or BC13 and/or SiCl4, as listed in Table XV below:
TABLE XV
Process Broad Preferred Optimum
Gas Flow, seem
N2 5 to 200 10 to 150 10 to 50
Cl2 30 to 400 50 to 300 100 to 200
Ar 0 to 200 10 to 100 10 to 50
HBr and/or BC13 lto70 5 to 40 5 to 20 and/or SiCL
Pressure, mT 0.1 to 300 10 to 100 10 to 50
RF Power of Coil 100 to 5000 500 to 3000 750 to 1500 Inductor (Watts)
RF Power of Wafer 50 to 3000 100 to 1000 150 to 400 Pedestal (Watts)
Temperature of about 150 to about 200 to 400 250 to 350 Wafer (°C) 500
Layer 16 Etch Rate 200 to 6000 500 to 3000 1000 to 2000 (A/min)
RF Frequency of 100Kto300 Hz 400Kto20MHz 2 to 13.5 MHz Coil Inductor
RF Frequency of 100K to 300 MHz 400Kto20MHz 400Ktol3.5MHz Wafer Pedestal
If a reactive ion etch (RIE) plasma processing apparatus is employed for etching the electrode layer 16 (e.g., platinum electrode layer 16) in a low density plasma of the etchant gas(es), the process parameters for etching fall into ranges as hsted on the basis of flow rates of the gases, including nitrogen (N2), the halogen gas(es) (i.e., Cl2), and the noble gas(es) (i.e., Ar), and HBr and/or BC13 and/or SiCl4, as listed in Table XVI below:
TABLE XVI
Process Broad Preferred Optimum
Gas Flow, seem
N2 5 to 300 30 to 200 60 to 120
Cl2 30 to 400 50 to 300 100 to 200
Ar 0 to 200 10 to 100 10 to 50
HBr and/or BC13 l to 70 5 to 40 5 to 20 and/or SiCL
Pressure, mT 0.1 to 2000 50 to 400 100 to 200
RF Power of Wafer 100 to 5000 300 to 2500 500 to 1200
Pedestal (Watts)
Temperature of about 150 to about 200 to 400 250 to 350
Wafer (C°) 500
Layer 16 Etch Rate 200 to 6000 500 to 3000 1000 to 2000
(A/min)
RF Frequency of 100K to 300 MHz 400Kto 20 MHz 400K to 13.5 MHz
Wafer Pedestal
Therefore, for this prefened embodiment of the present invention, the foregoing process conditions are preferably based on flow rates of etchant gas(es) having a flow rate value ranging from about 5 to about 500 seem. As was previously mentioned, the etchant gas comprises or consists of or consists essentially of nitrogen, a halogen (preferably chlorine) and a noble gas selected from the group consisting of helium, neon, and argon. The noble gas is preferably argon. As was also previously mentioned, the etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 0.1 %> by volume to about 60%> by volume nitrogen, from about 40% by volume to about 90% by volume of the halogen gas (i.e., chlorine), and from about 0.1% by volume to about 40% by volume of the noble gas (i.e., argon); more preferably from about 5% by volume to about 40% by volume nitrogen, from about 50% by volume to about 80%> by volume of the halogen gas (i.e., chlorine), and from about 5% by volume to about 30% by volume of the noble gas (i.e., argon); most preferably from about 10% by volume to about 30%> by volume nifrogen, from about 60% by volume to about 70% by volume of the halogen gas (i.e., chlorine), and from about 10%) by volume to about 20% by volume of the noble gas (i.e., argon). Alternatively, the etchant gas comprises or consists of or consists essentially of a nitrogen and halogen (preferably chlorine). The etchant gas more specifically comprises, or consists of or consists essentially of, preferably from about 10% by volume to about 90%> by volume nifrogen and from about 10% by volume to about 90% by volume of the halogen gas (i.e., chlorine); more preferably from about 20%> by volume to about 60% by volume nitrogen and from about 40% by volume to about 80% by volume of the halogen gas (i.e., chlorine); most preferably from about 30%> by volume to about 40% by volume nitrogen and from about 60% by volume to about 70%) by volume of the halogen gas (i.e., chlorine). In another prefened embodiment of the invention and was also previously mentioned, the etchant gas comprises, preferably consists of or consists essentially of, nifrogen, the halogen (i.e., chlorine), the noble gas (i.e., argon), and a gas selected from the group consisting of HBr, BC13, SiCL, and mixtures thereof. As was further also previously mentioned, the etchant gas more specifically comprises, or consists of or consists essentially of, from about 0.1% by volume to about 60%> by volume nitrogen, from about 40% by volume to about 90% by volume of the halogen gas (i.e., chlorine), and from about 0.1% by volume to about 40% by volume of the noble gas (i.e., argon), and from about 1% by volume to about 30% by volume of HBr and/or BC13 and/or SiCL; preferably from about 5%> by volume to about 40% by volume nitrogen, from about 50% by volume to about 80% by volume of the halogen gas (i.e., chlorine), and from about 5% by volume to about 30% by volume of the noble gas (i.e., argon), and from about 5% by volume to about 20% by volume of HBr and/or BC13 and/or SiCl4; and more preferably from about 10% by volume to about 30% by volume nitrogen, from about 60%> by volume to about 70% by volume of the halogen gas (i.e., chlorine), and from about 10% by volume to about 20% by volume of the noble gas (i.e., argon), and from about 1% by volume to about 10% by volume of HBr and/or BC1 and/or SiC-U- Thus, the foregoing process conditions stated in the previously mentioned Tables may be based on such etchant gas constituency and on such percent (%) by volume value(s).
It has also been discovered that noble metal etch by-products (e.g., platinum etch byproducts) may become less conductive electrically, and the stability of RF power transmission through the dielectric window becomes more stable, by operating the platinum etch process in a high Cl2/Ar ratio and a high pressure regime. The Cl2/Ar ratio may be any suitable elevated or high gas volume ratio, preferably a Cl2/Ar volume ratio of greater than 2(>2): 1 , more preferably greater than 4(>4): 1. The high pressure may be any suitable elevated or high pressure, preferably greater than 10 mTon (>10 mTon), more preferably greater than 24 mTon (>24). More generally, when the etchant gases are a mixture of the halogen gas(es) (i.e., chlorine) and the noble gas(es) (i.e., argon), the process parameters for etching the electrode layer 16 (e.g., platinum electrode layer 16) in a suitable inductively coupled plasma reactor for reducing the electrical conductivity of layer 16 by-products fall into the ranges as listed on the basis of flow rates of the gases, including the halogen gas(es) (i.e., Cl2) and the noble gas(es) (i.e., Ar), as hsted in Table XVII below:
TABLE XVπ
Process Broad Preferred Optimum
Gas Flow, seem
Halogen (e.g., Cl2) 30 to 400 50 to 250 100 to 150
Noble gas (e.g., Ar) 20 to 300 20 to 100 20 to 30
Cl /Ar vol. ratio l to 20 2 to 10 4 to 6
Pressure, mT 0.1 to 300 10 to 100 10 to 50
RF Power of Coil 100 to 5000 500 to 3000 750 to 1500 Inductor (Watts)
RF Power of Wafer 50 to 3000 100 to 1000 150 to 400 Pedestal (Watts)
Temperature of Wafer about 150 to about 200 to 400 250 to 350 (°C) 500
Layer 16 Etch Rate 200 to 6000 500 to 3000 1000 to 2000 (A/min)
RF Frequency of Coil 100K to 300 MHz 400K to 20 MHz 2 to 13.5 MHz Inductor
RF Frequency of 100K to 300 MHz 400K to 20 MHz 400K to l3.5 MHz Wafer Pedestal
The foregoing process conditions stated in Table XVII above may be based on the following etchant gas constituency for reducing the electrical conductivity of noble metal by-products (e.g., platinum etch by-products): preferably from about 50%> to about 96% by volume of the halogen gas(es) (i.e., chlorine) and from about 4% to about 50% by volume of the noble gas(es) (i.e., argon); more preferably from about 60% to about 90% by volume of the halogen gas(es) (i.e., chlorine) and from about 10% to about 40%> by volume of the noble gas(es) (i.e., argon); most preferably from about 70% to about 85% by volume of the halogen gas(es) (i.e., chlorine) and from about 15% to about 30% by volume of the noble gas(es). For the embodiment of the invention illustrated in Figs. 2, 6, 8 and 10, the protective layers 22a, 22b, 22c and 22d protect the corners 16g of the etched elecfrode layers 16a, 16b, 16c and 16d during the etching process. Typically and as best shown in Figs. 11 and 12, some of the mask layers 18a, 18b, 18c and 18d would be etched during the etching process, leaving residual mask layers 18r on top of etched electrode layers 16a, 16b, 16c and 16d, or on top of the protective layers 22a, 22b, 22c and 22d. The protective layers 22a, 22b, 22c and 22d, respectively, insure that the corners 16g of the etched electrode layers 16a, 16b, 16c and 16d are protected during etching, especially in the event that the etching process removes essentially all of the mask layers 18a, 18b, 18c and 18d. Maintaining the corners 16g of the etched elecfrode layers 16a, 16b, 16c and 16d protects the quality of the profile formed during etching of the electrode layer 16 to produce the etched electrode layers 16a, 16b, 16c and 16d.
After the elecfrode layer 16 has been etched to produce the elecfrode layers 16a, 16b, 16c and 16d, the residual mask layers 18r (if not completely removed during the etching process) typically remain on top of the veil-less etched electrode layers 16a, 16b, 16c and 16d, or on top of the protective layers 22a, 22b, 22c and 22d which are respectively supported by the essentially veil-less etched electrode layers 16a, 16b, 16c and 16d, all as best shown in Figs. 11 and 12. The residual mask layers 18r are to be removed by any suitable means and/or in any suitable manner, such as by CHF3/Ar plasma. Likewise for the embodiment of the invention depicted in Fig. 12, the protective layers 22a, 22b, 22c and 22d are to be removed after removal of the residual mask layers 18r from the protective layers 22a, 22b, 22c and 22d. The protective layers 22a, 22b, 22c and 22d may be removed by any suitable means and/or in any suitable manner. For example, when the protective layers 22a, 22b, 22c and 22d comprise TiN removal is by Ar/Cl2 plasma in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following apparatus and process conditions as listed in Table XVIII below. TABLE XVπi
Process Broad Preferred Optimum
Gas Flow, seem
Cl2 20 to 150 30 to 120 40 to 100
Ar 20 to 100 30 to 80 40 to 60
Pressure, mT 0.5 to 40 4 to 30 7 to 14
RF Power of Coil
Inductor (Watts) 500 to 3000 500 to 2000 800 to 1200
RF Power of Wafer
Pedestal (Watts) 50 to 500 50 to 300 50 to 150
Temperature of Wafer (°C) 20 to 500 20 to 150 80 to 130
TiN Etch Rate (A/min) 500 to 5000 1000 to 3500 1500 to 2500
RF Frequency of Coil
Inductor 100 Kto 300 MHz 400 Kto 20 MHz 2 to 13.5 MHz
RF Frequency of Wafer
Inductor 100 Kto 300 MHz 400 Kto 20 MHz 400 K to 13.5 MHz
After removal of residual mask layers 18r, or the residual mask layers 18r and the protective layers 22a, 22b, 22c and 22d for the embodiment of the invention illustrated in Fig. 12, the veil-less etched elecfrode layered structure of Fig. 13 or Fig. 14 remains. It should be noted, as best shown in Figs. 15 and 16, respectively, that the barrier layer 14 could be etched simultaneously during or after removal of the residual mask layers 18r (see Fig. 15), or etched simultaneously during or after removal of the residual mask layers 18r and the protective layers 22a, 22b, 22c and 22d (see Fig. 16). It is to be understood that the patterned resist 20 (i.e., resist members 20a,
20b, 20c and 20d ) for the embodiment of the invention depicted in Fig. 1, or the patterned resist 20 (i.e., resist numbers 20a, 20b, 20c and 20d ) and/or the mask layers 18a, 18b, 18c and 18d for the embodiment of the invention depicted in Fig. 2, may be removed at any suitable time, preferably before the etching of the electrode layer 16. Similarly, the protective layers 22a, 22b, 22c and 22d and/or mask layers 18a, 18b, 18c and 18d for the embodiment of the invention depicted in Fig. 2, may also be removed at any suitable time, such as during the etching process or after the etching process. In another prefened embodiment of the present invention, the wafer 10 of Fig. 2 is provided with the semiconductor substrate 12, the banier layer 14 (e.g., TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, etc.) and the protective layer 22 comprising a compound selected from the group consisting of TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, and mixtures thereof, and the mask layer 18 selected from the group consisting of CVD SiO2, TEOS, Si3N4, BSG, PSG, BPSG, a low dielecfric constant material with a low dielectric constant of less than about 3.0, and mixtures thereof. The elecfrode layer 16 is a noble metal such as Pt, Ir, Pd, and Ru, or any oxide or alloy of a noble metal. This multilayered structure is initially placed in a suitable plasma processing apparatus to selectively break through and etch away from the surface of the elecfrode layer 16, the mask layer 18 except those mask layers 18a, 18b, 18c and 18d that are respectively below the resist members 20a, 20b, 20c and 20d as best shown in Fig. 6. The plasma for any suitable plasma processing apparatus may employ any suitable etchant gas.
After the mask layers 18a, 18b, 18c and 18d have been produced as shown in Fig. 6, the resist members 20a, 20b, 20c and 20d are removed in accordance with any of the previously mentioned procedures such that masking and etching sequence of Fig. 26 may be conducted. As best shown in Fig. 26, after removal of the resist 20 (i.e., resist members 20a, 20b, 20c and 20d, the protective layer 22 and the elecfrode layer 16 are etched. Preferably, etching continues into the barrier layer 14. Stated alternatively, etching stops in the barrier layer 14. Subsequently, the mask layers 18a, 18b, 18c and 18d are selectively removed, preferably without etching the barrier layer 14. The protective layers 22a, 22b, 22c and 22d are then removed, and the remaining part of the barrier layer 14 is thereafter etched with the etching process stopping in the subsfrate 12. Continuing to refer to Fig. 26 for a more particular explanation of the masking and etching sequence for this prefened embodiment of the invention, the protective layer 22 may be selectively etched in accordance with any of the previously mentioned procedures such as with a Cl2/HBr and/or BCl3/Ar gas chemistry in the same plasma processing apparatus that selectively etched the mask layer 18. Alternatively, and as was previously mentioned, the protective layer 22 may be selectively etched in the same chamber and under the same conditions for etching the elecfrode layer 16, i.e., in a high density plasma chamber containing a high density inductively coupled plasma. Etching of the protective layer 22 produced protective layers 22a, 22b, 22c and 22d. If the protective layer 22 is etched in accordance with the same procedure(s) for etching the elecfrode layer 16, the resist members 20a, 20b, 20c and 20d are initially removed before etching because they cannot be exposed to the high temperature (i.e., > 150°C) processing conditions for etching the electrode layer 16.
Subsequent to selectively etching the protective layer 22, the exposed parts of the electrode layer 16 are etched in accordance with any of the methods (e.g., the temperature of the wafer 10 is greater than about 150°C) and any of the etchant gases of any of the embodiments of the present invention to produce elecfrode layers 16a, 16b, 16c and 16d and expose selective parts of the banier layer 14. The electrode layer 16 may be etched not only in a high density plasma but also in a low density plasma. The mask layers 18a, 18b, 18c and 18d are then removed in any suitable plasm processing apparatus employing a plasma of any suitable etchant gas.
After removal of the mask layers 18a, 18b, 18c and 18d, the protective layers 22a, 22b, 22c and 22d are then removed in accordance with any suitable procedure and process conditions. Subsequently, and as best shown in Fig. 26, the barrier layer 14 is then etched through and the etching process ceases in the substrate 12. The foregoing sequences may be performed on the semiconductor wafer 10 of Fig. 1 (i.e., a wafer without the protective layer 22). All reactors and process conditions for conducting the foregoing mask and etching sequence may be any suitable reactors and process conditions.
Referring now to Fig. 27 for another embodiment of the present invention, the etching sequence is the same as for Fig. 26 except instead of etch-stopping in the barrier layer 14 before removal of the mask layer 18, etching continues into the substrate 12. After etching into the subsfrate 12, the mask layer 18 and the protective layer 22 are respectively removed, preferably without etching any further into the substrate 12. The barrier layer 14 and the protective layer 22 may be any one of the same compounds for the barrier layer 14 and the protective layer 22 for the embodiment of the invention illusfrated in Fig. 26. The mask layer 18 is preferably selected from the group consisting of Si3N , BSG, PSG, BPSG, a low dielectric constant (k) material with a dielectric constant less than about 3.0, and mixtures thereof. All reactors and process conditions for conducting the foregoing sequences may be any suitable reactors and process conditions, including the conditions where the temperature of the subsfrate 12 is greater than about 150°C and where the etchant gases may be any of the etchant gases of any of the embodiments of the present invention. The foregoing sequences may be performed on the semiconductor wafer 10 of Fig. 1 (i.e., a wafer without the protective layer 22).
Referring now to Fig. 28 for another embodiment of the present invention, there is seen the semiconductor wafer 10 of Fig. 25 having the etch-stop layer 17 (e.g., Si3N , TiO2, RuO2, IrO2). The etching sequence comprises respectively etching through the protective layer 22, the elecfrode layer 16, and the banier layer 14. The etching sequence stops in the etch-stop layer 17. Subsequently, the mask layer 18 is selectively removed, preferably without etching the etch-stop layer 17, and then the protective layer 22 is removed. The etch-stop layer 17 may be left intact or etched down to the substrate 12. The barrier layer 14 and the protective layer 22 may be any one of the same compounds for the barrier layer 14 and the protective layer 22 for the embodiment of the invention in Fig. 26. For this embodiment of the invention, the mask layer 18 is preferably selected from the group consisting of CVD SiO2, TEOS, BSG, PSG, BPSG, a low dielectric constant material with a dielecfric constant of less than about 3.0 and mixtures thereof. All reactors and process conditions for conducting the foregoing sequences may be any suitable reactors and process conditions, including the conditions where the temperature of the subsfrate 12 is greater than about 150°C and where the etchant gases may be any of the etchant gases of any of the embodiments of the present invention. The foregoing sequences may be performed on the semiconductor wafer 10 without the protective layer 22.
In another prefened embodiment of the invention as best shown in Fig. 29, there is seen the semiconductor wafer 10 having mask layer 18a and mask layer 18b. The ratio of the combined thicknesses of mask layer 18a and mask layer 18b (i.e., thickness of mask layer 18a plus thickness of mask layer 18b) to the thickness of the electrode layer 16 ranges from about 0.2 to about 5.0, preferably from about 0.5 to about 4.0, more preferably from about 1.0 to about 3.0. Stated alternatively, the ratio (thickness of mask layer 18a plus thickness of mask layer 18b)/thickness of elecfrode layer 16 ranges from about 0.2 to about 5.0, preferably from about 0.5 to about 4.0, more preferably from about 1.0 to about 3.0. Mask layer 18a is preferably composed of a compound selected from the group consisting of Si3N4, BSG, PSG, BPSG, an organic polymer, a low dielectric constant material with a dielectric constant of less than about 3.0 and mixtures thereof. A suitable organic polymer has been determined to be an organic polymer sold by Dow Chemical Co. of Midland, MI, under the registered frademark SiLK®. Mask layer 18b is preferably composed of a compound selected from the group consisting of CVD SiO2, TEOS, Si3N4, BSG, PSG, BPSG, and SiC. The barrier layer 14 and the protective layer 22 may be any one of the same compounds for the banier layer 14 and the protective layer 22 for the embodiment of the invention in Fig. 26. Mask layer 18b is initially removed, or optionally left in place, and the etch sequence includes: respectively etching through the protective layer 22, the electrode layer 16, and the banier layer 14. The etch sequence terminates in the subsfrate 12. Subsequently, mask layer 18b, or both mask layers 18a and 18b, are selectively removed, preferably without etching the subsfrate 12. Protective layer 22 is selectively removed from the etched elecfrode layer 22, preferably without etching subsfrate 12. The foregoing sequences may be performed on the semiconductor wafer 10 without the protective layer 22. All reactors and process conditions for conducting the foregoing sequences for this embodiment of the invention may be any suitable reactor and process conditions, including the conditions where the temperature of the subsfrate 12 is greater than about 150°C and where the etchant gases may be any of the etchant gases of any of the embodiments of the present invention. Thus, by the practice of the prefened embodiment of the inventions in Figs. 26-29, there is provided masking and etch sequences. The respective layer thickness(es) and composition(s) for the individual layers are given in the following Table XIX. It is to be understood that whenever "elecfrode layer 16" is mentioned for any of the embodiments of the present invention, "electrode layer 16" would include the combination of one or more layer(s) with each layer respectively comprising a noble metal and/or an oxide(s) of one or more noble metal and/or an alloy(s) of one or more noble metal(s). Thus, by way of example only, "elecfrode layer 16" could comprise the combination of a layer of platinum, a layer of ruthenium disposed on the layer of platinum, and a layer of iridium oxide disposed on the layer of ruthenium. It is to be similarly understood that whenever "thickness of elecfrode layer 16" is mentioned for any of the embodiments of the present invention, the "thickness of electrode layer 16" would include the summation of the respective thicknesses of all layer(s) that form the "elecfrode layer 16." Thus, by way of example only, if "elecfrode layer 16" comprises the combination of a layer of platinum having a thickness of 300A, a layer of iridium having a thickness of 500A, and a layer of iridium dioxide having a thickness of 20θA, the thickness of the electrode layer 16 would be 1,000A (i.e., 30θA + 50θA + 200 A).
Figure imgf000092_0001
The invention will be illusfrated by the following set forth example which s being given to set forth the presently known best mode and by way of illusfration only and not by way of any limitation. All parameters such as concentrations, mixing proportions, temperatures, pressure, rates, compounds, etc., submitted in this example are not to be construed to unduly limit the scope of the invention.
Example I A test semiconductor wafer was formulated with the following film stack:
0.8 μm patterned PR (photoresist)/500θA Oxide/100 A Ti/IOOOA Pt/30θA TiN
The feature size of the patterned PR test semiconductor wafer was 0.3 μm block and 0.25 μm spacing. The oxide mask (i.e., the mask layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the frademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening the oxide mask comprised about 68% by volume Ar and about 32% by volume CHF3. The reactor and process conditions were as follows: Reactor Conditions
Pressure 60 mTon
RF Power 850 watts
Rotational Magnetic Field 40 Gauss
Temperature of Test Wafer 100 °C
Oxide Mask Etch Rate 3000 A/min
Process Conditions Based on the Flow Rate of Ar and CHF3
CHF3 50 seem
Ar 100 seem
Pressure, mTon 60 mTon
RF Power Density 850 watts
Temperature (°C) of Test Wafer 100 °C
Oxide Mask Etch Rate (A/min) 3000 A/min
Magnetic Field (Gauss) 40 Gauss
The photoresist was stripped from the oxide mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2/N2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O2, 300 seem N2, and 2 Ton. The Ti protective layer was etched with Ar, Cl2 and BC13 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
Ti Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl? and BC13
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
Ti Etch Rate 2000 A/min
The platinum layer of the test semiconductor wafer was then etched with Ar and Cl2 as the etchant gas and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 150 watts
Temperature of Test Wafer 260 °C
Platinum Etch Rate 1500 A/min
Process Conditions Based on the Flow Rate of Ar and Cl?
Ar 40 seem
Cl2 60 seem
Pressure, mTon 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 150 watts
Temperature (°C) of Test Wafer 260 °C
Pt Etch Rate (A/min) 1500 A/min
Selectivity of Pt/Oxide Mask 1:1 The resulting etched platinum layer of the test semiconductor wafer is shown in Fig. 19 wherein a platinum profile of about 87 degrees is shown.
The oxide mask was then removed in a 6: 1 FJF solution to produce the veil-less test semiconductor wafer shown in Fig. 20. The remaining Ti protective layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC13 and Cl2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C Ti Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar. Cl? and BCk
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C Ti Etch Rate 2000 A min
Exan nple II
A test semiconductor wafer was formulated with the following film stack: 0.8 μm patterned PR (photoresist)/500θA Oxide/60θA TiN/200θA Pt/300A TiN The feature size of the patterned PR test semiconductor wafer was 0.25 μm block and 0.2 μm spacing. The oxide mask (i.e., the mask layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the frademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening the oxide mask comprised about 68% by volume Ar and about 32% by volume CHF3. The reactor and process conditions were as follows: Reactor Conditions
Pressure 60 mTon
RF Power 850 watts
Rotational Magnetic Field 40 Gauss
Temperature of Test Wafer 100 °C
Oxide Mask Etch Rate 3000 A/min
Process Conditions Based on the Flow Rate of Ar and CHF3
CHF3 50 seem
Ar 100 seem
Pressure, mTon 60 mTon
RF Power Density 850 watts
Temperature (°C) of Test Wafer 100 °C
Oxide Mask Etch Rate (A/min) 3000 A/min
Magnetic Field (Gauss) 40 Gauss
The photoresist was stripped from the oxide mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2 2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O2, 300 seem N2, and 2 Ton.
The TiN protective layer was etched with Ar, Cl2 and BC13 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
TiN Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl? and BC13
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
TiN Etch Rate 2000 A/min
The platinum layer of the test semiconductor wafer was then etched with Ar and Cl2 and BC13 as the etchant gas and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 150 watts
Temperature of Test Wafer 260 °C
Platinum Etch Rate 1500 A/min Process Conditions Based on the Flow Rate of Ar and Cl? and BGU
Ar 40 seem
Cl2 60 seem
BC13 10 seem
Pressure, mTon 12 mTon RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 150 watts
Temperature (°C) of Test Wafer 260 °C
Pt Etch Rate (A min) 1500 A/min
Selectivity of Pt/Oxide Mask 1 : 1 The resulting etched platinum layer of the test semiconductor wafer is shown in Fig. 23 wherein a platinum profile of about 87 degrees is shown.
The oxide mask could have been removed in a 6: 1 HF solution to produce a veil-less test semiconductor wafer similar to the one shown in Fig. 20. The remaining TiN protective layer could have been removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC13 and Cl2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
TiN Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl? and BCk
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
TiN Etch Rate 2000 A/min
Example III A test semiconductor wafer was formulated with the following film stack:
1.2 μm patterned PR (photoresist)/500θA TEOS/200A TiN/250θA Pt/300A TiN/50θA SiN.
The feature size of the patterned PR test semiconductor wafer was 0.35 μm line and 0.35 μm spacing. The TEOS mask (i.e., the mask layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the trademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening the TEOS mask comprised about 68% by volume Ar and about 32% by volume CHF3. The reactor and process conditions were as follows: Reactor Conditions
Pressure 60 mTon
RF Power 850 watts
Rotational Magnetic Field 40 Gauss
Temperature of Test Wafer 100 °C
TEOS Mask Etch Rate 3000 A/min
Process Conditions Based on the Flow Rate of Ar and CHF3
CHF3 50 seem
Ar 100 seem
Pressure, mTon 60 mTon
RF Power Density 850 watts
Temperature (°C) of Test Wafer 100 °C
TEOS Mask Etch Rate (A/min) 3000 A/min
Magnetic Field (Gauss) 40 Gauss
The photoresist was stripped from the TEOS mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2/N2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O2, 300 seem N2, and 2 Ton. The TiN protective layer was etched with Ar, Cl2 and BC13 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
TiN Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl? and BC13
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
TiN Etch Rate 2000 A/min
The platinum layer of the test semiconductor wafer was then etched with Ar, Cl2, BC13 and N2 as the etchant gas and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 36 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 300 watts
Temperature of Test Wafer 320 °C
Platinum Etch Rate 600 A/min
Process Conditions Based on the Flow Rate of Ar, Cl?, BC13 and N?
Ar 24 seem
Cl2 120 seem
BC12 10 seem
N2 30 seem
Pressure, mTon 36 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 300 watts
Temperature (°C) of Test Wafer 320 °C
Pt Etch Rate (A/min) 600 A/min
Selectivity of Pt/TEOS Mask 1:1
The TiN layer underneath the platinum layer was then etched with Ar, BC12 and N2 as the etchant gas and in a DPT™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions Pressure, mTon 36 mTon RF Power to Coil Inductor 900 watts RF Power to Wafer Pedestal 300 watts Temperature (°C) of Test Wafer 320 °C TiN Etch Rate 300 A/min
Process Conditions
Ar 100 seem
BC13 5 seem
N2 100 seem
Pressure, mTon 36 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 300 watts
Temperature (°C) of Test Wafer 320 °C
TiN Etch Rate 300 A/min
The TEOS mark was then removed in a 6:1 HF solution to produce a veil- free test semiconductor wafer shown in the picture of Fig. 30.
The remaining TiN protective layer on the etched platinum layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC13 and Cl2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
TiN Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar. Cl? and BCl?
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
TiN Etch Rate 2000 A/min Example IN A test semiconductor wafer was formulated with the following film stack: 1.2 μm patterned PR (photoresist)/200θA TEOS/8000A SiLK®/200θA Pt/30θA TiΝ/SiO2 substrate.
The feature size of the patterned PR test semiconductor wafer was 0.35 μm line and 0.35 μm spacing. SiLK® is a registered frademark of Dow Chemical Co. of Midland, Michigan 48674. It is a high temperature organic polymer. It is disposed on the Pt layer by the spin coating method. The TEOS mask (i.e., the first mask layer) was etched with Ar, CF4 and
CHF3 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 10 mTon
RF Power to Coil Inductor 1500 watts
RF Power to Wafer Pedestal 400 watts
Temperature of Test Wafer 80 °C
TEOS Etch Rate 4500 A/min
Process Conditions Based on the Flow Rate of Ar and CF? and CHF3
Ar 100 seem
CF4 20 seem
CHF3 60 seem
Pressure 10 mTon
RF Power to Coil Inductor 1500 watts
RF Power to Wafer Pedestal 400 watts
Temperature of Test Wafer 80 °C
TEOS Etch Rate 4500 A/min
The SiLK brand layer (i.e., the second mask layer) of the test semiconductor wafer was then etched (which also completely etched away the patterned PR) with NH3 as the etchant gas in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 10 mTon
RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 400 watts
Temperature of Test Wafer 80 °C
SiLK® Etch Rate 3000 A/min
Process Conditions Based on the Flow Rate of NFU
NH3 50 seem
Pressure, mTon 10 mTon
RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 400 watts
Temperature (°C) of Test Wafer 80 °C
SiLK® Etch Rate (A/min) 3000 A/min
The results are shown in Fig. 31. The platinum layer was then etched with Ar, BC12, Cl2 and N2 as the etchant gas and in a DPT™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
Pressure, mTon 32 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 400 watts
Temperature (°C) of Test Wafer 310 °C
Pt Etch Rate 600 A/min
Process Conditions
Ar 30 seem
BC13 10 seem
Cl2 120 seem
N2 30 seem
Pressure, mTon 32 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 400 watts
Temperature (°C) of Test Wafer 310 °C
Pt Etch Rate 600 A/min
The TiN layer (i.e., a barrier layer) underneath the Pt layer is also etched with the same etchant gases and in the same DPS chamber and same reactor and process conditions after Pt etching. The result is shown in Figure 32.
The remaining SiLK® brand mask was stripped from the Pt layer in an ASP chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2/N2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O2, 300 seem N2, and 2 Ton. Fig. 33 shows the final result of etching Pt layer after the SiLK® brand mask was removed. Fig. 34 is a top plan view picture of the etched platinum layer of Fig. 33.
Example V A test semiconductor wafer was formulated with the following film stack: 0.8 μm PR (photoresist)/700θA Oxide/20θA Ti/300θA Pt/30θA TiN/Si3N4
The feature size of the formulated test semiconductor wafer was 0.27 μm block and 0.13 μm spacing. The oxide hard mask (i.e., the insulation layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the trademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening up the oxide hard mask comprised about 68% by volume Ar and about 32% by volume CHF3. The reactor and process conditions were as follows:
Reactor Conditions
Pressure 60 mTon
RF Power 850 watts
Rotational Magnetic Field 40 Gauss
Temperature of Test Wafer 100 °C
Oxide Hard Mask Etch Rate 3000 A/min
Process Conditions Based on the Flow Rate of Ar and CHF3
CHF3 50 seem Ar 100 seem
Pressure, mTon 60 mTon
RF Power Density 850 watts
Temperature (C) of Test Wafer 100 °C
Oxide Mask Etch Rate (A/min) 3000 A/min Magnetic Field (Gauss) 40 Gauss
The photoresist was stripped from the oxide hard mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2/N2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O2, 300 seem N2, and 2 Ton. The Ti protective layer was etched with Ar, Cl2 and BC13 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 325 °C
Ti Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl? and BC
Ar 40 seem
Cla 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 325 °C
Ti Etch Rate 2000 A min The platinum layer of the test semiconductor wafer was then etched with N2,
Ar and Cl2 as the etchant gas and in a DPS™ brand chamber of the Metal Etch DPS
Centura™ brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
Pressure 36 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 300 watts
Temperature of Test Wafer 325 °C Platinum Etch Rate 800 A/min
Process Conditions Based on the Flow Rate of N? Ar and Cl?
N2 30 seem
Ar 24 seem Cl2 120 seem
Pressure, mTon 36 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 300 watts
Temperature (C) of Test Wafer 325 °C Pt Etch Rate (A/min) 800 A/min
Selectivity of Pt Oxide Hard Mask 1.5:1
The resulting etched platinum layer of the test semiconductor wafer is shown in the photograph picture of Fig. 37 wherein a platinum profile of about 88 degrees is shown. Fig. 38 is a drawing representing the photograph of Fig. 37 with the respective parts identified by a reference numeral.
The oxide hard mask could have been removed in a 6:1 HF solution to produce the veil-less test semiconductor wafer similar to the one shown in Fig. 20. The remaining Ti protective layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC13 and Cl2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
Ti Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl? and BCU
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
Ti Etch Rate 2000 A/min
Exar nple VI
A test semiconductor wafer was formulated with the following film stack: 0.8 μm PR (photoresist)/500θA Oxide/IOOA TiN/150θA Pt 30θA TiN/Si3N4 The feature size of the formulated test semiconductor wafer was 0.3 μm block and 0.2 μm spacing. The oxide hard mask (i.e., the insulation layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the frademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening up the oxide hard mask comprised about 68% by volume Ar and about 32% by volume CHF3. The reactor and process conditions were as follows:
Reactor Conditions
Pressure 60 mTon
RF Power 850 watts
Rotational Magnetic Field 40 Gauss
Temperature of Test Wafer 100 °C
Oxide Hard Mask Etch Rate 3000 A/min
Process Conditions Based on the Flow Rate of Ar and CHF3
CHF3 50 seem
Ar 100 seem
Pressure, mTon 60 mTon
RF Power Density 850 watts
Temperature (°C) of Test Wafer 100 °C
Oxide Mask Etch Rate (A/min) 3000 A/min Magnetic Field (Gauss) 40 Gauss
The photoresist was stripped from the oxide hard mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2/N2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O2, 300 seem N2, and 2 Ton.
The TiN protective layer was etched with Ar, Cl2 and BC13 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 325 °C
TiN Etch Rate 2000 A min
Process Conditions Based on the Flow Rate of Ar and Cl? and BC13
Ar ■ 40 seem
Cl2 30 seem
BC13 30 seem Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 325 watts
Temperature of Test Wafer 325 °C
TiN Etch Rate 2000 A/min The platinum layer of the test semiconductor wafer was then etched with N2 and Cl2 as the etchant gas and in a parallel plate RIE low density plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 100 mTon RF Power to Wafer Pedestal 1000 watts
Temperature of Test Wafer 325 °C
Platinum Etch Rate 1000 A/min
Process Conditions Based on the Flow Rate of N?, and Cl? N2 80 seem
Cl2 200 seem
Pressure, mTon 100 mTon
RF Power to Wafer Pedestal 1000 watts
Temperature (°C) of Test Wafer 325 °C Pt Etch Rate (A/min) 1000 A/min
Selectivity of Pi/Oxide Hard Mask 0.5:1
The resulting etched platinum layer of the test semiconductor wafer is shown in Fig. 39 wherein a platinum profile of about 85 degrees is shown. Fig. 40 is a drawing representing the photograph picture of Fig. 39 with the respective parts identified by a reference numeral.
The oxide hard mask could have been removed in a 6:1 HF solution to produce the veil-less test semiconductor wafer similar to the one shown in Fig. 20. The remaining TiN protective layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC13 and Cl2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
TiN Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl? and BC
Ar 40 seem
Cl2 30 seem
BC13 30 seem Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
TiN Etch Rate 2000 A/min
Example Nil A test semiconductor wafer was formulated with the following film stack: 0.8 μm PR (photoresist)/500θA Oxide/IOOA Ti/200θA Pt/30θA TiΝ The feature size of the formulated test semiconductor wafer was 0.3 μm block and 0.25 μm spacing. The oxide hard mask (i.e., the insulation layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the trademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening up the oxide hard mask comprised about 68% by volume Ar and about 32% by volume CHF3. The reactor and process conditions were as follows:
Reactor Conditions Pressure 60 mTon
RF Power 850 watts
Rotational Magnetic Field 40 Gauss
Temperature of Test Wafer 100 °C
Oxide Hard Mask Etch Rate 3000 A/min Process Conditions Based on the Flow Rate of Ar and CHF3
CHF3 50 seem
Ar 100 seem
Pressure, mTon 60 mTon
RF Power Density 850 watts Temperature (C) of Test Wafer 100 °C
Oxide Mask Etch Rate (A/min) 3000 A min
Magnetic Field (Gauss) 40 Gauss
The photoresist was stripped from the oxide hard mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2/N2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O2, 300 seem N2, and 2 Ton.
The Ti protective layer was etched with Ar, Cl2 and BC13 as the etchant gases and in a DPS™ brand chamber of a Metal Etch DPS Centura™ brand plasma processing apparatus sold by Applied Materials, Inc. The Ti protective layer was etched under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
Ti Etch Rate 2000 A min Process Conditions Based on the Flow Rate of Ar and Cl? and BC13
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
Ti Etch Rate 2000 A/min The platinum layer of the test semiconductor wafer was then etched in a
DPS™ brand chamber of a Metal Etch DPS™ brand plasma processing apparatus. The DPS™ brand chamber included an etch chamber and a generally hemispherical shaped standard dome (i.e., dielectric ceiling 62 having inside concave surface 62a) as shown in Fig. 41 manufactured of a dielectric aluminum oxide that was capable of allowing RF power to pass therethrough for being coupled to a plasma of an etchant gas. The hemispherical shaped standard dome (hereinafter "Standard Dome") covered the etch chamber as a lid as represented in Figs. 17 and 18 and sealed the chamber for pumping down to mTon vacuum pressure. The inside concave surface 62a of the dielectric ceiling 62 (i.e., the "Standard Dome") had a peak-to- valley roughness height with an average height value of about 500A. The inductive coils circled the outside of the hemispherical sloped dome and connected to a RF power supply. RF power energy delivered to the inductive coils were transmitted through the Standard Dome and into the DPS™ brand chamber and generated a high density plasma from a processing gas for processing the semiconductor test wafer. The platinum layer of the test semiconductor wafer was etched in the DPS™ brand chamber with BC13, Ar and Cl2 as the etchant gas under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 150 watts Temperature of Test Wafer 350 °C
Platinum Etch Rate 1000 A/min
Process Conditions Based on the Flow Rate of Ar. Cl? and BC13
Ar 30 seem Cl2 70 seem
BC13 10 seem
Pressure, mTon 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 150 watts Temperature (C) of Test Wafer 350 °C
Pt Etch Rate (A/min) 1000 A/min
Selectivity of Pt/Oxide Hard Mask 1 : 1 During the metal etching of the platinum layer of the semiconductor test wafer, a deposit 7 of materials occuned on the inside concave surface 62a of the Standard
Dome or ceiling 62, as best shown in Fig. 42. The deposit 7 included, by way of example only, oxides and silicates and chlorides of platinum, and was located between the plasma and the power source. The deposit 7 was conductive and had an electrical resistance of 10 to 20
M ohms measured with a DC ohm meter after etching 25 wafers.
Example Niπ
Example Nil was repeated with the platinum layer of the test semiconductor wafer etched with BC13, Ar, and Cl2 as the etchant gas and in the same DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 24 mTon RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 175 watts
Temperature of Test Wafer 350 °C
Platinum Etch Rate 1000 A/min Process Conditions Based on the Flow Rate of Ar, Cl? and BC13
Ar 20 seem
Cl2 100 seem
BC13 10 seem
Pressure, mTon 24 mTon RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 175 watts
Temperature (C) of Test Wafer 350 °C
Pt Etch Rate (A/min) 1000 A/min
Selectivity of Pt/Oxide Hard Mask 1 : 1
During the platinum etching of the platinum layer under the foregoing reactor and process conditions, a deposit 7a of platinum-containing materials occuned on the inside concave surface 62a of the Standard Dome or ceiling 62, as best shown in Fig. 42. The deposit 7a included, by way of example only, oxides, and nitrides and silicates and chlorides of platinum, etc. The deposit 7a was not conductive as measured with a DC ohm meter after etching 50 wafers. Thus, the use of high Cl2 flow and high pressure resulted in a deposit 7a that was less conductive than the deposit 7 in Example Nπ where the etching was done at low Cl2 content (i.e., low Cl2/Ar volume ratio) and low pressure. More Cl2 content (i.e., high Cl /Ar volume ratio) at high pressure promotes more chemical etching rather than physical sputtering at low pressure.
Example IX
Example Nil was repeated with a Modified Dome and with the platinum layer of the test semiconductor wafer etched with BC13, Ar and Cl2 as an etchant gas and in a DPS™ brand chamber of the Metal Etch DPS™ Centura™ brand plasma processing apparatus under the following reactor and process conditions: Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 150 watts
Temperature of Test Wafer 350 °C
Platinum Etch Rate 1000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl?
Ar 30 seem
Cl2 70 seem
BC13 10 seem
Pressure, mTon 12 mTon
RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 150 watts
Temperature (°C) of Test Wafer 350 °C
Pt Etch Rate (A/min) 1000 A/min
Selectivity of Pt Oxide Hard Mask 1:1
The Modified Dome for this Example IX used the Standard Dome (i.e., dielectric ceiling 62) but whose inside concave surface 62a had a surface finish comprising a peak-to-valley roughness height with an average height value of about 5000 A. During the platinum etching of the platinum layer under the above-identified conditions, the same deposit 7 from Example NH occuned on the inside concave surface 62a as illustrated in the exploded view of Fig.44. However, deposit 7 for this Example IX was not conductive as measured with a DC ohm meter after etching 100 wafers. Thus, the electric conductivity (and thickness) of the deposit 7 for this Example IX was less than deposit 7 from Example Nil because the inside concave surface 62a for the Modified Dome had a surface finish including a peak-to- valley roughness height with an average height value of about 5000 A, as opposed to the inside concave surface 62a for the Standard Dome in Example N which had a surface finish including a peak-to-valley roughness height with an average height value of about 500A. Using a roughen surface design on the dielectric ceiling increased the overall inside surface area that provided a larger surface area for the same volume of deposit 7, thus causing a decrease in the deposition thickness which would then extend the stability of external RF power transmission through the dielectric ceiling or window for etching platinum.
Example X
A test semiconductor wafer was formulated with the following film stack: 1.2 μm patterned PR (photoresist)/400θA Oxide/IOOA Ti/200θA Ir/IOOOA
TiΝ
The feature size of the patterned PR test semiconductor wafer was 2.5 μm block and 4.0 μm spacing. The oxide mask (i.e., the mask layer) was opened in the oxide etch chamber of a plasma processing apparatus sold under the trademark Oxide Etch MxP Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA
95054-3299. The etchant gas for opening the oxide mask comprised about 68% by volume
Ar and about 32% by volume CHF3. The reactor and process conditions were as follows:
Reactor Conditions
Pressure 60 mTon RF Power 850 watts
Rotational Magnetic Field 40 Gauss
Temperature of Test Wafer 100 °C
Oxide Mask Etch Rate . 3000 A/min
Process Conditions Based on the Flow Rate of Ar and CHF3
CHF3 50 seem
Ar 100 seem
Pressure, mTon 60 mTon
RF Power Density 850 watts Temperature (C) of Test Wafer 100 °C
Oxide Mask Etch Rate (A/min) 3000 A/min
Magnetic Field (Gauss) 40 Gauss
The photoresist was stripped from the oxide mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2/N2 plasma: 120 seconds, 250° C, 1400 W, 3000 seem O2,
300 sccmN2, and 2 Ton.
The Ti protective layer was etched with Ar, Cl2 and BC1 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110 °C
Ti Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl? and BC13
Ar 40 seem Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts Temperature of Test Wafer 110 °C
Ti Etch Rate 2000 A/min
The iridium layer of the test semiconductor wafer was then etched with O2, Ar and Cl2 as the etchant gas and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 450 watts
Temperature of Test Wafer 300 °C
Iridium (Ir) Etch Rate 600 A/min
Process Conditions Based on the Flow Rate of O?, Ar and Cl?
O2 15 seem
Ar 100 seem
Cl2 50 seem
Pressure, mTon 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 450 watts
Temperature (°C) of Test Wafer 300 °C Ir Etch Rate (A/min) 600 A/min
Selectivity of Ir/Oxide Mask 2: 1
The resulting etched iridium layer of the test semiconductor wafer is shown in the picture of Fig. 45 wherein an iridium profile of about 85 degrees is shown. Fig.46 is a drawing representing the elevational view in the picture of Fig. 45 with the respective parts identified. by a reference numeral..
The oxide mask was then removed in a 6: 1 HF solution to produce the veil- less test semiconductor wafer. The remaining Ti protective layer could be removed by any suitable means and/or in any suitable manner, such as by etching with Ar, BC13 and Cl2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
Ti Etch Rate 2000 A/min
Process Conditions Based on fhe Flow Rate of Ar. Cl?. BCk
Ar 40 seem
Cl2 30 seem
BC13 30 seem
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
Ti Etch Rate 2000 A/min
Exar nple XI
A test semiconductor wafer was formulated with the following film stack:
1.2 μm patterned PR (photoresist)/ 1000 A TiN/200θA Ir/IOOOA TiN
The feature size of the patterned PR test semiconductor wafer was 2.5 μm block and 4.0 μm spacing. The TiN mask (i.e., the mask layer) was opened in the metal etch chamber of a plasma processing apparatus sold under the trademark Metal Etch DPS
Centura™, owned by Applied Materials Inc., 3050 Bowers Avenue, Santa Clara, CA 95054-3299. The etchant gas for opening the TiN mask comprised about 68% by volume Ar and about 32% by volume Cl2. The reactor and process conditions were as follows:
Reactor Conditions .
Pressure 12 mTon
RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
TiN Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl?
Ar 100 seem
Cl2 50 seem
Pressure 12 mTon RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110 °C
TiN Etch Rate 2000 A/min
The photoresist was stripped from the oxide mask in an ASP chamber of the Metal Etch MxP Centura™ brand plasma processing apparatus under the following recipe using microwave downstream O2/N plasma: 120 seconds, 250° C, 1400 W, 3000 seem O , 300 sccmN2, and 2 Ton.
The iridium layer of the test semiconductor wafer was then etched with O2 Ar and Cl2 as the etchant gas and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions
Pressure 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 450 watts
Temperature of Test Wafer 320 °C
Iridium Etch Rate 600 A/min
Process Conditions Based on the Flow Rate of O? and Ar and Cl?
O2 15 seem
Ar 100 seem
Cl2 50 seem
Pressure, mTon 12 mTon
RF Power to Coil Inductor 900 watts
RF Power to Wafer Pedestal 150 watts Temperature (C) of Test Wafer 320 °C
Iridium Etch Rate (A/min) 1500 A/min
Selectivity of Ir/TiN Mask 10:1
The remaining TiN mask layer could have been removed by any suitable means and/or in any suitable manner, such as by etching with Ar and Cl2 as the etchant gases and in a DPS™ brand chamber of the Metal Etch DPS Centura™ brand plasma processing apparatus under the following reactor and process conditions:
Reactor Conditions Pressure 12 mTon
RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
TiN Etch Rate 2000 A/min
Process Conditions Based on the Flow Rate of Ar and Cl?
Ar " 100 seem
Cl2 50 seem
Pressure 12 mTon RF Power to Coil Inductor 1200 watts
RF Power to Wafer Pedestal 100 watts
Temperature of Test Wafer 110° C
TiN Etch Rate 2000 A/min
The resulting etched iridium layer of the test semiconductor wafer is shown in Fig. 47 wherein an iridium profile of about 80 degrees is shown. Fig. 48 is a drawing representing the elevational view in the picture of Fig. 47 with the respective parts identified by a reference numeral.
Conclusion Thus, by the practice of the present invention there is provided a method for etching of the elecfrode layer 16 (e.g., platinum electrode layer 16 or iridium elecfrode layer 16). The etched electrode layer 16 includes a plurality of etched elecfrode layers 16a, 16b, 16c and 16d having a platinum profile where the angle °= of the sidewalls 16s with respect to a horizontal plane is equal to or greater than about 80 degrees, preferably equal or greater than about 85 degrees. The elecfrode layers 16a, 16b, 16c and 16d are separated by a distance or space having a dimension equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm. Each of the electrode layers 16a, 16b, 16c and 16d include a dimension having a value equal to or less than about 0.6 μm, preferably equal to or less than about 0.35 μm, more preferably equal to or less than about 0.3 μm. More preferably, each of the electrode layers 16a, 16b, 16c and 16d has a width equal to or less than about 0.35 μm, preferably equal to or less than about 0.3 μm, a length equal to or less than about 0.6 μm, and a height equal to or less than about 0.6 μm. Because the produced etched electrode layers 16a, 16b, 16c and 16d are essentially a "veil-less" with no "fences" or "rabbit ears," they are ideally suited for receiving a dielectric (e.g., a BST layer) in producing a semiconductor device. The etchant gas in Example I consisted of about 40% by vol. Ar and about 60% by vol. Cl2, and produced an etched platinum layer with a platinum profile of about 87 degrees. In Example II, the etchant gas consisted of 54.5% by vol. (about 55% by vol.) Cl2, 36.4% by vol. (about 36% by vol.) Ar, and 9.1% by vol. (about 9% by vol.) BC13, and the resulting etched platinum layer had a platinum profile of about 87 degrees. In Example X, the etchant gas consisted of about 9.1% by vol. 02, about 60.6% by vol. argon, and about 30.3% by vol. Cl2, and produced an etched iridium layer with an iridium profile of about 85 degrees. In Example XE, the etchant gas consisted of about 9.1% by vol. O2, about 60.6% by vol. argon, and about 30.3% by vol. Cl2, and produced an etched iridium layer with an iridium profile of about 80 degrees.
By the further practice of the present invention there is provided a method for etching a noble metal, and masking and etching sequences for patterning elecfrodes of high density RAM capacitors. One masking and etching sequence is to etch through a protective layer, an elecfrode layer, and into a banier layer before removing a mask layer and a protective layer. A pair of mask layers may be employed instead of only one mask layer. Optionally, etching may be through the barrier layer and into the subsfrate before removing a mask layer and a protective layer. Another masking and etching sequence comprises respectively etching through a protective layer, an elecfrode layer, a barrier layer and into a etch-stop layer before removing a mask layer and a protective layer. In Example III, the etchant gas for etching the protective layer, the elecfrode layer, and the barrier layer included Ar/Cl2/BCl3, Ar/Cl2/BCl3/N2 and Ar/BCl2/N2, respectively.
Thus, while the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosure, and it will be appreciated that in some instances some features of the invention will be employed without a conesponding use of other features without departing from the scope and spirit of the invention as set forth. While some features of the subject invention have been described with platinum or iridium being the electrode layer, it is to be understood that the spirit and scope of the present invention would include the use of other noble metal(s) and/or noble metal oxide(s) and/or alloy(s) of noble metal(s) (e.g., iridium, iridium oxide (IrO2), ruthenium, ruthenium oxide (RuO2), palladium, palladium oxide, platinum alloy (s), rhodium, etc.) instead of platinum or iridium under the identical disclosed conditions employing the identical parameters. Therefore, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular embodiment(s) disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments and equivalents falling within the scope of the appended claims.

Claims

WHAT IS CLAIMED IS:
1. A method of etching a noble metal layer disposed on a substrate comprising the steps of: a) providing a subsfrate supporting a barrier layer, a noble metal layer on said barrier layer, a protective layer on said noble metal layer, a mask layer on said protective layer, and a patterned resist layer on said mask layer; b) etching a portion of said mask layer including employing a plasma of a mask etchant gas to break through and to remove said portion of said mask layer from said protective layer to expose part of said protective layer and to produce said subsfrate supporting said barrier layer, said noble metal layer on said barrier layer, said protective layer on said noble metal layer, a residual mask layer on said protective layer, and said patterned resist layer on said residual mask layer; c) removing said patterned resist layer from said residual mask layer of step (b) to produce said substrate supporting said barrier layer, said noble metal layer on said banier layer, said protective layer on said noble metal layer, and said residual mask layer on said protective layer; d) etching said exposed part of said protective layer to expose part of said noble metal layer and to produce said subsfrate supporting said banier layer, and said noble metal layer on said banier layer, a residual protective layer on said noble metal layer, and said residual mask layer on said residual protective layer; e) heating said subsfrate of step (d) to a temperature greater than about 150°C; f) etching said exposed part of said noble metal layer of step (d) including employing a plasma of an etchant gas selected from the group consisting of a halogen containing gas, a noble gas, nifrogen, oxygen, and mixtures thereof, to produce said subsfrate supporting said barrier layer, an etched noble metal layer on said barrier layer, said residual protective layer on said etched noble metal layer, and said residual mask layer on said residual protective layer; g) removing said residual mask layer from said residual protective layer to produce said substrate supporting said barrier layer, said etched noble metal layer on said barrier layer, and said residual protective layer on said etched noble metal layer; and
h) etching a portion of said barrier layer including employing a plasma of a barrier etchant gas to expose part of the subsfrate to produce said subsfrate supporting a residual banier layer, said etched noble metal layer on said residual barrier layer, and said residual protective layer on said etched noble metal layer.
2. The method of Claim 1 wherein said step (f) etching of said noble metal layer of step (d) additionally produces a remaining noble metal layer on said banier layer, said step (g) removing of said residual mask layer additionally produces said remaining noble metal layer on said banier layer, and said method additionally comprises etching said remaining noble metal layer on said barrier layer prior to said step (h) etching.
3. The method of Claim 1 additionally comprising removing said residual protective layer from said etched noble metal layer.
4. The method of Claim 1 wherein said step (f) etching of said noble metal layer of step (d) additionally produces a remaining noble metal layer on said banier layer, said step (g) removing of said residual mask layer additionally produces said remaining noble metal layer on said banier layer, and said method additionally comprises etching said residual protective layer and said remaining noble metal layer on said barrier layer prior to said step (h) etching.
5. The method of Claim 3 wherein said removing of said residual protective layer from said etched noble metal is simultaneous with said etching step (h).
6. The method of Claim 1 wherein said mask layer comprises CND SiO2.
7. The method of Claim 2 wherein said mask layer and said subsfrate comprises CND SiO2. The method of Claim 4 wherein said mask layer comprises CND
SiO2.
9. The method of Claim 1 wherein said mask layer comprises a compound selected from the group consisting of TEOS, CND SiO2, Si3Ν4, BSG, PSG, BPSG, a low dielectric constant material with a dielectric constant less than about 3.0, and mixtures thereof.
10. The method of Claim 1 wherein said barrier layer comprises a compound selected from the group consisting of TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, and mixtures thereof.
11. The method of Claim 1 wherein said protective layer comprises a compound selected from the group consisting of TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, and mixtures thereof.
12. The method of Claim 1 wherein said mask layer has a thickness ranging from about 6000A to about 9,OOθA.
13. A method of etching a noble metal layer disposed on a subsfrate comprising the steps of: a) providing a subsfrate supporting a barrier layer, a noble metal layer on said banier layer, a mask layer on said noble metal layer, and a patterned resist layer on said mask layer; b) etching a portion of said mask layer including employing a plasma of a mask etchant gas to break through and to remove said portion of said mask layer from said noble metal layer to expose part of said noble metal layer and to produce said subsfrate supporting said barrier layer, said noble metal layer on said barrier layer, a residual mask layer on said noble metal layer, and said patterned resist layer on said residual mask layer; c) removing said patterned resist layer from said residual mask layer of step (b) to produce said subsfrate supporting said barrier layer, said noble metal layer on said barrier layer, and said residual mask layer on said noble metal layer; d) heating said substrate of step (c) to a temperature greater than about 150°C; e) etching said exposed part of said noble metal layer of step (c) including employing a plasma of an etchant gas selected from the group consisting of a halogen containing gas, a noble gas, nifrogen, oxygen, and mixtures thereof, to produce said subsfrate supporting said barrier layer, an etched noble metal layer on said barrier layer, and said residual mask layer on said etched noble metal layer; f) removing said residual mask layer from said etched noble metal layer to produce said subsfrate supporting said barrier layer and said etched noble metal layer on said barrier layer; and g) etching a portion of said banier layer including employing . a plasma of a barrier etchant gas to expose part of the subsfrate to produce said substrate supporting a residual banier layer and said etched noble metal layer on said residual banier layer.
14. A method of etching a noble metal layer disposed on a subsfrate comprising the steps of: a) providing a substrate supporting a barrier layer, a noble metal layer on said barrier layer, a protective layer on said noble metal layer, a mask layer on said protective layer, and a patterned resist layer on said mask layer; b) etching a portion of said mask layer including employing a plasma of a mask etchant gas to break through and to remove said portion of said mask layer from said protective layer to expose part of said protective layer and to produce said subsfrate supporting said barrier layer, said noble metal layer on said barrier layer, said protective layer on said noble metal layer, a residual mask layer on said protective layer, and said patterned resist layer on said residual mask layer; c) removing said patterned resist layer from said residual mask layer of step (b) to produce said subsfrate supporting said barrier layer, said noble metal layer on said barrier layer, said protective layer on said noble metal layer, and said residual mask layer on said protective layer; d) etching said exposed part of said protective layer to expose part of said noble metal layer and to produce said substrate supporting said barrier layer, said noble metal layer on said barrier layer, a residual protective layer on said noble metal layer, said residual mask layer on said residual protective layer, and said patterned resist layer on said residual mask layer; e) heating said subsfrate of step (d) to a temperature greater than about 150°C; f) etching said exposed part of said noble metal layer of step (d) including employing a plasma of an etchant gas selected from the group consisting of a halogen containing gas, a noble gas, nifrogen, oxygen, and mixtures thereof, to produce said substrate supporting said barrier layer, an etched noble metal layer on said barrier layer, said residual protective layer on said etched noble metal layer, and said residual mask layer on said residual protective layer; g) etching a portion of said barrier layer including employing a plasma of a barrier etchant gas to expose part of the subsfrate to produce said substrate supporting a residual banier layer, said etched noble metal layer on said residual barrier layer, said residual protective layer on said etched noble metal layer, and said residual mask layer on said residual protective layer; and h) removing said residual mask layer from said residual protective layer to produce said substrate supporting said residual barrier layer, said etched noble metal layer on said residual banier layer, and said residual protective layer on said etched noble metal layer.
15. The method of Claim 14 wherein said barrier layer comprises a compound selected from the group consisting of TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, and mixtures thereof.
16. The method of Claim 14 wherein said protective layer comprises a compound selected from the group consisting of TiN, TiSiN, Ti, WN, TaN, TaSiN, Ta, and mixtures thereof.
17. The method of Claim 14 wherein said mask layer has a thickness ranging from about 6000A to a about 9,OOθA.
18. The method of Claim 14 wherein said mask layer comprises a compound selected from the group consisting of Si3N4, BSG, PSG, BPSG, a low dielectric constant material with a dielectric constant of less than about 3.0, and mixtures thereof.
19. A method of etching a noble metal layer disposed on a substrate comprising the steps of: a) providing a subsfrate supporting an etch-stop layer, a barrier layer on said etch-stop layer, a noble metal layer on said barrier layer, a mask layer on said noble metal layer, and a patterned resist layer on said mask layer; b) etching a portion of said mask layer including employing a plasma of a mask etchant gas to break through and to remove said portion of said mask layer from said noble metal layer to expose part of said noble metal layer and to produce said subsfrate supporting said etch-stop layer, said barrier layer on said etch-stop layer, said noble metal layer on said barrier layer, a residual mask layer on said noble metal layer, and said patterned resist layer on said residual mask layer; c) removing said patterned resist layer from said residual mask layer of step (b) to produce said substrate supporting said etch-stop layer, said banier layer on said etch-stop layer, said noble metal layer on said banier layer, and said residual mask layer on said noble metal layer; d) heating said subsfrate of step (c) to a temperature greater than about 150°C; e) etching said exposed part of said noble metal layer including employing a plasma of an etchant gas selected from the group consisting of a halogen containing gas, a noble gas, nifrogen, oxygen, and mixtures thereof, to expose part of the barrier layer and to produce said subsfrate supporting said etch-stop layer, said barrier layer on said etch-stop layer, an etched noble metal layer on said barrier layer, and said residual mask layer on said etched noble metal layer; f) etching said exposed part of said barrier layer to expose part of said etch-stop layer and to produce said subsfrate supporting said etch-stop layer, a residual banier layer on said etch-stop layer, said etched noble metal layer on said residual banier layer, and said residual mask layer on said etched noble metal layer; and g) removing said residual mask layer from said etched noble metal layer to produce said subsfrate supporting said etch-stop layer, said residual barrier layer on said etch-stop layer, and said etched noble metal layer on said residual banier layer.
20. The method of Claim 19 additionally comprising etching said etch- stop layer.
21. The method of Claim 19 wherein said mask layer comprises a compound selected from the group consisting of CND SiO2, TEOS, BSG, PSG, BPSG, a low dielectric constant material with a dielecfric constant of less than about 3.0.
22. A method of etching a noble metal layer disposed on a subsfrate comprising the steps of: a) providing a subsfrate supporting a banier layer, a noble metal layer on said barrier layer, a first mask layer on said noble metal layer, a second mask layer on said first mask layer, and a patterned resist layer on said second mask layer; b) etching a portion of said second mask layer including employing a plasma of a mask etchant gas to break through and to remove said portion of said second mask layer from said first mask layer to expose part of said first mask layer and to produce said subsfrate supporting said banier layer, said noble metal layer on said barrier layer, said first mask layer on said noble metal layer, a residual second mask layer on said first mask layer, and said patterned resist layer on said residual second mask layer; c) etching said exposed part of said first mask layer to expose part of said noble metal layer and to produce said subsfrate supporting said barrier layer, said noble metal layer on said barrier layer, a residual first mask layer on said noble metal layer, said residual second mask layer on said residual first mask layer, and said patterned resist layer on said residual second mask layer; d) removing said patterned resist layer from said residual second mask layer of step (c) to produce said subsfrate supporting said barrier layer, said noble metal layer on said barrier layer, and said residual first mask layer on said noble metal layer, and said residual second mask layer on said first residual mask layer; e) heating said substrate of step (d) to a temperature greater than about 150°C; f) etching said exposed part of said noble metal layer and said residual second mask layer of step (d) including employing a plasma of an etchant gas selected from the group consisting of a halogen containing gas, a noble gas, nitrogen, oxygen, and mixtures thereof, to produce said substrate supporting said barrier layer, an etched noble metal layer on said barrier layer, and said residual first mask layer on said etched noble metal layer; g) etching said barrier layer to remove a portion of the barrier layer from said subsfrate to produce said substrate supporting a residual barrier layer, said etched noble metal layer on said residual banier layer, and said residual first mask layer on said etched noble metal; and h) removing said residual first mask layer from said etched noble metal layer to produce said subsfrate supporting said residual barrier layer, and said etched noble metal layer on said residual barrier layer.
23. The method of Claim 22 wherein said patterned resist layer is removed from said residual second mask layer during said etching step (c).
24. The method of Claim 22 wherein said first mask layer comprises a compound selected from the group consisting of Si3N4, BSG, PSG, BPSG, an organic polymer, a low dielectric constant material having a dielectric constant of less than about 3.0, and mixtures thereof.
25. The method of Claim 22 wherein said second mask layer comprises a compound selected from the group consisting of CND Si02, TEOS, Si3Ν4, BSG, PSG, BPSG, SiC, and mixtures thereof.
26. The method of Claim 22 wherein said first mask layer has a thickness ranging from about 3000A to about 8000A.
27. The method of Claim 22 wherein said second mask layer has a thickness ranging from about 50θA to about 4000A.
28. The method of Claim 22 wherein said etching step (g) additionally comprises etching into said substrate.
PCT/US2000/004240 1999-02-17 2000-02-17 Improved masking methods and etching sequences for patterning electrodes of high density ram capacitors WO2000049651A1 (en)

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US09/251,633 US6265318B1 (en) 1998-01-13 1999-02-17 Iridium etchant methods for anisotropic profile
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