WO2000025174A1 - Circuit d'alimentation commandant des cristaux liquides et affichage a cristaux liquides correspondant - Google Patents

Circuit d'alimentation commandant des cristaux liquides et affichage a cristaux liquides correspondant Download PDF

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Publication number
WO2000025174A1
WO2000025174A1 PCT/JP1998/004878 JP9804878W WO0025174A1 WO 2000025174 A1 WO2000025174 A1 WO 2000025174A1 JP 9804878 W JP9804878 W JP 9804878W WO 0025174 A1 WO0025174 A1 WO 0025174A1
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WIPO (PCT)
Prior art keywords
voltage
power supply
liquid crystal
circuit
voltages
Prior art date
Application number
PCT/JP1998/004878
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English (en)
Japanese (ja)
Inventor
Shinsaku Chiba
Takashi Tsuyuki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1998/004878 priority Critical patent/WO2000025174A1/fr
Publication of WO2000025174A1 publication Critical patent/WO2000025174A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers

Definitions

  • the present invention relates to a power supply circuit for driving a liquid crystal with low power consumption, and a liquid crystal display device incorporating the same.
  • the present invention relates to a high-speed driving Alto ⁇ Plesico method, a multi-line selection method, etc.
  • the present invention relates to a low-power-consumption liquid crystal driving power supply circuit for driving a high-speed and high-voltage liquid crystal, and a liquid crystal display device incorporating the same. (Background technology)
  • a main use of a liquid crystal display device is a notebook personal computer, and there is a demand for improvement in response speed and image quality as demands of users.
  • a super nematic liquid crystal display (STN) liquid crystal display device is advantageous in terms of production cost, but in terms of image quality, an active liquid crystal display device such as a TFT liquid crystal is required to have a reduced image quality.
  • STN super nematic liquid crystal display
  • High-speed driving method with a frame frequency of 300 Hz or higher using the Alto's Plesico method described (Hi-FAS: also called High Frequency Amplitude Selection), or a frame frequency of about 150 to 300 Hz and two scanning lines
  • Hi-FAS also called High Frequency Amplitude Selection
  • an enhanced high-addressing drive method combining a drive for simultaneously selecting two or more lines and a shadowing correction circuit
  • the latter driving method is described in Japanese Patent Application Laid-Open No. Hei 9-15556.
  • the power supply voltage for driving the liquid crystal needs to be relatively higher than the conventional driving voltage in order to secure the effective value of the liquid crystal to a required level.
  • Japanese Patent Application Laid-Open Nos. 8-5987 and 8 338980 disclose low power consumption by these driving methods.
  • a power supply circuit that divides a power supply voltage supplied to a plurality of operational amplifiers into two according to the level of a liquid crystal drive voltage
  • Japanese Patent Application Laid-Open No. 294415/1994 and Japanese Patent Application Laid-Open No. 3-226717 / 1995 are mentioned. Operation to be divided into In order to generate the amplifier power supply voltage, the op-amp circuit using the high voltage (VLCD or V1) and the low voltage (ground voltage or V6) is used in the previous operational amplifier circuit. However, the total loss power has been solved.
  • JP-A-6-130916 JP-A-7-66642, JP-A-7-120718, JP-A-7-230265, and JP-A-7-230265.
  • JP-A-10-253945 JP-A-10-253945, and those using an emitter follower transistor circuit for the power supply circuit are also disclosed in JP-A-60-262138, JP-A-61-73196, and -48284.
  • the power supply of the operational amplifier is basically a power supply voltage (V op) as shown in FIG.
  • VDH high-potential power supply voltage
  • VDC intermediate-potential power supply voltage
  • VDL low-potential power supply voltage
  • Vop single voltage generated by the operational amplifier
  • the high-potential power supply voltage (V DH) needs to be about 5.0 V
  • the intermediate potential power supply voltage (V DC) needs to be about 2.5 V
  • the operational amplifier voltage (V op) needs to be about 8.5 V
  • the high-potential power supply voltage (V SH) supplied to the scan electrode drive circuit is about 22.0 V and the low-potential power supply voltage (V SL) is about 17.0 V
  • the intermediate potential power supply voltage (V sc) Is reduced from the power supply voltage (V op) of the operational amplifier by using two transistors (TR 1 and TR 2), and is about 2.5 V which is the same as the intermediate potential power supply voltage (V DC).
  • the potential difference between the operational amplifier voltage (V op) and the intermediate potential power supply voltage (V DC) is about 6.0 V
  • the power generated from the potential difference between the operational amplifier voltage (V op) and the intermediate potential power supply voltage (Vsc) is the loss power.
  • the intermediate potential power supply voltage (Vsc) of the scan electrode drive circuit is a circuit of an emitter follower for increasing the capability. Since they are generated by the star transistors (TR1, TR2), relatively large transistors with high withstand voltage are required, which is an obstacle to miniaturization (small package). Also, transistors with large allowable loss are expensive, and this is an obstacle to reducing the production cost of liquid crystal display devices.
  • An object of the present invention is to solve the above problems and to provide a power supply circuit for driving a liquid crystal with low power consumption and a liquid crystal display device incorporating the same.
  • Another object of the present invention is to provide a liquid crystal driving power supply circuit having a small circuit size and a low cost, and a liquid crystal display device incorporating the same.
  • a power supply circuit for driving a liquid crystal includes a resistive voltage dividing section that generates a plurality of voltages by dividing at least first and second reference voltages, and a voltage dividing circuit that generates the plurality of voltages.
  • Another liquid crystal driving power supply circuit that achieves the above object is a resistive voltage dividing section that generates a plurality of voltages by dividing at least the first and second reference voltages, and a voltage dividing circuit. It consists of an operational amplifier for generating a plurality of liquid crystal driving voltages from the generated voltage, a transistor circuit for generating a non-selection voltage for the scanning electrodes, and a circuit for generating a plurality of operational amplifier power supply voltages having different voltages. The first power supply voltage of one of the power supply voltages is supplied to the operational amplifier, and the second power supply voltage lower than the first power supply voltage is supplied to the transistor circuit.
  • the present invention is effective when the potential difference between the driving voltage generated by the second operational amplifier or the transistor and the first power supply voltage is at least 4 V, and the potential difference of about 6 V or more is effective. In some cases, a remarkable effect is observed.
  • an operational amplifier (including the first or second operational amplifier) to which each power supply voltage is supplied, and the potential of the liquid crystal driving voltage generated by the transistor is The difference is preferably between 1.0 and 5.0 V, particularly preferably between 1.5 and 3.0 V.
  • a transient current that causes distortion depending on the display pattern flows through the non-selection voltage supplied to the scanning electrode. It is desirable that the power supply voltage of the booster transistor and the like be lower than the power supply voltage supplied to the operational amplifier that generates the high voltage of the data electrode drive voltage.
  • FIG. 1 is a first schematic configuration diagram of a part of a power supply circuit to which the present invention is applied.
  • FIG. 2 is a second schematic configuration diagram of a part of a power supply circuit to which the present invention is applied.
  • FIG. 3 is a diagram for explaining a scan electrode drive voltage generator and a data electrode drive voltage generator closer to the actual circuit implementation of the power supply circuit shown in FIG.
  • FIG. 4 is an overall schematic configuration diagram of a liquid crystal display device to which the present invention is applied.
  • FIG. 5 is a schematic configuration diagram of the entire power supply circuit to which the present invention is applied.
  • FIG. 6 is a schematic configuration diagram of a voltage correction circuit in a power supply circuit to which the present invention is applied.
  • FIG. 7 is a functional block diagram of the correction cook generation circuit.
  • FIG. 8 is a drive output waveform diagram of a liquid crystal display device suitable for the power supply circuit according to the present invention.
  • FIG. 9 is a schematic configuration diagram of a DC-DC converter suitable for a power supply circuit according to the present invention.
  • FIG. 10 is a diagram showing a schematic configuration of a conventional power supply circuit.
  • FIG. 1 shows a first embodiment of the present invention.
  • a control signal VCON is input and becomes a reference voltage.
  • DC-DC converter that outputs four voltages (VSH, VSL, V.pH, VopL), voltage-dividing resistor circuits (R1, R2, R3, R4) and data electrodes
  • the operational amplifiers (OP1, OP2, OP3) that generate the applied drive voltages (VDH, VDC, VDL) and the drive voltage (Vsc) that serves as the reference for the non-selection voltage supplied to the scan electrodes And a transistor circuit (TR1, TR2) to be generated.
  • This transistor circuit can be appropriately expressed as a booster transistor or an auxiliary transistor. This is to assist the element capability of the operational amplifier (OP 2 or OP 4).
  • the high voltage is indicated by V s H, and basically the output from the DC-DC converter 1 is directly used.
  • the low voltage is indicated by VSL, and this is also basically the output from the DC-DC converter 1, which is used directly.
  • the high voltage has a VSH of about 22 V and the low voltage has a VSL of about 17 V.
  • the first power supply voltage (V. P H) is about 7. 5 V
  • the second power supply voltage (V. P L) is about 4.
  • VDH drive voltage applied to the data electrodes
  • VDC drive voltage applied to the data electrode
  • the drive voltage (Vsc) and the drive voltage (VDC) are the same voltage and may be generated with the same configuration. However, when the drive voltage (Vsc) is corrected as described later, this voltage is not applied. As in the embodiment, it is preferable that the voltage is generated separately even if the voltage is the same.
  • the details of the internal configuration and operation of the DC-DC converter 1 are omitted here. As shown in Fig.
  • the input power (Vcc) of 2.8 to 3.6V (3.3V here) is The voltage is boosted using transformers (T1 and T2) to generate the above-mentioned voltages (V. PH , V. PL , VSH, VSL). Therefore, inside the DC-DC converter 1, the circuit configuration is such that the power supply that has been boosted once is divided and a plurality of power supply voltages for the subsequent operational amplifier are generated by the operational amplifier at the preceding stage as described in the related art. Absent. Note that one of the reference voltages (Vss) is omitted because it is a ground voltage.
  • Another modification of the internal configuration of the DC-DC converter 1 is an operational amplifier used for generating a plurality of drive voltages as described in Japanese Patent Application Laid-Open No. 8-5987 (US Pat. No. 5,663,743).
  • the power supply voltage is generated from a directly input reference power supply by voltage division or the like, and other drive voltages are generated by boosting the reference power supply.
  • the reference voltage (Vcc, Vss) is boosted in the entire power supply circuit including the DC-DC converter 1. It is needless to say that some operation is performed between the potential differences, and loss power is generated in the operation.
  • the operational amplifiers (OP1, OP2, OP3) that generate the drive voltages (VDH, VDC, VDL) to be applied to the data electrodes have 0P1 and other operational amplifiers. Since different power supply voltages are supplied to OP2 and OP3, power consumption can be reduced as compared with the conventional power supply circuit shown in FIG.
  • the second power supply voltage (V.pL) is used as a reference voltage used to generate a drive voltage (Vsc) serving as a reference for the non-selection voltage supplied to the scan electrode, the transistor circuit ( Since the voltage applied to TR1 and TR2) is small, transistors in a small package can be used, which leads to downsizing of the circuit scale and reduction of production cost.
  • FIG. 2 shows a second embodiment of the power supply circuit to which the present invention is applied.
  • the operational amplifier (OP4) is simplified to only one.
  • the operational amplifier (OP 4) is the same as the conventional one in that a high voltage (V opH) is used as the power supply voltage, but the drive voltage (Vsc), which is the reference of the non-selection voltage supplied to the scan electrode, is used.
  • V opH high voltage
  • Vsc the drive voltage
  • the second power supply voltage (V. P L) is used for the reference voltage used to generate a voltage decreases applied to as in the first embodiment transistors circuit (TR 1, TR 2) Therefore, not only power consumption but also transistors in small packages can be used, which leads to downsizing of the circuit scale and reduction of production cost.
  • the relationship between the driving voltages is the same as that of the first embodiment.
  • the potential difference between the two power supply voltages (VSH and VSL) supplied as the selection voltage to the scan line and the selection signal is applied to the data line. If the ratio of the potential difference between the two power supply voltages (VDH, VDL) supplied as the above is approximately 7.5 to 10 times or more, the above first and second embodiments are not suitable. Needless to say.
  • FIG. 3 is a diagram for explaining a scan electrode driving voltage generating unit and a data electrode driving voltage generating unit, which are closer to actual circuit mounting of the power supply circuit shown in FIG. 1, (OP1, OP2, OP3) and DC-DC converters, each shows an image formed in one integrated circuit IC.
  • a logic voltage (V Logic) generated by dividing VSH and VSL is used for controlling the drive circuit, but is not directly related to the description of the present invention, and thus the details are omitted.
  • the potential difference between the highest voltage (VSH: 22 V) and the lowest voltage (VSL: —17 V) of the output voltage from the converter 1 is 39 V, which is 39 V in relation to the effective value of the liquid crystal. From 1 V 1 V of Z (that is, 3.25 V), it can be specified that a large difference in the potential of the above-mentioned operation power supply is an effective range.
  • FIG. 4 is a block diagram showing a configuration of a liquid crystal display device to which the power supply circuit for driving a liquid crystal of the present invention is applied, where 103 is a liquid crystal panel, and 101 is a scanning electrode driving circuit for simultaneously selecting two lines.
  • Reference numeral 102 denotes a data electrode drive circuit that determines a display state on two lines to be selectively scanned by the scan electrode drive circuit 101.
  • parallel display data D7 to D0
  • data latches synchronized with display data multiple bits (8 bits here, but 12 or 16 bits may be used)
  • Clock data clock signal CL 2
  • line clock signal that sends one line of data in one cycle
  • Line clock CL 1 first line clock (frame synchronization signal or frame pulse) indicating the beginning of one frame period FLM, display is stopped when it is "0"
  • Display off control signal (DIS POF F) is output Is done.
  • Reference numerals 108 and 109 denote a power supply voltage group required for the data electrode drive circuit and the data electrode drive circuit, respectively, and 100 denotes a power supply circuit according to the present invention for generating a power supply voltage group.
  • the orthogonal function generation circuit 104 generates the orthogonal function W1 signal and W2 signal. Orthogonal function W1 signal and W2 signal are scan electrode drive circuit 101, data electrode drive The circuit 102 is supplied to the correction clock generation circuit 105.
  • the correction cook generation circuit 105 generates correction clocks C C1 and C C2 for adjusting the effective value of the scanning line selection voltage as described later.
  • the essential function is the total correction of the correction amount based on the contents of the display data for a plurality of rows corresponding to the so-called shift number and the correction amount calculated from the pulse-like distortion generated in the non-selection voltage of the scanning line. It can also be expressed as a function of generating a correction clock corresponding to the amount.
  • the pulse width calculated from the pulse-like distortion generated in the non-selection voltage is used for the vertical shadowing.
  • the pulse width period that is the sum of the pulse width calculated from the contents of display data for multiple rows corresponding to the so-called shift number is the effective value during the selection voltage application. Is given to the scan electrode drive circuit 101 as an adjustment period.
  • FIG. 5 is an overall configuration diagram of the power supply circuit 100 according to the present invention.
  • the power supply circuit 100 is composed of a DC-DC converter 1 driven by the Vcc voltage, voltage dividing resistors R1 to R4, operational amplifiers 0P1, 0P2 and ⁇ P3, a voltage correction circuit 200, and an operational amplifier / integrator circuit 205. Is done.
  • the voltage correction circuit 200 further has a circuit as shown in FIG. 6 described later.
  • the transient current detected by the current detection resistor R10 is added to the operational amplifier
  • the driving voltage (Vsc) is corrected by the integration circuit portion including the above.
  • the voltage VSH and the voltage VSL are each directly generated by the DC-DC converter 1 and can be varied by the adjustment voltage VCON.
  • the voltages VDH, VDC, and VDL, including the voltage Vsc, are divided by R1 to R4 between the scan driver power supply voltage VSH and the voltage VSL, and the operational amplifiers OP1, ⁇ P2, OP3, and the transistor TR 1. Impedance conversion is performed via a voltage follower circuit using TR 2 and output. Note that between the resistors R1 to R4,
  • VDH-VDC VDC-VDL
  • the voltage Vsc is generated in the voltage correction circuit 200 based on the reference voltage Vc.
  • predetermined voltages VSHA, VSLA
  • Vsc voltage closer to the voltage (Vsc) than the original selection voltages (VSH, VSL) are generated.
  • the effective value of the selection voltage is controlled by the first pulse width according to the waveform distortion generated in the scanning line to which the non-selection voltage is applied.
  • the second pulse width corresponding to the display content is added to the first pulse width to reduce the vertical shadowing and to reduce the horizontal shadowing. This also makes it possible to control the effective value of the selection voltage more finely.
  • the pulse width is determined by the correction pulses CC 1 and CC 2.
  • the scan electrode drive circuit to which this signal is input replaces the original selection voltage (VSH or VSL) with the voltage (VSH or VSL) during the selection pulse input period.
  • a predetermined voltage (VSHA or VSLA) close to Vsc) is selectively supplied to the scan electrodes.
  • the pulse widths of the correction pulses CC 1 and CC 2 are controlled in order to increase or decrease the effective value due to the above two different factors.
  • the correction of the effective value is performed by a predetermined voltage (VSHA or VSLA) selectively supplied instead of the original selection voltage (VSH or VSL).
  • VSHA or VSLA a predetermined voltage
  • VSH or VSL original selection voltage
  • the characteristics are different from those of a clock having a fixed pulse width, such as the temporary division period and the line clock CL1, which are part of the system clock.
  • VDH, VDL data driving power supply
  • resistors R20, R21, and R22 are used as a reference voltage for a distortion pulse generating circuit 203 described later with reference to FIG. Between each voltage,
  • FIG. 6 shows an embodiment of the voltage correction circuit 200.
  • R10 is a current detection resistor, and is provided in series with the scan electrode driving non-selection voltage line.
  • Scan electrode drive wave Distortion of the non-selected portion of the shape is caused by a current flowing through the scan electrode due to crosstalk in switching the voltage over time and a voltage drop of the circuit resistance.
  • the current flowing through the scanning electrode can be predicted from the current flowing through the power supply circuit. Therefore, the distortion of the non-selection portion of the scan electrode drive waveform can be predicted by the current value flowing through the scan electrode drive non-selection line of the power supply circuit. That is, by detecting the voltage generated at both ends of R 10, the distortion of the non-selected portion of the scan electrode drive waveform can be detected.
  • the operational amplifier circuit is composed of the resistors R11 to R14 and the operational amplifier OP5.
  • the terminal on the scan electrode drive circuit side of the resistor R10 is connected to R13 on the non-inverting amplifier side of the operational amplifier circuit.
  • the terminal of the resistor R10 on the power supply circuit side is connected to R11 on the inverting amplification side of the operational amplifier circuit.
  • an integrating circuit (however, an inverting integrating circuit) is constituted by the switches 204 which perform on / off operations according to the resistors R15 and R16, the capacitor C10, the operational amplifier OP6 and the CL1 signal. In this circuit, the integration circuit also functions as the correction voltage generation circuit.
  • the output voltage V Y 0 becomes the same as the reference voltage Vsc.
  • the output voltage V 2 of the operational amplifier circuit is the output voltage of the integrator circuit V 1 (provided that the reference voltage Vc is 0 V)
  • V 2 -AV 1 + B (V 1-i-R I O)
  • the effect of time delay is added and the amplitude of the correction is reduced by using the integral of the current value for the correction first.
  • the integral value since the current changes for each temporary division, the integral value must be reset for each temporary division.
  • the circuit is stabilized by adding a term that suppresses the change of v 1 by setting A ⁇ B (A ⁇ B). As described above, a sufficient correction can be obtained in a stable state.
  • the signal modulating circuit 201 is constituted by a bidirectional diode, whereby the integrator does not operate unless a voltage higher than the diode forward voltage is input. Accordingly, correction can be performed without detecting circuit noise. Also, even when compensating for shadowing that occurs above and below the vertical ⁇ line, strictly due to the difference in the dielectric constant of the liquid crystal between the case of a black ⁇ line on a white background and the case of a white ⁇ line on a black background. Is different in the appropriate correction amount.
  • the orthogonal function W1 signal and W2 signal were generated by the orthogonal function generation circuit 105.
  • the orthogonal function is generated inside the scanning driver, and the orthogonal function is generated by a data dryino or correction clock. There is no problem even if the configuration is supplied to the generating circuit. Furthermore, there is no problem even if one drive IC is used in combination with the above power supply circuit for one drive IC.
  • the present invention is not limited to this.
  • the configuration described above since the transient waveform distortion is detected, the analog operation result of the correction voltage becomes too large than an appropriate value, and the display is stopped. Depending on the turn, the shadowing reduction effect may be halved.
  • a pair of bidirectional short-circuit diodes 202 are provided between the reference voltage Vc and the output of the signal modulation circuit 201.
  • the current flowing through the integrating circuit (C 10 + OP 6) is reduced by the threshold voltage (referred to as VF) of the Schottky diode 202 and the resistance. Since the ratio of R16 can be limited to VFZR16, overcorrection due to transient current can be suppressed.
  • the positive-direction distortion pulse signal CW + (hereinafter, positive distortion pulse signal) and the negative-direction distortion pulse signal CW— (hereinafter, negative distortion pulse signal) generated by the distortion pulse generation circuit 203 are output from the correction clock generation circuit 105. Supplied to
  • FIG. 7 is a functional block diagram of the clock generator 105.
  • the first logic circuit 300 that has received the above-described distortion pulses (CW +, CW—) generates a quadrature function that is also supplied to the scan electrode driving circuit 101 and a non-selective spike that causes vertical shadowing.
  • the first correction pulses (CCA1, CCA2) for correcting the selection voltages selected at the same time are determined based on the magnitude of the shape distortion.
  • the start timing (or the end timing) for controlling the effective value with the determined pulse width is performed at a predetermined timing within each time division period, so that the line clock CL 1 is also connected to the first logic circuit 300.
  • the clock is not necessarily required depending on the supplied power and the content of the adder circuit.
  • the second logic circuit 301 includes a data signal (D7 to D0) or another input signal as shown in the figure to reduce the increase in the effective value depending on the display content that causes horizontal shadowing.
  • the second correction pulse width is generated for the number of simultaneously selected scanning lines.
  • the specific width of the second correction pulse ( WeeD ) is 800 data lines (corresponding to SVGA) and the temporary division period (from the falling edge of clock pulse CL1 to the next falling edge ). ) Is about 20 seconds, a black (off) horizontal line is displayed on a white display (on) background, and when the number of white (on) is n,
  • W CCD An + B (However, -4.1X10 -3 A A--3.4X10 ', 1.60 ⁇ B 1. 1.90), which is a pulse width correction in the range of 0.24 to 1.8 seconds,
  • W CCD An + B (with ⁇ , ⁇ -6 ⁇ 0 ⁇ 1 ( ⁇ 4 , ⁇ ⁇ 0 ⁇ 48)
  • the pulse width is corrected in the range of 0.24 seconds or less.
  • correction pulses generated by the first and second logic circuits are input to the adder circuit, and correction clocks CC1 and CC2 actually used for controlling the selected voltage are generated.
  • the correction clock CC1 is a correction clock for the selection voltage of the simultaneously selected odd-numbered scanning electrodes
  • the correction clock CC2 is a correction clock for the selection voltage of the evenly selected scanning electrodes. It is.
  • the time when the correction by the first correction pulse (CCA) becomes 0 and the correction by the second correction pulse (CCD) during the normal selection voltage application period The time when it becomes 0 is matched.
  • the correction amount by the correction of the first correction pulse (CCA) is larger than 0, in the case where the above correction amount becomes 0, the correction to reduce the effective value in the traveling direction on the time axis is performed, and the second correction pulse If the correction amount due to (CC D) is larger than 0, correction is performed to reduce the effective value in the direction that goes backwards on the time axis from the time when the correction amount becomes 0.
  • the spike-like distortion may increase the effective value of one selected voltage of the scanning lines simultaneously selected according to the direction and simultaneously decrease the other selected voltage.
  • the first correction pulse may have a negative correction amount and to offset the correction by the second correction pulse by the negative correction amount.
  • FIG. 8 is a timing chart showing the voltage applied to the liquid crystal panel.
  • Frame frequency is 15 Driven at 0 to 300 Hz.
  • VSH or VSL supplied to the scan electrode drive circuit and Vsc are distortions caused by vertical shadowing flowing in the scan line to which the non-scan voltage Vsc is supplied.
  • the voltage varies in accordance with the current c.
  • the output of the scan electrode driving circuit has a waveform as exemplified by Y1 to Y6.
  • the scanning voltage selection period there is a correction waveform in which the effective value of the selection voltage is reduced by the correction clock from the correction clock generation circuit 105 described above, and in the non-selection period, the background Correction of the effective value due to pulse-like waveform distortion due to switching of the evening voltage waveform is seen.
  • non-selection period correction a correction voltage is applied immediately after the waveform distortion so as to cancel the distortion, and reset at the end of the time division period.
  • the line clock CL1 for controlling the timing of the temporary division period is a clock signal having a fixed pulse width.
  • the start timing of each time division period is the falling timing of the line clock CL1, and the reset of the correction voltage is started at the rising timing of the line clock CL1.
  • the power supply circuit to which the present invention is applied is suitable in terms of power consumption and the like.
  • the present invention can be applied to a liquid crystal display device requiring a relatively high driving voltage, as well as a control device or a display device requiring a small size.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Liquid Crystal Display Device Control (AREA)
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Abstract

La présente invention concerne un circuit d'alimentation commandant des cristaux liquides qui consomme peu d'énergie, et un affichage à cristaux liquides doté d'un tel circuit d'alimentation. Le circuit d'alimentation comprend des éléments diviseurs de tension du type à résistance (R1, R2, R3 et R4) qui produisent une pluralité de tensions en divisant au moins une première et une deuxième tensions de référence (Vsh, Vsl) ; une pluralité d'amplificateurs opérationnels (OP1, OP2) qui génèrent une pluralité de tensions de commande des cristaux liquides à partir des tensions produites par les éléments diviseurs de tension (R1, R2, R3 et R4) ; et un circuit (1) qui fournit une pluralité de tensions d'alimentation. Une première tension d'alimentation (VopH) va alimenter un amplificateur opérationnel (OP1) et une seconde tension d'alimentation (VOPL), plus faible que la première (VopH), va alimenter le second amplificateur opérationnel.
PCT/JP1998/004878 1998-10-28 1998-10-28 Circuit d'alimentation commandant des cristaux liquides et affichage a cristaux liquides correspondant WO2000025174A1 (fr)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04315897A (ja) * 1991-04-15 1992-11-06 Sharp Corp サンプルホールド回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04315897A (ja) * 1991-04-15 1992-11-06 Sharp Corp サンプルホールド回路

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