WO2000019538A1

WO2000019538A1 - Self-aligned non-volatile contactless memory cell with reduced surface

Info

Publication number: WO2000019538A1
Application number: PCT/FR1999/002298
Authority: WO
Inventors: Joël HARTMANN
Original assignee: Commissariat A L'energie Atomique
Priority date: 1998-09-29
Filing date: 1999-09-28
Publication date: 2000-04-06
Also published as: FR2783972A1; FR2783972B1; EP1036417A1

Abstract

The invention concerns a non-volatile memory cell comprising a floating gate type memory element (58), a source zone, a drain zone, a channel zone and a control gate (68), the floating gate comprising a chip made of conductor or semiconductor material and a layer (58, 64) made of conductor or semiconductor material, formed and etched above the chip of conductor or semiconductor material, in electrical contact therewith.

Description

NON-VOLATILE, SELF-ALIGNED, NON-CONTACT, REDUCED SURFACE MEMORY CELL

Technical field and prior art

The invention relates to the production of non-volatile memory points of the PROM, ΞPROM, EEPROM or FLASH EPROM type.

Most non-volatile memory cells are today made with a so-called T-shaped structure comprising a double grid (floating grid and control grid for the word line), a source zone and a drain zone contacted at the line of bit. This cell has an area of the order of 9 ^" times the square of the minimum dimension printable by the lithography tool corresponding to the technological generation of the moment (currently, the minimum dimension is 0.25 μm).

Each memory point comprises a half bit line contact (a contact shared between two adjacent cells). With the constant reduction of drawing rules and the continuous increase in integration densities (16 Mbits, even recently 64 Mbits and 256 Mbits), this T-cell becomes difficult to achieve, and the number of contacts is always increasing (already several millions today), leads to a significant defect, and therefore a loss of yield.

Other cells have already been proposed to solve the problem of the number of contacts in a non-volatile memory plan. The cell called NAND from Toshiba allows to share a contact - between 16 cells, instead of 2 in the T-cell. The AND cell of Hitachi also allows to reduce the number of contacts per plane memory. These cells are placed in series and require a very specific addressing and writing mode. They are generally slower than the T cell. The AMG cell proposed by R. Kazerounian et al. (Published at the IEDM 1991 conference, cf. IEDM91 Technical Digest, p. 311) also enables the number of contacts in the memory plane to be reduced, by symmetrizing the source and drain zones. For this, a selection transistor is inserted every 64 cells. Each bit line is shared between two diffusion lines, thus allowing each diffusion line to become sometimes a drain, sometimes a source. This modification is made using the selection transistor. The integration density is thus improved, since the pitch of the metal level can be reduced, but the complexity is transferred to the addressing level since in order to select a cell, it is necessary to address the grid, the source and the drain at the same time. that, in a T-cell, the source is common and permanently connected to the ground of the circuit. This results in an increased complexity of the modes of polarization of the memory plane: for example, all the bit lines situated to the left of the source of the selected cell must be polarized to ground, while all those situated to the right of the drain of the selected cell must be polarized at V _dd . The periphery of the memory plane is therefore more complex and consequently occupies a larger surface, proportionally, than that occupied by a memory having T cells.

The cell known as “split spoils” proposed by Boaz Eitan in 1987 (US-4,639,893) also makes it possible to reduce the number of contacts in the memory card. In addition, the control gate is made in such a way that the memory point is composed of two transistors in series: the double gate storage transistor (control gate and floating gate) and a selection transistor, the control gate being common to the two transistors. This configuration eliminates the parasitic conduction problem of cells located on the same bit line as the cell addressed in word line (problem called "drain turn-on" in English). Here too, the addressing of a memory point requires the decoding of the gate, the source and the drain. The problem of the complexity of the addressing then arises, as well as that of the surface occupied by the peripheral circuitry, necessary to manage this multiple addressing.

Statement of the invention

The object of the present invention is to propose a non-volatile memory device making it possible to solve the problems set out above.

To achieve this object, the invention more specifically relates to a memory device with a plurality of non-volatile memory cells each comprising a floating grid, a source zone and a drain zone, self-aligned with respect to the floating grid, a channel zone and a control grid, the floating grid comprising a block of conductive or semiconductor material and a layer of conductive or semiconductor material, formed and etched above the block of conductive or i-conductive material , in electrical contact with it, and wherein the memory cells are arranged in rows and columns in a staggered pattern.

Each memory cell is therefore produced by a crossed stack of a first level of conductive or semiconductor material, and of a second level of conductive or semiconductor material.

The source and drain zones are self-aligned with respect to the blocks of conductive or semiconductor material: in fact, the first level of conductive or semiconductor material makes it possible to define, for example, diffusion lines N * constituting said source and drain zones.

The layer of conductive or semiconductor material overflows on either side of the block of conductive or semiconductor material, above the source and drain zones.

The control grid is separated and isolated from the layer of conductive or semiconductor material by a first dielectric layer. A second layer of dielectric material is deposited over the control grid. First metallic lines, called bit lines, can be formed over the second layer of dielectric material. A third layer of dielectric material is then deposited over the first metal lines and second metal lines, called word lines, can be formed over the third layer of dielectric material. The non-volatile memory device according to the invention comprises a plurality of cells according to the embodiment described above. These cells are arranged in rows and columns, in a staggered pattern comparable to a checkerboard pattern.

This staggered configuration is such that the source zones of the cells arranged in the same column form a continuous zone from the electrical point of view.

The subject of the invention is also a method of producing a non-volatile memory cell, comprising a memory point of the floating gate type, a source area, a drain area, a channel area and a control gate, the floating grid being produced by:

deposition and etching of a first layer of conductive or semiconductor material, so as to form a block of a first level of conductive or semiconductor material,

- deposition and etching of a second layer of conductive or semiconductor material, over the block of first level of conductive or semiconductor material and in electrical contact with it, so as to form a layer of a second level of conductive or semiconductor material.

The production of the block of the first level of conductive or semiconductor material may include:

a first step of forming a strip of conductive or semiconductor material, in a first direction,

a second step of etching the strip of conductive or semiconductor material, in a second direction perpendicular to the first, so as to release the silicon block. In addition, this method may include, between the first and second steps, a step of producing the source and drain zones, self-aligned with respect to the strip of conductive or i-conductive material.

This method may also include, after the second step of etching the strip of conductive or semiconductor material, a step of producing isolation zones of the source and drain zones, these isolation zones being self-aligned with respect to the source and drain zones and with respect to the block of conductive or semiconductor material.

The invention also relates to a method for producing a non-volatile memory device, comprising a plurality of non-volatile memory cells, each cell being produced according to a method as defined above.

The cells are advantageously arranged in rows and columns, according to a checkerboard configuration. In particular, the source zones of the cells of the same column can be produced according to a continuous zone from the electrical point of view.

Thus, the invention relates to a method for producing a non-volatile memory device comprising a plurality of non-volatile memory cells, each non-volatile memory cell comprising a memory point of the floating gate type, an area of source, a drain zone, a channel zone and a control grid, the floating grid being produced by:

- deposition and etching of a first layer of conductive or semiconductor material, so as to form a paved with a first level of conductive or semiconductor material,

- deposition and etching of a second layer of conductive or semiconductor material, over the block of first level of conductive or semiconductor material and in electrical contact with it, so as to form a layer of a second level of conductive or semiconductor material, the blocks of the first level of conductive or semiconductor material being produced by:

- a first step of forming a strip of conductive material or a semiconductor, according to ^a first direction,

a second step of etching the strip of conductive or semiconductor material, in a second direction perpendicular to the first, so as to release the block, the cells being arranged in lines at a pitch X equal to twice the first pitch and in columns according to a step Y equal to the second step.

The invention makes it possible both to achieve a completely self-aligned memory point, without making contact holes, and the surface of which is directly given by the product of the pitch of a level of conductive or semiconductor material in X, by twice the pitch of the grid level in Y. In addition, the source of each memory point is connected to the ground of the circuit and therefore does not require any particular decoding (due to the common source) which considerably simplifies the circuitry external to the memory map, necessary to manage the addressing of cells as well as reading the information therein.

The memory cell is produced by crossing a level of conductive or semi-conductive material, which makes it possible to predefine the N ⁺ diffusion lines, and another level of conductive or semi-conductive material which defines the control grids. of the memory plan. The cell occupies a double pitch of conductive or semiconductor material in X. The selective elimination of a portion of conductive or semi-conductive material, every two lines, and this in a Y-offset manner (thanks to a checkered resin mask) makes it possible to ensure electrical continuity between the diffusion zones N ⁺ intended to form the source of the cells.

Brief description of the figures

In any case, the characteristics and advantages of the invention will appear better in the light of the description which follows. This description relates to the exemplary embodiments, given by way of explanation and without limitation, with reference to the appended drawings in which:

- Figures 1A to 7C show steps of a method of producing a device according to the invention, the figures referenced A each representing a top view, the figures referenced B (respectively C) each representing a sectional view along the plane AA '(respectively BB') of the corresponding figure A.

- Figures 8A and 8B show a device according to the invention, comprising a plurality of memory points arranged in a checkerboard pattern, seen from above (Figure 8A) and according to a simplified electrical diagram (Figure 8B).

- Figures 9 and 10 show a device according to the invention, with 20 checkerboard memory points, seen from above.

According to the preferred embodiment of the invention described below, the conductive or semiconductor material is polycrystalline silicon. More generally, however, the invention relates to other embodiments according to which the pavement of the floating gate layer and the floating gate are made of conductive material or ^whether emi- conductor. The conductive or semiconductor material which constitutes the block of the floating gate can then be identical or different from the conductive or semiconductor material which constitutes the layer of the floating gate.

Detailed description of embodiments of the invention

A first step in producing a device according to the invention is illustrated in FIGS. 1A to 1C. On a semiconductor substrate 2, for example P-type silicon, a layer 4 of gate oxide is produced, for example by thermal oxidation of the semiconductor substrate. Then, a polycrystalline silicon layer is deposited and doped, over the gate layer 4. This polycrystalline silicon layer is etched, by photolithography, to define bands 6, 8, 10, 12 of a polyl level. N ⁺ junctions 14, 16, 18, 20, 22 are then produced, for example by ion implantation of arsenic. These junctions are self-aligned with respect to the bands 6, 8, 10, 12 of polyl and will make it possible to define the source and drain zones, separated by channel zones 17, 19, 21, 23.

The source and drain contacts are distributed outside the memory plane.

In a second step (FIGS. 2A-2C), a second network, perpendicular to the first, is produced, for example by photolithography, so as to define polycrystalline silicon squares 24, 26, 28, 30, 32, in alternating checkerboards. This step is carried out using resin masks 25, 27, 29, 31, 33, 35 (FIG. 2A). In FIG. 2B, the references 38, 40 respectively designate the imprints of the resin mask in the gate oxide layer 4 and the imprints of the etched polycrystalline silicon pad. The resin mask is then removed by any known technique.

In a third step (Figures 3A-3C), the junctions are isolated. To this end, a P-type ion implantation is carried out, for example. It can be a full slice ion implantation of boron ions, followed by thermal annealing. P ⁺ type junctions 44, 46, 48, 50 are thus produced, self-aligned with respect to the N ⁺ junctions 14, 16, 18, 20, 22 and the polycrystalline silicon blocks 24, 26, 28, 30, 32 .

In a fourth step (FIGS. 4A-4C), a second deposition of polycrystalline silicon (poly2) is carried out.

To this end, a layer 52 of thick dielectric is first deposited (for example, in Si0 ₂ doped with phosphorus). This layer can advantageously be densified by annealing. It then undergoes a chemical mechanical planarization, with stopping on the polycrystalline silicon blocks 28, 32 (FIG. 4B). A deposition is then carried out, by CVD technique, and by doping, of a second thin layer of polycrystalline silicon (poly2). This layer is in electrical contact with the blocks 28, 32 of polyl.

This layer is etched, for example by photolithography and using a resin mask 54 with a stop on the planarized dielectric 52. One thus obtains, above each block 28, 32 of silicon, and in electrical contact with it, an etched layer 56, 58, 60, 62, 64. This etched layer overflows on either side of the corresponding block, above the source and drain zones. Each polyl + poly2 set forms the floating grid of a memory point.

In a fifth step (FIGS. 5A, 5B, 5C), a control grid for each memory point is produced. To this end, a layer 66 of interpoly dielectric is deposited by CVD technique, of the N-0 or O-N-O type. Then, a third layer 68, 70, 72 of polycrystalline silicon (poly3 level) is produced, for example by CVD deposition and doping. This third layer of polycrystalline silicon undergoes a photolithography step with stopping on the dielectric interpoly 66. This level poly3 forms, after etching, the control grid of the memory point.

Then, in a sixth step (FIGS. 6A-6C), the bit lines of the memory points are produced. To this end, a thick dielectric 76 is deposited intended to provide the dielectric insulation between the poly3 level and the metal of the bit lines. This dielectric undergoes a chemical-mechanical planarization operation.

Then, by photolithography, contact holes are made, intended to resume the electrical contacts on the N + junctions and on the poly3 level.

A first metallization layer is then deposited. This layer is etched, for example by photolithography, to produce the first level of metallization (metal 1) intended to form, in particular, the bit lines 78, 80, 82, 84, 86 of the memory points.

Then, the electrical shunt of the poly3 control grids is carried out. To this end (FIGS. 7A, 7B, 7C) a new thick dielectric layer 90 is deposited, intended to provide dielectric isolation between the metal levels 1 and the metal level 2. This dielectric undergoes chemical-mechanical planarization. One then proceeds to a photolithography of contact vias intended to resume metallic contacts on the metal level 1. A second metallization layer 92 is then deposited. This layer is etched, for example by photolithography, to produce the second metallization level (metal 2: strips 92, 94, 96) intended to form, in particular, the electrical shunt of the control grids of the poly3 level.

FIG. 8A represents, in top view, a device according to the invention, with several memory cells arranged in a checkerboard pattern. The memory cells are obtained by the method which has been described above in connection with FIGS. 1A to 7C. In FIG. 8A, the references 100, 104, 108 denote source lines (ground). The references 102, 106 designate bit lines, while the references 110, 112, 114 represent word lines. The memory cells, arranged in a checkerboard pattern, are designated by the references 116, 118, 120, 122, 124, 126.

Examples of access mode to different cells will be given, using the diagram in FIG. 8B:

1. Access mode to cell 116: The control grid of this cell is polarized by the word line 110. The source line 100 is grounded. The cell drain is polarized by the bit line 102.

2. Access mode to cell 126: The control grid of this cell is polarized by the word line 112. Then the source line 108 is grounded. The cell drain is then polarized by the bit line 106.

3. Access mode to cell 124: The control grid of this cell is polarized by the word line 114. The source line 104 is grounded. The cell drain is polarized by the bit line 106.

The programming mode for writing a cell, for example cell 116, is as follows.

A strong positive voltage V _pp is applied to the word line 110. The source line 100 is grounded, or maintained. A positive programming voltage is applied to the bit line 102. This results in conduction-saturation of the transistor of cell 116, and an injection of hot carriers into the floating grid of this cell. No other neighboring cell is switched on: cell 122 is on the word line 110, but is connected to the bit line 106, which is non-polarized; cell 120 is on the same bit line 102, but is connected to the word line 112 which is unpolarized.

The reading mode of a cell, for example cell 116, is as follows. A positive nominal voltage V _cc is applied to the word line 110, and the source line 100 is grounded or maintained. This results in a weak conduction ^" of the transistor of the cell 116, and a reading of an electric current on the bit line 102, if the cell 116 is not programmed. If it is already programmed a zero electric current No other neighboring cell is switched on: cell 122 is on the same word line 110 but is connected to a bit line 106, not polarized; cell 120 is on the same bit line 102, but is connected to the word line 112 which is unpolarized.

The programming mode for erasing a cell, for example cell 116, is as follows. A zero, or slightly negative, voltage is applied to the word line 110, then a positive (or medium) positive voltage, to the source line 100. The bit line 102 is not polarized. In the case of non-decoding of the source, all the source lines are always connected to ground or to the erasing voltage. All cells connected to the same word line are then deleted. If there is decoding of the source, it is then possible to ground (or erase voltage) only the addressed cell (here: cell 116). In this case, the erasure is selective and only the cell 116 is erased (operation of the EEPROM type). It should be noted that a decoding device to connect the source to ground is not necessary. Indeed, it is by its design that the source is connected to ground.

Figures 9 and 10 show, in top view, devices produced by the technique described above, and each comprising four memory planes, of which only one is shown entirely. In these two figures, the references 130, 132, 134, 136 designate bit lines, the reference 138 designates a source line shared between the four memory planes. The memory cells are represented by hatching, and are well arranged in a checkerboard pattern. In FIG. 9, the references 140, 142, 144, 146 designate mini-fields of field oxide produced for example by localized thermal oxidation of the silicon or by isolation in trenches (shallo Trench Isolation), while the references 148, 150, 152, 156 denote, in FIG. 10, isolation zones between bit lines and sources. These P ⁺ type isolation zones are defined during the lithography of the polyl level. In these two figures, common drain zones are designated, in correspondence with each bit line, by the references 131, 133, 135, 137.

The surface of a conventional cell, in T, is defined by: - the pitch in X which is the pitch of the first level of metal, and which is therefore necessarily greater than the pitch of polycrystalline silicon. The pitch in X corresponds to twice the pitch of the first level of polycrystalline silicon (6, 8, 10, 12),

- the pitch in Y which is the half-space defined by the width of the level poly2, the greater the distance between contacts and grid, the greater the half-size of the drain contact. The step in Y is the step of the level of the control grids (68, 70, 72).

For example, for a 0.25 μm drawing surface, we have:

- not in X: 0.8 μm,

- step in Y: lμm, i.e. a minimum surface of the memory cell equal to

0.8μm ² .

In a cell according to the present invention, if the pitch of the poly level is 0.5 μm, the surface of the cell will be: - pitch in X: 2x0.5 = lμm,

- step in Y: 0.5 μm, ie a minimum surface of the memory cell equal to 0.5 μm ² ; this is equivalent, with identical drawing rule, to a gain of 35%. In addition, the functionality of the cell according to the invention is 100% guaranteed, since it is fully self-aligned, which is not the case for the T-cell. The functionality of the latter is indeed very sensitive, for example to the respect of the alignment of the drain contact with respect to the double gate, any misalignment which can cause a short circuit between bit lines and word lines. This sensitivity is further increased with the reduction drawing rules, since the alignment precision is never reduced in the same ratio as the minimum resolution of the lithography. 'A fully self-aligned cell of the invention, _therefore, all the more interesting that the design rules evolve towards values submicron widely.

Claims

1. Memory device with a plurality of non-volatile memory cells each comprising a floating grid (28, 58, 34, 64), a source area. (20, 16) and a drain zone (22, 18, 14), self-aligned with respect to the floating grid, a channel zone and a control grid (68), the floating grid comprising a block (28, 32) of conductive or semiconductor material and a layer (58, 64) of conductive or semiconductor material, formed and etched above the pad (28, 32), in electrical contact therewith, and in which the cells of memory are arranged in rows and columns in a staggered pattern.

2. Device according to claim 1, in which the source zone of each memory cell is connected to ground.

3. Device according to claim 1, in which the layer (58, 64) of conductive or semiconductor material overflows on either side of each block (28, 32), above the source zones (20, 16) and drain (14, 18, 22).

4. Device according to claim 1, in which the control grid (68) is separated and isolated from the layer (58, 64) of conductive or semiconductor material by a first dielectric layer (66), and does not overflow on the part and on the other side of the layer (58, 64) of conductive or semiconductor material.

5. Device according to claim 4, further comprising a second layer of dielectric material (76), deposited over the control grid and the dielectric layer (66) which separates this control grid and the layer (58, 64 ) of conductive or semiconductor material, and first metallic lines (78, 80, 82, 84, 86), called bit lines, formed over the second layer (76) of dielectric material.

6. Device according to claim 5, comprising:

- a third layer (90) of dielectric material deposited over the first metallic lines (78, 80, 82, 84, 86) and the second layer (76) of dielectric material,

- second metal lines (90, 92, 94), called word lines, formed over the third layer (90) of dielectric material.

7. Device according to any one of the preceding claims, characterized in that the conductive or semiconductor material which constitutes the block (28, 32) is identical to the conductive or semiconductor material which constitutes the layer (58, 64) .

8. Device according to claim 7, characterized in that the conductive or semiconductor material is polycrystalline silicon.

9. Device according to any one of claims 1 to 6, characterized in that the conductive or semiconductor material which constitutes the block (28, 32) is different from the conductive or semiconductor material which constitutes the layer (58, 64) .

10. Method for producing a non-volatile memory device comprising a plurality of non-volatile memory cells (116, 118, 120, 122, 124, 126), each non-volatile memory cell comprising a memory point of the floating gate type (28, 58), a source area (16, 20), a source area drain (14, 18, 22), a channel zone and a control grid (68), the floating grid being produced by:

- depositing and etching a first layer of conductive or semiconductor material, so as to form a block (28, 32) of a first level of conductive or semiconductor material,

- Deposition and etching of a second layer of conductive or semiconductor material, over the block (28, 32) of the first level of conductive or semiconductor material and in electrical contact therewith, so as to form a layer (58, 64) of a second level of conductive or semiconductor material, the blocks of the first level of conductive or semiconductor material being produced by:

a first step of forming a strip (6, 8, 10, 12) of conductive or semiconductor material, in a first direction,

- a second step of etching the strip of conductive or semiconductor material, in a second direction perpendicular to the first, so as to release the block (28, 32), the cells being arranged in lines at a pitch X equal to the double the first step and in columns according to a step Y equal to the second step.

11. The method of claim 10, further comprising, between the first and second steps, a step of producing the source (16, 20) and drain (18, 22, 24) zones, self-aligned with respect to the strip (6, 8, 10, 12) of conductive or semiconductor material.

12. The method of claim 11, comprising, after the second step of etching the strip of conductive or semiconductor material, a step of producing isolation zones (44, 46, 48, 50) of the source and drain zones, these isolation zones being self-aligned with respect to the source zones (16, 20), drain (18, 22, 24) and relative to the pad ^* of conductive or semiconductor material (28, 32).

13. The method of claim 10, wherein before the deposition and etching of the second layer of conductive or semiconductor material, a thick layer (52) of dielectric material is deposited so as to cover the blocks (28, 32) and the layer of dielectric material is subjected to a chemical-mechanical planarization treatment with stopping on said block.

14. The method of claim 10, the layer (58, 62) of the second level of conductive or semiconductor material projecting on either side of the block of the first level of conductive or semiconductor material.

15. The method of claim 10, further comprising:

- a step of depositing a first dielectric layer (66) over the second layer of conductive or semiconductor material, - a step of forming a control grid (68, 70, 72) on this first dielectric layer , the control grid not projecting on either side of the layer of conductive or semiconductor material (58, 64).

16. The method of claim 10, further comprising a step of producing word lines (92, 94, 96) and bits (78, 80, 82, 84, 86) associated with the volatile memory cell.

17. The method of claim 10, the source areas (100, 104, 106) of the cells of the same column being produced according to a continuous area from the electrical point of view.