WO2000017788A1 - Dispositifs et procedes de traitement logique - Google Patents

Dispositifs et procedes de traitement logique Download PDF

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Publication number
WO2000017788A1
WO2000017788A1 PCT/US1999/021955 US9921955W WO0017788A1 WO 2000017788 A1 WO2000017788 A1 WO 2000017788A1 US 9921955 W US9921955 W US 9921955W WO 0017788 A1 WO0017788 A1 WO 0017788A1
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WIPO (PCT)
Prior art keywords
vectors
vector
logic
logical circuit
points
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Application number
PCT/US1999/021955
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English (en)
Inventor
Jonathan Westphal
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Vectorlog
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Publication date
Application filed by Vectorlog filed Critical Vectorlog
Priority to EP99948387A priority Critical patent/EP1116142A1/fr
Priority to AU61580/99A priority patent/AU6158099A/en
Publication of WO2000017788A1 publication Critical patent/WO2000017788A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Definitions

  • This invention relates to the field of logical processing and, more particularly to devices and techniques for simplifying digital logic.
  • Logic can be described as techniques and operations by which one moves from what one knows to be true to new truths.
  • the principles of logic have been applied in the design and operation of digital logic circuits.
  • Modern-day computers and other processing devices have utilized digital logic extensively.
  • Many of the problems to which digital logic can be applied are complex, involving many independent variables. This results in extremely complex logical circuits in which large numbers of operations are performed. The cost associated with manufacturing and fabrication of such complex digital circuits is great. It would be highly desirable to reduce the number of complements required for performing a particular logical function or set of functions while at the same time increasing the speed with which those functions can be performed.
  • Digital computers are, of course, well-known. More recently, optical computers have been developed which can perform logical functions using optical elements. These optical computers can perform the same functions performed by digital computers but in principle much faster.
  • the invention is directed to apparatus, methods, systems and computer program products which permit a simplification of the logic required for performing a certain function to a minimum set of logical elements of operations.
  • the this permits the complexity of digital circuitry to be simplified the processing speed with which complex digital operations can be performed, reduced.
  • Figure 1 represents two-dimensional space for propositions.
  • Figure 2 illustrates the propositions P and V ⁇ V in the space of figure 1 •
  • Figure 3 is a diagram of the vector two-dimensional space showing in the conditional normal schemata or CNS-plane.
  • Figure 4 is a diagram of the vector two-dimensional space showing the alternational normal schemata or the ANS- plane.
  • Figure 5 is a diagram showing modus ponens in the CNS-plane.
  • Figure 6 is a diagram showing modus tollens in the CNS- plane
  • Figure 7 use a diagram showing the disjunctive syllogism in the CNS- plane.
  • Figure 8 is the diagram showing how the ANS- and CNS- planes relate.
  • Figure 9 is a diagram illustrating operations within the ANS- space.
  • Figure 10 shows an extension of the ANS- plane of Figure 4 to a three-dimensional ANS- space.
  • Figure 11 shows an extension of the CNS- space to three dimensions together with a hypothetical syllogism.
  • Figure 12A illustrates a hypothetical syllogism with three variables in the CNS- space.
  • Figure 12B shows a view of the hypothetical syllogism in the three-dimensional CNS- space.
  • Figure 13 A illustrates a cancellation technique used in simplifying logical representations and in accordance with the invention.
  • Figure 13B shows the representations of Figure 13 A in graphical form.
  • Figure 13C illustrates implication and equivalence.
  • Figures 14 A, 14B and 14C illustrate a solution to the simplification problem using the techniques of the invention.
  • Figure 15 shows a 4-clause schema simplified.
  • Figure 16A shows a 3-clause schema simplified.
  • Figure 16B shows the truth-table for the representation of Figure 16A.
  • Figure 17 shows a 4-variable vector diagram simplification.
  • Figure 18B is an illustration of an example of the Fix Rule.
  • Figure 20 illustrates application of the invention to situations in which developed normal formulas are not the point of departure.
  • Figure 21 illustrates the equivalence of a developed alternational formal and its undeveloped counterpart.
  • Figure 22 illustrates the simplification of an undeveloped set of statements.
  • Figure 23 illustrates another simplification of an undeveloped set of statement taken from Quine.
  • Figure 24 illustrates an equivalence within the set of statements shown in Figure 23.
  • Figure 24A illustrates superfluity in the Consensus Theorem and its dual in the CNS- form in a truth-table.
  • Figure 25 illustrates the Consensus Theorem.
  • Figure 26 illustrates the dual of the Consensus Theorem.
  • Figure 27 illustrates a superfluity shown in Figure 23.
  • Figure 28 illustrates a target circuit to be simplified in accordance with the invention.
  • Figure 29 shows a simplest circuit equivalent to the target circuit.
  • Figure 30 is an illustration of optical computation of modus ponens.
  • Figure 31 is an illustration of interferometric processing for modus ponens to the Figure 32 illustrates an optical element used for disconj unction and conjunction in a free- space optical processing.
  • Figure 33 is an illustration of flat optical processing.
  • Figure 34 or is an illustration of vector addition utilizing sequences of spatial light modifiers.
  • Figure 35 is an illustration of colorimetric computation of modus ponens.
  • Figure 36 is a colorimetric simplification of pq v p q .
  • Part I of this paper describes a system of propositional logic in which propositions are represented as vectors or displacements in a space.
  • Part II gives the application of the system to the simplification problem, the problem of finding a method for reducing a truth-functional schemata in altemational normal form to a shortest equivalent.
  • Part III is about applications: (i) to problems of electrical circuit minimization; (ii) to free-space optical processing; (iii) to "flat" optical processing; and (iv) to logical processing using colorimetry.
  • V is for vector, which is from the Latin word meaning “carrier”, “traveller” or “ rider”.
  • the V-diagram can be further built up by adding the negation symbols for the negative vectors p and q in the negative or reverse directions along their respective axes. So we arrive at all of the literals, which are single letters and negations of single letters, and we can also find pairs of single negated or unnegated letters, the propositions p v q , and p v q .
  • the plane of theretemational normal schemata or the ANS-plane as I shall call it, in which the points are not alternations but conjunctions, and the vector operation "+" within the space is interpreted as alternation.
  • the ANS-plane and the CNS-plane are duals, so that each point in each plane correspond to its dual in the other plane. This also means that the uniting operation in the CNS-plane is related to the dual of the operation in the ANS-plane, and vice versa. In the CNS-plane "+" is alternation, and so in the ANS-plane it is conjunction.
  • Together with here means treating the points and directions algebraically as themselves directions from the origin. This yields a cancellation technique in which a starting-point of 0 is cancellation of no literal, and an end point of 0 is the cancellation of all the literals
  • disjunct of this is equivalent to p p, and so it is always false. Hence the alternation is equivalent to the second disjunct, or the assertion pq.
  • O has the effect of reversing the truth- values of the base propositions.
  • O Moving towards O from the base (p,q) in the CNS- space we get the vector p v q. O has the effect of putting p and q through the Sheffer- function "
  • the vector moving away from O in the CNS-space towards e.g. (p,q) is
  • N in the Tractatus could be described as a generalization of 4- to more than two places, as N(p,q,r), for example, is pqr.
  • N(p,q,r) for example, is pqr.
  • the simplification problem is the problem of reducing truth-functional schemata (or, in the system I am describing, systems of vectors in the ANS-space) to their shortest equivalents.
  • a practical method for doing this, in altemational normal form continues, as Quine observes (Quine, 1982, p. 78), to be suprisingly elusive.
  • each clause or disjunct of t is a position vector (i.e. one pointing to O) with O at one comer of a parallelogram made of propositional addresses to the i-point at the other . Any two other outside vertices of such a parallelogram are implicants which are among the original clauses of t.
  • the first job is to plot the target schema in a V-diagram.
  • the target schema is equivalent to qr v pr .
  • the whole figure in Figure 17 is a "measure polytope" or hypercube, though one with a further complex internal structure.
  • tessellation to the number of propositional variables or vectors p, q, r s ... that can be handled, because the space is derived not from a closed figure, such as a cube, but from a sheaf of lines in the geometrical sense. Not all closed figures tessellate. All the lines of the multidimensional sheaves are coincident.
  • v is the number of vectors required to make the fix on the ⁇ -point
  • d is the drop in the number of literals from the clauses of the given schema to the resulting clause in the target schema.
  • the vector summation of p q and q r to p qq r or p q r is disallowed by the Fix Rule, according to which the number of vectors needed to make a fix is equal to the d-th power of 2. This summation would actually produce a negative value for d. As the number of literals rises from two to three, the drop increases from 2 to 3, or -1.
  • Quine gives another interesting example of a simplification with four simplest equivalents, one which also illustrates the method of simplification for non-developed or unbalanced schemata like the last example.
  • the example (Quine, 1952, p. 528) is pqr v pr v pqs v j r v p q r s ( Figure 23).
  • the charm of a vector simplification technique is that is follows a least-action principle, for any number of propositional vectors, in the sense that the problem is not one of finding shortest equivalents to truth-functional schemata. Rather the space, inasmuch as it is fixed vector space in which all free vectors having the same direction are in a sense the same directional vector, is unable not to give the desired result.
  • the first job is to plot this in the ANS-space as the set of vectors pqr v pr v pqs v p r v p q r s , as in Figure 23 above.
  • this system of vectors e.g., pq v p r v pr v p q s (cf. p. 39).
  • the resultant schema can then be translated into the circuit diagram AB + A C + A C + A B D ( Figure 29).
  • a beam V can be sent from the origin to a half-darkening beamsplitting mirror at the node p. At p it is split and sent at half-strength to q, and to q .
  • a second beam U from O is sent to the node pv q, which is also p— >q.
  • Both half-implication beams are coincident on q, and at q the photoreceptor gives a reading of .5 + .5 or 1.
  • the system has optically computed modus ponens; from an input of p and an input of p v q, it has yielded up q.
  • the system gives a physical interpretation of beamsplitting as multiple implication and of darkening as fractional implication.
  • the beamsplitter at p v q itself directs the beam to q at only half- strength, and the desired computation is achieved.
  • a second method of exploiting the vector system for computation is more markedly spatial.
  • SLMs spatial light modifiers
  • Colored laser beams can be used so that the refractive angle is built into the vector rather than into the propositional nodes as the CIE (Commission Internationale de 1' Eclairage) x-y chromaticity diagram (a color mixing diagram) is itself a vector space. (Or a mixed system of colored laser and colored mirrors could be used.) Then optical computation for simplification is simply the colorimetric process of additive color mixing.
  • p red
  • Y yellow
  • B complementary blue
  • YR p v q yellow-red
  • BR p v q blue-red
  • p v q is the complementary of YR, a cyan blue.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Complex Calculations (AREA)

Abstract

L'invention concerne un appareil, des procédés, des systèmes et des produits de programme informatique qui permettent de simplifier la logique requise pour réaliser une fonction. Grâce à une série minimale d'éléments logiques d'opérations, un circuit numérique complexe peut être simplifié, de façon à réduire la vitesse de traitement permettant de réaliser les opérations numériques complexes. A cet effet, on utilise un système de logique propositionnelle (13B), on représente la logique d'un circuit logique sous forme de points et de vecteurs dans un espace vectoriel, on fait prendre une forme simplifiée à la logique d'un circuit logique, au moyen des points et des vecteurs dans un espace vectoriel, enfin on conçoit le circuit sous une forme simplifiée.
PCT/US1999/021955 1998-09-22 1999-09-22 Dispositifs et procedes de traitement logique WO2000017788A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP99948387A EP1116142A1 (fr) 1998-09-22 1999-09-22 Dispositifs et procedes de traitement logique
AU61580/99A AU6158099A (en) 1998-09-22 1999-09-22 Devices and techniques for logical processing

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US10137198P 1998-09-22 1998-09-22
US60/101,371 1998-09-22

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WO2000017788A1 true WO2000017788A1 (fr) 2000-03-30

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DK2672215T3 (en) 2012-06-08 2014-12-08 Alfa Laval Corp Ab PLATE HEAT EXCHANGE
CN103034758B (zh) * 2012-12-07 2015-03-11 南通大学 集成电路逻辑优化并行处理方法
CN111857822B (zh) * 2016-08-05 2024-04-05 中科寒武纪科技股份有限公司 一种运算装置及其操作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640328A (en) * 1994-04-25 1997-06-17 Lam; Jimmy Kwok-Ching Method for electric leaf cell circuit placement and timing determination
US5649165A (en) * 1995-01-31 1997-07-15 Fujitsu Limited Topology-based computer-aided design system for digital circuits and method thereof
US5920484A (en) * 1996-12-02 1999-07-06 Motorola Inc. Method for generating a reduced order model of an electronic circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640328A (en) * 1994-04-25 1997-06-17 Lam; Jimmy Kwok-Ching Method for electric leaf cell circuit placement and timing determination
US5649165A (en) * 1995-01-31 1997-07-15 Fujitsu Limited Topology-based computer-aided design system for digital circuits and method thereof
US5920484A (en) * 1996-12-02 1999-07-06 Motorola Inc. Method for generating a reduced order model of an electronic circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NGUYEN T.V. ET AL.: "Multipoint Pade Approximation Using a Rational Block Lanczos Algorithm", 1997 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN, 1997, DIGEST OF TECHNICAL PAPERS, 9 November 1997 (1997-11-09), pages 72 - 74, XP002926264 *

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EP1116142A1 (fr) 2001-07-18
AU6158099A (en) 2000-04-10

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