AU6158099A - Devices and techniques for logical processing - Google Patents
Devices and techniques for logical processingInfo
- Publication number
- AU6158099A AU6158099A AU61580/99A AU6158099A AU6158099A AU 6158099 A AU6158099 A AU 6158099A AU 61580/99 A AU61580/99 A AU 61580/99A AU 6158099 A AU6158099 A AU 6158099A AU 6158099 A AU6158099 A AU 6158099A
- Authority
- AU
- Australia
- Prior art keywords
- techniques
- devices
- logical processing
- logical
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10137198P | 1998-09-22 | 1998-09-22 | |
US60101371 | 1998-09-22 | ||
PCT/US1999/021955 WO2000017788A1 (en) | 1998-09-22 | 1999-09-22 | Devices and techniques for logical processing |
Publications (1)
Publication Number | Publication Date |
---|---|
AU6158099A true AU6158099A (en) | 2000-04-10 |
Family
ID=22284315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU61580/99A Abandoned AU6158099A (en) | 1998-09-22 | 1999-09-22 | Devices and techniques for logical processing |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1116142A1 (en) |
CN (1) | CN1384944A (en) |
AU (1) | AU6158099A (en) |
WO (1) | WO2000017788A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DK2672215T3 (en) | 2012-06-08 | 2014-12-08 | Alfa Laval Corp Ab | PLATE HEAT EXCHANGE |
CN103034758B (en) * | 2012-12-07 | 2015-03-11 | 南通大学 | Logic optimizing and parallel processing method of integrated circuit |
CN107688466B (en) * | 2016-08-05 | 2020-11-03 | 中科寒武纪科技股份有限公司 | Arithmetic device and operation method thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5640328A (en) * | 1994-04-25 | 1997-06-17 | Lam; Jimmy Kwok-Ching | Method for electric leaf cell circuit placement and timing determination |
US5649165A (en) * | 1995-01-31 | 1997-07-15 | Fujitsu Limited | Topology-based computer-aided design system for digital circuits and method thereof |
US5920484A (en) * | 1996-12-02 | 1999-07-06 | Motorola Inc. | Method for generating a reduced order model of an electronic circuit |
-
1999
- 1999-09-22 AU AU61580/99A patent/AU6158099A/en not_active Abandoned
- 1999-09-22 EP EP99948387A patent/EP1116142A1/en not_active Withdrawn
- 1999-09-22 CN CN99811246A patent/CN1384944A/en active Pending
- 1999-09-22 WO PCT/US1999/021955 patent/WO2000017788A1/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
WO2000017788A1 (en) | 2000-03-30 |
CN1384944A (en) | 2002-12-11 |
EP1116142A1 (en) | 2001-07-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |