WO2000016393A1 - Procede de formation d'interconnexions par depot selectif - Google Patents

Procede de formation d'interconnexions par depot selectif Download PDF

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Publication number
WO2000016393A1
WO2000016393A1 PCT/US1999/019335 US9919335W WO0016393A1 WO 2000016393 A1 WO2000016393 A1 WO 2000016393A1 US 9919335 W US9919335 W US 9919335W WO 0016393 A1 WO0016393 A1 WO 0016393A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductive
polishing
conductive material
forming
Prior art date
Application number
PCT/US1999/019335
Other languages
English (en)
Inventor
Geeng-Chuan Chern
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corporation filed Critical Atmel Corporation
Publication of WO2000016393A1 publication Critical patent/WO2000016393A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

Definitions

  • the present invention relates generally to semiconductor manufacture and more specifically to a method for forming interconnect structures.
  • CMP Chemical mechanical polishing
  • a CMP polisher comprises a polishing table and a holder for holding the wafer to be polished.
  • a slurry is continuously supplied upon the wafer as a polishing pad is drawn across the wafer. Polishing by CMP involves a combination of chemical reactions between wafer and slurry, and the combined mechanical action of the slurry and the polishing pad.
  • the method of forming an interconnect in accordance with the invention includes depositing an insulative layer atop a layer of conductive material.
  • This bottom layer may be a conductive layer comprised of active devices, or it may be the metallization layer of a lower interconnect level.
  • the insulative layer is etched to form trenches which will be the traces of the interconnect structure.
  • one or more contact holes (vias) to the bottom conducting layer are formed through the insulative layer.
  • a liner layer is then deposited over the insulative layer, including those portions of the insulative layer within the trenches and the contact holes.
  • portions of the liner layer outside of the trenches and contact holes are removed.
  • a conductive material is selectively deposited atop the remaining portions of the liner layer.
  • a light planarization step may be applied to improve the planarity of the deposited material by compensating for tolerance variations of the selective deposition.
  • Figs. 1A - IF show the processing steps of the present invention.
  • a conductive layer 100 is formed atop a semiconductor substrate 10.
  • the conductive layer 12 may be a portion of an active devices as shown in the figure.
  • two or more levels of interconnect may be needed to connect the devices.
  • conductive layer 100 may be a lower interconnect layer, in which case the elements identified by reference numeral 12 are the traces of a lower interconnect layer.
  • Fig. IB shows the application of a planarized layer 20 atop the conductive layer.
  • insulation layer 20 is formed by chemical vapor deposition (CVD) of an intermetal dielectric such as Si0 2 .
  • CVD chemical vapor deposition
  • any of a number of alternate intermetal dielectrics can be used and deposited by methods including plasma-enhanced CVD of Si0 2 , bias-sputtered Si0 2 , low temperature decomposition of tetraethoxysilane (TEOS) gas to form a Si0 2 film, spin-on glass, low dielectric constant materials, various nitride compounds, and combinations of the above.
  • planarization can be achieved by known methods such as CMP.
  • a planar deposition method such as high density plasma (HDP) CVD can be used.
  • HDP high density plasma
  • a pattern of trenches 30 and contact holes (vias) 32 are formed into insulation layer 20.
  • the trenches 30 will eventually be filled with a conductive metal which constitutes the traces of the interconnect structure.
  • vias 32 will be filled with conductive material to provide electrical contact between the interconnect and the underlying active devices.
  • the vias provide an electrical connection to the traces of the underlying interconnect.
  • the trenches and vias are formed by depositing a first dielectric layer atop substrate 10. Then an etch stop layer is deposited over the first dielectric layer and patterned with openings that correspond with vias 32. A second dielectric layer is then deposited over the etch stop. The second dielectric layer is patterned with a mask having the desired pattern of trenches 30. An etch step is then performed to etch away the portions of the second dielectric layer to form the trenches. The etch stop layer limits the depth of the trenches. Where there are openings in the etch stop layer which expose portions of the first dielectric layer, etching continues to form vias 32. In an alternate technique, a single dielectric layer would be deposited and etched to form trenches 30 and vias 32.
  • a thin liner layer 40 of conductive material is formed.
  • the liner layer serves as an adhesive layer to facilitate the adhesion of the subsequent conductive material onto insulation layer 20.
  • the liner layer also serves as a barrier layer to protect the underlying metal during a subsequent metal deposition step.
  • the material for the liner layer can be any of a number of metallic compounds such as titanium nitride (TiN) , tantalum nitride (TaN) , a multi-layered combination of titanium and TiN, or a titanium-tungsten alloy.
  • Liner layer 40 can be deposited by a sputter deposition method, by CVD, or by a physical vapor deposition process such as an evaporation process. As can be seen in Fig. ID, liner layer 40 is formed upon all of the exposed surfaces of insulation layer 20, including the vertical walls of trenches 30 and vias 32 and upon the exposed portions of the underlying conductive layer 100. Following deposition of the thin liner layer
  • Fig. IE where the uppermost surfaces 21 of insulation layer 20 become exposed.
  • a CMP process can be used.
  • liner layer 40 is thin.
  • an advantage of the present invention is that a CMP polishing step at this point in the process is simpler and less costly as compared to prior art techniques where CMP polishing is applied as a final step to a thick layer of metal.
  • U.S. Patent No. 4,789,648 shows in Fig.
  • metallization layer 9 which is subsequently polished by CMP.
  • Another important aspect of the present invention is that as a consequence of the etchback or polishing step, portions of the underlying surface 21 of insulation layer 20 are exposed and portions of liner layer 40 remain. As will be explained, the presentation of two different surfaces is ideal for the subsequent selective deposition of conductive material to fill trenches 30 and vias 32.
  • the interconnect is formed by deposition of conductive material 50 in the trenches and vias.
  • a preferred material is copper, but other conductive metals such as tungsten (W) , nickel (Ni, or aluminum (Al) are contemplated.
  • W tungsten
  • Ni nickel
  • Al aluminum
  • the presence of the two surfaces, namely liner layer 40 and insulation layer 20, permits the use of a selective deposition process of the conductive material; e.g., electroless plating deposition of metals such as Cu, Ni, Au or Pd, or by a selective CVD technique.
  • selective deposition of tungsten e.g., electroless plating deposition of metals such as Cu, Ni, Au or Pd.
  • the electrophysical properties of the two different surfaces enables tungsten to form in the trenches and vias where liner layer 40 is present and not upon exposed surfaces 21 of insulation layer 20.
  • This can be achieved, for example, in a hydrogen reduction reaction of tungsten hexafluoride (WF 6 ) below approximately 500 degrees C.
  • WF 6 tungsten hexafluoride
  • the surface dissociation of H 2 molecules into atomic hydrogen will not be catalyzed by the Si0 2 comprising the insulation layer, but will be catalyzed on other surfaces such as that of liner layer 40.
  • tungsten will be selectively deposited only within the trenches and the vias, while leaving exposed the surfaces 21 of insulation layer 20 as shown in Fig. IF.
  • the result is an interconnect structure that requires no subsequent planarization step. However, it may be desirable to perform a light etch to improve the deposition process variation tolerance.
  • Another example is to use an electroless plating technique to deposit metals such as Cu, Ni, Au, Pd, etc.
  • electroless plating the wafer to be plated is immersed in a chemical solution containing metal ions without applying an electric current or potential through electrodes. Plating occurs only to those surfaces on the wafer which have a proper electrochemical potential in the solution.
  • a liner layer 40 can be formed of a combination of a thin sputtered Cu layer atop a layer of TaN.
  • a subsequent electroless deposition step in a Cu-containing solution will deposit copper in the trenches and vias 30 and 32 as conductive material 50, while leaving the dielectric materials of exposed surfaces 21 virtually untouched.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention porte sur un procédé de formation d'une interconnexion multiniveau qui consiste à déposer une couche (20) de matériau isolant sur une première couche (10) conductrice. Des tranchées et des trous d'interconnexion sont formés dans la couche (20) isolante. Une couche (40) de revêtement mince est déposée sur le dessus de la couche (20) isolante. Des parties de la couche (20) isolante sous-jacente à l'extérieur des tranchées et des trous d'interconnexion sont exposées sous l'effet de l'attaque chimique des parties de la couche (40) de revêtement. Un dépôt sélectif ultérieur d'un matériau (50) conducteur est effectué uniquement dans les tranchées et les trous d'interconnexion, ce qui crée l'interconnexion.
PCT/US1999/019335 1998-09-17 1999-08-24 Procede de formation d'interconnexions par depot selectif WO2000016393A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15480198A 1998-09-17 1998-09-17
US09/154,801 1998-09-17

Publications (1)

Publication Number Publication Date
WO2000016393A1 true WO2000016393A1 (fr) 2000-03-23

Family

ID=22552846

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/019335 WO2000016393A1 (fr) 1998-09-17 1999-08-24 Procede de formation d'interconnexions par depot selectif

Country Status (2)

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TW (1) TW437041B (fr)
WO (1) WO2000016393A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits

Also Published As

Publication number Publication date
TW437041B (en) 2001-05-28

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