WO2000013431A2 - Device and method for generating orthogonal codes in mobile communication system - Google Patents
Device and method for generating orthogonal codes in mobile communication system Download PDFInfo
- Publication number
- WO2000013431A2 WO2000013431A2 PCT/KR1999/000494 KR9900494W WO0013431A2 WO 2000013431 A2 WO2000013431 A2 WO 2000013431A2 KR 9900494 W KR9900494 W KR 9900494W WO 0013431 A2 WO0013431 A2 WO 0013431A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- orthogonal code
- bit number
- effective bit
- chip count
- generating
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J13/00—Code division multiplex systems
- H04J13/10—Code generation
- H04J13/12—Generation of orthogonal codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J13/00—Code division multiplex systems
- H04J13/0007—Code type
- H04J13/004—Orthogonal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/02—Channels characterised by the type of signal
- H04L5/023—Multiplexing of multicarrier modulation signals
- H04L5/026—Multiplexing of multicarrier modulation signals using code division
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
Definitions
- the present invention relates to a device and method for generating orthogonal codes in a mobile communication system, and in particular, to a device and method for generating orthogonal codes differing in length according to various symbol rates.
- orthogonal codes are used for spreading channels and for distinguishing between channels as identifiers.
- a Walsh code (which is one form of the orthogonal code) having a 64-chip length has been used to maintain orthogonality between channels and to spread bands.
- a band spreading rate of 1.2288 Mcps is obtained, since the symbol rates of coded data for various channels which are provided from a modulator of the transmitter to a spreader are uniformly maintained at 19.2 Kbps.
- a 64 x 64 Walsh code table has been used.
- an object of the present invention to provide a device and method for generating orthogonal codes differing in length according to various symbol rates in a mobile communication system.
- a device for generating orthogonal codes in a mobile communication system includes a memory having registers for respectively storing an effective bit number, an orthogonal code index and a chip count value, and an orthogonal code generating circuit for sequentially generating the chip count value up to a maximum value which can be counted by the effective bit number, and generating an orthogonal code by logic operation of the orthogonal code index and the sequentially generated chip count values.
- a method for generating orthogonal codes in a mobile communication system includes the steps of: calculating an orthogonal code length corresponding to a variable symbol rate; determining an effective bit number by the calculated orthogonal code length; sequentially generating a chip count value up to a maximum value which can be counted by the effective bit number; converting an orthogonal code index into a binary number of the effective bit number; and performing a logic operation of the orthogonal code index converted into the binary number and the sequentially generated chip count values to generate an orthogonal code.
- FIG. 1 is a block diagram illustrating a modulator of a mobile communication system according to an embodiment of the present invention
- FIG. 2 is a diagram illustrating an orthogonal code generating process expressed by an equation according to an embodiment of the present invention.
- FIG. 3 is a circuit diagram illustrating the orthogonal code generator illustrated in FIG. 1.
- FIG. 1 illustrates a modulator of a mobile communication system according to an embodiment of the present invention.
- the description of the modulator will be focused on parts relating to orthogonal spreading.
- a demultiplexer (DEMUX) & signal mapping circuit 1 1 1 demultiplexes input symbol data (or coded data) to separately output an I- channel (or first channel) signal and a Q-channel (or second channel) signal.
- the DEMUX & signal mapping circuit 111 also converts a level of the symbol data, for instance, "0" into “+1” and “1” into “-1”.
- First and second channel gain controllers 115 and 116 control gains of the first and second channel signals output from the DEMUX & signal mapping circuit 111, respectively, by a gain control signal provided by a controller 113.
- a memory 112 stores data for various programs and data temporarily generated in the course of executing the programs.
- the memory 112 includes a register having information about orthogonal code lengths varying with symbol rates of channels, a register having orthogonal code indexes assigned to the channels, and a register having chip counts, which are obtained by counting one symbol to be orthogonally spread by a corresponding chip clock.
- the information about the orthogonal code lengths which is described below, can be defined as a meaning to restrict an actually effective bit number of the orthogonal code index and chip count.
- the controller 113 controls the overall operation of the modulator. More particularly, the controller 113 reads parameters relating to generating the orthogonal code from the memory 112 and provides the parameters to an orthogonal code generator 114 of each channel generator.
- the orthogonal code generator 114 generates a corresponding orthogonal code according to the orthogonal code length information (i.e., the effective bit number), orthogonal code index and chip count provided from the controller 113.
- First and second multipliers 117 and 118 multiply the first and second channel signals output from the first and second channel gain controllers 1 15 and 116 by the orthogonal code to generate orthogonally modulated first and second channel signals IW and QW, respectively.
- the memory 112, controller 113, and orthogonal code generator In achieving a device for generating the orthogonal code according to the present invention, the memory 112, controller 113, and orthogonal code generator
- 1 14 may be indispensable constituents.
- orthogonal code generator 114 the term “orthogonal code generating circuit” will be used.
- the coded data (or symbol data) is separated by the DEMUX & signal mapping circuit 111 into the first and second channel signals.
- the separated signals are gain- controlled by the first and second channel gain controllers 115 and 116, as instructed by the controller 113.
- the gain-controlled first and second channel signals are respectively provided to the first and second multipliers 117 and 118.
- the controller 113 receives the orthogonal code length corresponding to a symbol rate of the coded data, the chip count and the orthogonal code index to be assigned to the channel. Those parameters are obtained by accessing the registers contained in the memory 112 and provided to the orthogonal code generator 114 of a corresponding channel generator.
- the orthogonal code generator 114 then generates a corresponding orthogonal code through a program stored in its internal DSP (Digital Signal Processor) or through an ASIC (Application Specific
- the generated orthogonal code is provided to the multipliers 1 1 7 and 118.
- the multipliers 117 and 118 respectively multiply the gain- controlled first and second channel signals output from the first and second channel gain controllers 115 and 116 by the orthogonal code, to generate the orthogonally modulated first and second channel signals IW and QW corresponding to the I and Q channels, respectively.
- the process of generating the orthogonal code will now be described in more detail.
- the orthogonal code generating process is executed by the orthogonal code generating circuit, which consists of the controller 113 and the orthogonal code generator 114. It should be noted that the orthogonal code length information is used interchangeably as the effective bit number.
- the orthogonal code generating process is broadly divided into two steps; a first step of generating information needed to generate the orthogonal code, and a second step of generating the orthogonal code based on the generated information.
- the information needed is the orthogonal code index assigned to each channel, the chip count obtained by counting one symbol period by a chip clock, and the orthogonal code length.
- a symbol rate of data provided to a spreader in the process of modulating forward channels differs according to channel types, unlike the conventional IS-95 CDMA system.
- orthogonal code lengths become different according to the different symbol rates.
- the orthogonal code lengths may have 8, 16, 32, 64, 128, 256, 512, and 1024 chips. If the band spreading rate is 3.6864 Mcps, and the symbol rates of data provided to the spreader are 14.4 Kbps, 28.8 Kbps, 57.6 Kbps and 115.2 Kbps, the orthogonal code lengths become 256 chips, 128 chips, 64 chips and 32 chips to produce the band spreading rate of 3.6864 Mcps. That is,
- the orthogonal codes having different lengths according to the various symbol rates of data provided to the spreader are generated to obtain a uniform band spreading rate.
- a processor for controlling the modulator provides information relating to the orthogonal code length to the modulator.
- the base corresponding to each orthogonal code length is 2 and only the exponent differs. Therefore, the orthogonal code length information determined by the symbol rate uses the exponent.
- the processor provides the exponent to the modulator as orthogonal code length information I.
- the range of an orthogonal code index n assigned to each channel and a chip count t which is obtained by counting one symbol period using a chip clock, can flexibly be enlarged or reduced by the various orthogonal code lengths 4, 8, 1 6, 64, 128,—. More particularly, the orthogonal code index n and the chip count t are each determined within the same range of 0 ⁇ n, t ⁇ 2'-l .
- the orthogonal code index indicates a value expressing one of the integers within the above range as a binary number of I bits.
- the chip count sequentially designates an integer within the above range by a binary number of I bits.
- the orthogonal code index becomes a binary number expressing one of integers 0 to 15 as 4 bits.
- the chip count binary number values of 4 bits, that is, 0000 through 1111 are sequentially provided to designate integers ranging from 0 to 15.
- the bit number need not be restricted. Namely, it is possible to assign the bit number of the orthogonal code index and chip count up to the maximum bit number. Then all bits except actually effective bits among the assigned bit number are set to "0".
- the maximum bit number is determined on the basis of the longest Walsh code used in a mobile communication system.
- the orthogonal code length is determined by the designated symbol rate, and the range of the chip count and the orthogonal code index are determined by the orthogonal code length. Once the range of the chip count is determined, the chip count is sequentially increased within the determined range. The orthogonal code length, the orthogonal code index, and the increased chip count are provided as information for generating the orthogonal code. If the orthogonal code generator 114 has a function which can estimate the orthogonal code length by the orthogonal code index, the controller 1 13 need not provide the orthogonal code length information.
- the orthogonal code is generated by using the orthogonal code length information, the orthogonal code index assigned to each channel, and the chip count which are provided from the processor. That is, an algorithm is supplied with the orthogonal code length information in addition to the orthogonal code index and chip count so that the orthogonal codes of differing length can be generated.
- the processor for controlling the modulator determines the orthogonal code length information based on the symbol rate and provides this information to the orthogonal code generator 114, thereby generating the orthogonal code having a variable length according to the symbol rate.
- the orthogonal code of a necessary length is generated by restricting the number of digits of the orthogonal code index n and chip count t expressed as a binary number through the orthogonal code length information. This can be represented by Equation 1 :
- I orthogonal code length information (i.e., 2, 3, 4,...)
- n is an orthogonal code index assigned to each channel
- t is a chip count obtained by counting one symbol period by a chip clock.
- Equation 1 If the orthogonal code length information, the orthogonal code index and the chip count are designated by Equation 1, a corresponding one-chip orthogonal code is generated. As can be appreciated from Equation 1, an effective calculation range is determined by the orthogonal code length information I. Meanwhile, the orthogonal code of one bit is obtained by logic operation of bits constituting the chip count and bits constituting the orthogonal code index within the effective calculation range. That is, the chip count and the orthogonal code index are ANDed in the unit of bits and the ANDed results are XORed.
- Equation 2 Equation 2
- i is a temporary count parameter
- wc is a parameter in which a final value is to be stored
- length is a parameter having an orthogonal code length information value determined according to the symbol rate
- index is an orthogonal code index assigned to a channel
- count is a chip count obtained by counting one symbol period by a chip clock.
- the range of the chip count differs according to the orthogonal code length as listed below in Table 1 :
- the orthogonal code generating process may be achieved by a program as shown in Equation 2 on a DSP or by algorithm such as HDL (Hardware Development Language) on an ASIC.
- HDL Hardware Development Language
- the orthogonal code generator includes an AND gate circuit 310 consisting of a plurality of AND gates 310_0,...,310_M- 1 and an XOR gate 320.
- the orthogonal code having a length shorter than the longest orthogonal code length is generated, all bits other than the actually effective bits are considered to be "0". In other words, bits except the actually effective bits are considered masked to "0".
- the AND gates 310_0,...,310JV1-1 each perform an AND operation of a corresponding bit of the orthogonal code index and a corresponding bit of the chip count.
- the XOR gate 320 performs an XOR operation of the outputs of the AND gate circuit 310 to generate one bit constituting the orthogonal code.
- a reference symbol Walsh_Index is a register for storing the orthogonal code index to be calculated; Chip_count is a register for storing the current chip count; Walsh code is a currently calculated orthogonal code value; and M is a value expressing the longest orthogonal code length as 2 to the power of a prescribed number (for instance, if the longest orthogonal code length is 128 chips, M is 7).
- the orthogonal code index the actual information 011 is continuously provided together with 4 bits masked to "0".
- the chip count 4 bits masked to "0" and 3 least significant bits varying from 000 to 111 are provided.
- the output of the AND gate circuit 310 according to the orthogonal code index and the chip count is listed in below in Table 2.
- the outputs q 0 to q 6 of the AND gates 310_0,...,310_M-1 are provided to the XOR gate 320.
- the XOR gate 320 generates the orthogonal code "01100110" by XOR operation of the outputs q 0 to q 6 .
- the controller 113 has determined the information for generating the orthogonal code, including the chip count, and provided the information to the orthogonal code generator 114.
- the controller 113 may provide only the orthogonal code length and orthogonal code index, and the orthogonal code generator 114 generates the chip count.
- the orthogonal code generator should include a counter to generate the chip count based on the orthogonal code length.
- the present invention may usefully be applied to a CDMA-2000 mobile communication system in which symbol rates vary according to channel types. Furthermore, since there is no need to make various types of orthogonal code tables corresponding to the different orthogonal code lengths, multiple varying memories are not required and the hardware configuration can be realized by a common structure which is applicable to various symbol rates.
Abstract
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
BR9906781-1A BR9906781A (en) | 1998-08-28 | 1999-08-28 | Device and process for generating orthogonal codes in a mobile communication system |
AU55310/99A AU732063B2 (en) | 1998-08-28 | 1999-08-28 | Device and method for generating orthogonal codes in mobile communication system |
CA002309032A CA2309032A1 (en) | 1998-08-28 | 1999-08-28 | Device and method for generating orthogonal codes in mobile communication system |
EP99941826A EP1057287A2 (en) | 1998-08-28 | 1999-08-28 | Device and method for generating orthogonal codes in mobile communication system |
Applications Claiming Priority (2)
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KR1998/35118 | 1998-08-28 | ||
KR19980035118 | 1998-08-28 |
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WO2000013431A2 true WO2000013431A2 (en) | 2000-03-09 |
WO2000013431A3 WO2000013431A3 (en) | 2000-06-29 |
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PCT/KR1999/000494 WO2000013431A2 (en) | 1998-08-28 | 1999-08-28 | Device and method for generating orthogonal codes in mobile communication system |
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EP (1) | EP1057287A2 (en) |
CN (1) | CN1286840A (en) |
AU (1) | AU732063B2 (en) |
BR (1) | BR9906781A (en) |
CA (1) | CA2309032A1 (en) |
WO (1) | WO2000013431A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10305536B2 (en) | 1999-05-31 | 2019-05-28 | Electronics And Telecommunications Research Institute | Apparatus and method for modulating data message by employing orthogonal variable spreading factor (OVSF) codes in mobile communication system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US5533013A (en) * | 1992-12-01 | 1996-07-02 | Nokia Mobile Phones Limited | Communication method and system |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0918450A (en) * | 1995-06-27 | 1997-01-17 | Sony Corp | Code division multiplex transmitter |
JP3317866B2 (en) * | 1996-12-20 | 2002-08-26 | 富士通株式会社 | Spread spectrum communication system |
-
1999
- 1999-08-28 AU AU55310/99A patent/AU732063B2/en not_active Ceased
- 1999-08-28 CA CA002309032A patent/CA2309032A1/en not_active Abandoned
- 1999-08-28 BR BR9906781-1A patent/BR9906781A/en not_active IP Right Cessation
- 1999-08-28 EP EP99941826A patent/EP1057287A2/en not_active Withdrawn
- 1999-08-28 CN CN 99801662 patent/CN1286840A/en active Pending
- 1999-08-28 WO PCT/KR1999/000494 patent/WO2000013431A2/en not_active Application Discontinuation
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Publication number | Priority date | Publication date | Assignee | Title |
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US5533013A (en) * | 1992-12-01 | 1996-07-02 | Nokia Mobile Phones Limited | Communication method and system |
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PATENT ABSTRACTS OF JAPAN & JP 09 018 450 A (SONY CORP) 17 January 1997 * |
PATENT ABSTRACTS OF JAPAN & JP 10 190 520 A (FUJITS LTD) 21 July 1998 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10305536B2 (en) | 1999-05-31 | 2019-05-28 | Electronics And Telecommunications Research Institute | Apparatus and method for modulating data message by employing orthogonal variable spreading factor (OVSF) codes in mobile communication system |
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Publication number | Publication date |
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AU5531099A (en) | 2000-03-21 |
AU732063B2 (en) | 2001-04-12 |
BR9906781A (en) | 2000-12-05 |
CA2309032A1 (en) | 2000-03-09 |
WO2000013431A3 (en) | 2000-06-29 |
CN1286840A (en) | 2001-03-07 |
EP1057287A2 (en) | 2000-12-06 |
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