WO1999064953A1

WO1999064953A1 - Redundant form address decoder for cache system storing aligned data

Info

Publication number: WO1999064953A1
Application number: PCT/US1999/012719
Authority: WO
Inventors: David J. Sager; Andrew Glew
Original assignee: Intel Corporation
Priority date: 1998-06-08
Filing date: 1999-06-07
Publication date: 1999-12-16
Also published as: TW426848B

Abstract

A memory system includes a memory (220, 520) having a plurality of memory lines (222, 522) and an address decoder (210, 510) that enables one of the memory lines in response to a redundant form address signal. A redundant form decoder (230, 530) decodes redundant form data into a differential pair of decoded address signals, for each bit position of a memory address, which are applied to a memory line driver (240, 540). One of the two differential pairs carries correct address data. The one address line to be used is determined on a memory line basis, using the address of the memory lines themselves. The redundant form address decoder avoids a completion add that would otherwise be required, yielding very fast access to memory.

Description

REDUNDANT FORM ADDRESS DECODER FOR CACHE SYSTEM STORING ALIGNED DATA

BACKGROUND

The present invention relates to an address decoder for a memory.

Microprocessors and other integrated circuits store data in memory systems. The memory systems store digital data such as program instructions or variable data. Shown in FIG. 1 , a typical memory system 100 includes an address decoder 110, a memory 120 and, optionally, a selection switch 130. The memory 120 is organized into rows, called "memory lines." Each memory line possesses a unique address. When an address is applied to the address decoder 110, the address decoder 110 causes data stored in the associated memory line to be output from the memory system 100.

In certain applications, it may be preferable to retrieve only part of a memory line. For example, a processor may load data into the memory 120 one memory line at a time but may use the loaded data in smaller increments. In this type of application, the selection switch 130 permits a selected portion of a memory line to be output from the memory system 100. An output port of each memory line is coupled to a common bus that is applied to the selection switch. Thus, data from an enabled memory line is provided to the selection switch 130. The selection switch 130 selects a part of the memory line to be provided from the memory system 100.

To reference a desired portion of data in the form of signals, the address decoder 110 typically receives an address signal that identifies not only a requested memory line but also a portion of the memory line. The memory line is identified by a first part of the address (Addr_s-Addr_n); the portion of the memory line is identified by a second part of the address (Addr₀-Addr_s.,).

The address decoder 110 is shown in greater detail in FIG. 2. The address decoder 110 is populated by a plurality of AND gates, one per memory line in memory 120. Each AND gate, such as gate 112, receives an input signals for each bit position i that references the memory line (i = s to n). Also for each bit position i, the address signals Add are inverted (Addr^) so that either the true value of the address bit or its complement may be applied to an AND gate. For any AND gate, the gate is coupled to the one of Add or Add # that is a one when the appropriate address signal is applied.

For example, AND gate 112 should enable its memory line when address "0000" is applied to the address decoder. In response to "0000," Add = 0 for all i. However, Addrj#=l for all i. Therefore AND gate 112 receives input signals from Addr₀#, Addr,#, Addr₂#, etc. Similarly, AND gate 114 should enable its memory line when address "0001" is applied to the address decoder. Therefore, Add # is applied to AND gate 114 for all i≠O. For address "0001," Addr₀=l and is applied to the AND gate 114 instead of Addr₀#. Each AND gate is coupled to the address lines in accordance with the address to which the AND gate should be responsive.

It is a goal of memory systems to retrieve requested data as quickly as possible. Any delays that occur between the time that an address is posted and the time that the requested data is available for use are undesirable. At times, however, address data may be posted as one or more arithmetic operations. The arithmetic operations must be performed before an address may be applied to the address decoder 110. Traditional arithmetic operations are slow; they impose the undesired delay to data retrieval operations.

A traditional adder is shown in FIG. 3. There, four bit inputs X and Y are added together to obtain a four-bit sum S and a single bit carry C_out. The adder includes an internal carry chain that propagates between every bit position in the adder. A carry from a first bit position may affect the value of the sum at a second bit position (S₂). A carry from the second bit position may affect the value of the sum at a third bit position (S₃). The carry chain continues through to the most significant bit. Because the carries affect the value of the sum result, true results cannot be output from the adder until the carry chain has traversed the entire length of the adder.

When several arithmetic operations are performed sequentially, carry chains must be completed for each operation. Sequential arithmetic operations on address data cause memory operations to be very slow.

Accordingly, there is a need in the art for a memory system that provides for fast retrieval of requested data when data is subject to arithmetic operations.

"Redundant form" adders are known to be faster than traditional adders. An example of a three input redundant form adder is shown in FIG. 4. There, the adder generates a multi-bit sum, labeled "O," from inputs W, X and Y. Each "bit position" in the resulting sum (such as O₂) actually is represented by two bits. The redundant form adder does not possess the internal carry chain found in traditional adders. Accordingly, redundant form arithmetic operations are very fast relative to traditional arithmetic operations. To obtain a traditional, non-redundant result, the two bits at each bit position must be added together by a traditional adder. For example, the two bits of each sum position Oi output by the redundant form adder may be input to the traditional adder of FIG. 3 to obtain a non-redundant result. Traditional memory cannot operate on address data that is input in redundant form. No known memory system performs address decoding on address data in redundant form.

SUMMARY

Embodiments of the present invention provide a memory system that retrieves data based upon redundant form address data. The memory system includes a memory having a plurality of memory lines and an address decoder that enables one of the memory lines in response to a redundant form address signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a known memory system.

FIG. 2 is a block diagram of a known address decoder for a memory system.

FIG. 3 is a block diagram of a traditional adder circuit.

FIG. 4 is a block diagram of a known redundant form adder circuit.

FIG. 5 is a block diagram of a memory system constructed in accordance with a first embodiment of the present invention.

FIG. 6 is a block diagram of a redundant form decoder circuit constructed in accordance with an embodiment of the present invention.

FIG. 7 is a block diagram of a redundant form decoder constructed in accordance with an embodiment of the present invention.

FIG. 8 is a block diagram of a combinatorial stage of a redundant form address decoder constructed in accordance with an embodiment of the present invention.

FIG. 9 is a block diagram of a memory system constructed in accordance with a second embodiment of the present invention.

FIG. 10 is a block diagram of a combinatorial logic stage constructed in accordance with a second embodiment of the present invention.

FIG. 11 is a block diagram illustrating how addition of two non-redundant values to obtain a result in redundant form employing no addition.

DETAILED DESCRIPTION

An embodiment of the present invention provides a memory system that retrieves data based upon address information input signals in redundant form. When arithmetic operations are performed on address data signals, data retrieval from memory systems is made faster than data retrieval from traditional systems.

FIG. 5 illustrates a memory system 200 constructed in accordance with a first embodiment of the present invention. The memory system 200 includes an address decoder 210 and a memory 220. The address decoder 210 receives address data signals in redundant form; that is, two bits per "bit position" O,. For notational purposes, the two bits of O, are labeled A, and B, respectively. Based on the value of the redundant form address data signals, the address decoder 210 accesses a selected memory line 222 in the memory 220. The memory 220 outputs signals data from the selected memory line 222.

The address decoder 210 may be a two-stage decoder in this embodiment. The first stage 230 comprises a redundant form decoder in which the redundant form address data signals are decoded into address signal lines in the embodiment. For all bit positions i (i≠O), the redundant form decoder 230 generates four address signals, labeled Z_ιa, Z_lb, Z_1C and Z_ld, in differential pairs (Z,_a=Z_lb#, Z,_c=Z,_d#). The redundant form decoder 230 is populated by a number of redundant form decoding circuits (not shown). The second stage comprises a memory line driver 240 in which the address decoder 210 generates memory line enable signals based upon data signals on the address lines.

FIG. 6 illustrates a redundant form decoder circuit 300 for bit position O, (i≠O) constructed in accordance with an embodiment of the present invention. The decoder circuit 300 generates address signals Z_ιa, Z,_b, Z_1C and Z_ld based upon the values of O, (A„ B,) and O, , (A,., and B,.,). Values A„ B„ A,., and B,., are input to the decoder 300 on input ports 302, 304, 306 and 308 respectively. Address signals Z_ιa, Z_lb, Z_1C and Z_ld are output from the decoder 300 on output ports 310, 312, 314 and 316 respectively.

A, and B, are input signals to a first XOR gate 320. XOR gate 320 generates an output signal on line 322. Line 322 is input to a pair of XOR gates 324 and 326. XOR gate 324 generates the first differential pair of address signals Z_ιa and Z_lb. XOR gate 326 generates the second differential pair of address signals Z_1C and Z_ld.

A,., and B,_, are input to an AND gate 328 and to an OR gate 334. AND gate 328 generates an output signal on line 332 which is input to XOR gate 324. The OR gate 334 generates an output signals on line 338 which is input to XOR gate 326.

The redundant form decoder circuit 300 resembles a traditional adder to a great degree. Line 322 represents a non-redundant sum that would be obtained by adding A, to B,. Lines 332 and 338 represent carries from position i-l under appropriate circumstances:

The signal on line 332 represents the carry from position i-l when S,.,=l (as described later).

The signal on line 338 represents the carry from position i-l when S,.,=0 (as described later).

Thus, either Z_ιa or Z,_c represents the non-redundant sum bit S,. Identification of the one address line that carries the correct value of S, is determined based on additional information. This is discussed in connection with FIG. 8 below. A traditional adder, however, employees an internal carry chain that propagates through every bit position in the addition in this embodiment. The redundant form decoder circuit 300 does not include any carry in from position i-2 in this embodiment.

The redundant form decoder circuit 300 may be but one stage of a multi-bit decoder. The gates shown in FIG. 6 may be shared with other stages to form a complete multi-bit decoder. For example, additional gates 340 and 342 (shown in phantom) illustrate gates that would be provided to couple input signals Aj and B_f to the i+1 position decoder. They correspond to gates 328 and 334 in the i^th position decoder. Gate 330 (also in phantom) may be used in an i-l position decoder.

FIG. 7 illustrates a redundant form decoder circuit 400 constructed in accordance with an embodiment of the present invention. The decoder circuit 400 is suitable for use with redundant form bit O₀. Again, for notational purposes, the two bits of O₀ are represented as A₀ and B₀ respectively. They are input to the decoder circuit 400 at input terminals 402 and 404. The decoder circuit 400 generates a single differential pair of address lines Z_0a and Z_ob on output terminals 406 and 408.

Ao and B₀ are input to an XOR gate 410. XOR gate 410 generates an output signal on line 412. A carry in C_iπ, if provided for bit position 0, is input at input terminal 416. A second XOR gate 414 receives input signals from line 412 and terminal 416. The second XOR gate 416 generates Z_0a and Z_0b on output terminals 406 and 408. If no carry in C_in is provided, the second XOR gate 414 may be omitted. Z_0a and Z_ob may be generated directly from the first XOR gate 410.

FIG. 8 illustrates a circuit diagram of a memory line driver 250 of the address decoder 210 (FIG. 5) constructed in accordance with an embodiment of the present invention. The memory line driver 250 is populated by a number of AND gates 252-

256. Each AND gate (such as gate 252) is provided in association with one of the memory lines in the memory 220 (FIG. 4). Each AND gate 252 receives one of the address lines Z_ιa-Z_ld (i=l to n) from the redundant form decoder 230 as an input. Each AND gate 252 also receives one of the pair of address lines Z_0a-Z_ob for bit position i=0. In response to an address input signal to the memory system in redundant form, one of the memory lines should be enabled.

As noted with respect to the redundant form decoder 300 of FIG. 6, one of address lines Z,_a and Z_1C carry the correct signal value of non-redundant S,. The correct signal value could be determined from an internal carry chain typical to conventional adders (sometimes called the "completion add"). However, improved performance maybe obtained by omitting the internal carry chain.

In this embodiment each AND gate 252, 254, etc. maps to a memory line having a unique address R. The address may be used as an additional piece of information to identify which of Z_]a or Z_1C carries the correct value of non-redundant S,. Specifically, the non-redundant value of the address R at bit position i-l (R,.ι) is taken to be the value of the non-redundant sum S,., (R^S,.,). This assumption is justified because, if it were not true, then some other input signal to the AND gate would be zero during the address decoding process. The AND gate might not drive its associated memory line in such a circumstance. In other words, the AND gate will function when the completion add would have generated a S,_, that agrees with the address bit R, ,. When the input signals values A„ B„ A,., and B,_, are known and the non-redundant sum S,., is "known" to be R,.,, the non-redundant value S, may be calculated.

Table 1 below illustrates the values of S, and the values Z_ιa-Z_ld output from the redundant form decoding circuit 300 for all possible permutations of A„ B„ A,.,, B,., and S,.,. The table is sorted first by S,.,, then by S,. As the table illustrates, when S,_, is 0, Z, =S,. When S,., is 1, Z, =S,. PAGE INTENTIONALLY LEFT BLANK

B, A B,., S_M s, z,_a z,_b Z,c z,_d A, B, A,., B|-ι S,.., s, Z,a z_lb Z,c z,_d _

0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1

0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0

0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0

(5 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 1

1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 1

1 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1

1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 0

1 1 0 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0

1® 0 0 1 0 0 1 0 0 0 1 1 1 0 1 0

0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0

0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 1

0 1 0 0 0 1 0 0 0 1 1 0 1 0 0 1

1 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0

IΈ 1 0 1 0 0 1 0 1 0 0 1 1 0 0 1

1 1 1 0 0 0 1 0 1 0 1 0 1 0 0 1

1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0

Table 1

Of course, an AND gate is responsive only when it receives input signals that 0 are 1. However, sometimes the correct value of S, is 0 (when R=0). If S, were input to the AND gate, it would not function even though the selected value of S, is correct.

Thus, when the correct value of S, is selected but S =0, S, is inverted and input to the

AND gate. Because Z_lb=Z_ιa# and Z_ld=Z_lc#, they are used as input signals when S =0.

Thus, for each bit position i (i≠O), an AND gate is coupled to one of the four 5 address lines Z_ιa-Z_ld based upon the non-redundant values of the address bits R„ R,.,. Table 2 demonstrates how the connections are made:

ue of Address for Selected

AND Gate Address Line

R, R

30

Table 2

35 In FIG. 8 the AND gates 252-255 illustrate couplings made in accordance with this principle for i=l . As described with reference to FIG. 5, bit position i=0 is used to address a memory line. For each AND gate related to an address R terminating in 0 (Ro=0), the

AND gate receives an input from line Z_0b in this embodiment. For each AND gate related to an address terminating in 1 (Ro=T), the AND gate receives an input signals from line Z_0a in this embodiment.

When the least significant bit of the redundant form input data signals is used in the address of the memory lines 222, in this embodiment of the present invention may be used with no completion add. However, a completion add may be employed when the least significant bit of the redundant form data does not address the memory. For example, if redundant form input data extends from O₀-O_n but bits O₃-O_n address the memory lines, a completion add may be employed for redundant form bits 0₀-O₃.

FIG. 9 illustrates a memory system 500 constructed in accordance with a second embodiment of the present invention. In the second embodiment, aligned data signals may be read out of a memory based on redundant form address data signals. The memory system 500, like the system 200 of FIG. 5, includes an address decoder 510 and a memory 520. The address decoder 510 comprises a two-stage decoder including a redundant form decoder 530 and a memory line driver 540. The memory system 500 also includes a selection switch 550.

In the second embodiment, of the redundant form address bits O₀-O_s+n subject to arithmetic preprocessing, only a portion of the bits O_s-O_s+n is employed to address individual memory lines. The remaining bits, O₀-O_s., represent data signals within a memory line.

The memory system 500 of FIG. 9 reads out "aligned data." Aligned data comprises data signals that are contained within a predefined block in a memory line. Each memory line 522 is divided into a plurality of blocks. Two blocks are shown in

FIG. 9: High order blocks and low order blocks. Within a memory line, the blocks are identified by address data S_s., at position s-1. In this embodiment, requested data may not cross a boundary between blocks.

The redundant form decoder 530 is populated by multiple stages of the redundant form decoder circuit 300 of FIG. 6. The redundant form decoder circuit 300 applied for use in decoding all redundant sum bits O, for i = s to s+n.

FIG. 10 illustrates a memory line driver 540 of the address decoder 510 constructed in accordance with an embodiment of the present invention. The memory line driver is populated by a number of AND gates each associated with a block of each memory line. Thus, in the memory line driver 540 of FIG. 9 there are twice as many AND gates as there are memory lines. Where each memory line is assigned an address R composed of bits R_s to R_s+n, the blocks within each memory line are addressed by lower order bits R_s., to R^. In the two-block example of FIG. 9, bit R^., addresses the blocks within a memory line.

For each bit position i (i from s to s+n), each AND gate receives as an input signal of the address lines Z,_a, Z,_b, Z_]C or Z_ld generated by the redundant form decoder stage 540. Identification of the one address line Z_ιa-Z_ld to which an AND is coupled is determined by the AND gates' address bit R, and R,_, according to the principle outlined in Table 2 above.

In the memory line driver 540 of FIG. 10, two AND gates 541, 542 are responsive to a predetermined redundant form address. A first AND gate 541 selects a low order block. The selected low order block is addressed correctly when S_s.,=0. A second AND gate 542 selects a high order block. The selected high order block is addressed correctly when S_s.,=l . The selection switch 550 (FIG. 9) determines which selected block of data is routed out of the memory system 500.

The requested block of data is selected by selection switch 550 based on non- redundant S_s_,. Initially, S_s., is not known. To obtain S_s. it may be desirable to perform a traditional add of the redundant form address data O for bit positions 0 through s-1. When a non-redundant value of S_s_, is obtained, it is applied to the selection switch 550 to select the correct block of data. The block selected by the _ selection switch 550 is the one whose decoding AND gate is known to have received a correct input signal.

Although a completion carry addition may be performed in the embodiment of FIG. 8, this embodiment still achieves improved performance over the systems of the prior art. The carry chain propagates only through bits 0 through s-1, not through the entire length of the address (0 though s+n). Thus, the carry chain is reduced.

The time employed to perform the short address add may be justified also due to operational characteristics of a memory memory. Traditionally, memory memories are somewhat slow to output data from a memory line once the memory line is enabled. There is an inherent latency in the time that data is available to a selection switch once a memory line is enabled. Thus, performing a traditional add on the short run of address data, from bits 0 to s-1, does not impair significantly the speed at which data may be retrieved from the memory.

Alternatively, control signals input to the selection switch 550 may be generated using the logic of FIG. 8. The selection switch itself may be controlled by redundant form logic.

The discussion of the redundant form address data provided above has assumed that one or a series of redundant form arithmetic operations are performed on address data before resultant address data is input to an address decoder. In a special case, arithmetic processing may be omitted from a memory operation. When a memory operation causes a single addition of two non-redundant addresses to be performed, the memory operation may be omitted. Instead, the two non-redundant addresses may be input directly to the address decoding.

As shown in FIG. 11, a redundant form addition of two non-redundant numbers, generates a redundant form sum O, where:

Thus, this embodiment of the present invention provides for zero delay decoding of address data in a single addition implementation.

This embodiment of the present invention provides an address decoder that decodes address data in redundant form. The address decoder permits arithmetic operations to be made on address data at very high speed and, therefore, reduces latency of memory operations that rely on those arithmetic operations. Because the address decoder omits the internal carry chain common to traditional adders, it provides dramatic performance benefits over conventional memory operations involving arithmetic operations.

Several embodiments of the present invention are specifically illustrated and described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention.

Claims

WE CLAIM:

1. A memory system, comprising: an address decoder receiving on an input redundant form address data signals and including memory enable lines as output ports, and a memory populated by a plurality of memory line entries, at least one entry coupled to at least one of the memory enable lines.

2. The memory system of claim 1 , wherein the address decoder comprises: a redundant form decoder stage, adapted to receive the redundant form address data signals and to generate decoded address signals on address lines, and a memory line driver stage, coupled to the address lines and including the memory enable lines as output ports.

3. The memory system of claim 2, wherein: at least one memory enable line is associated with a predetermined address of a predetermined width, the address decoder comprising a multi-stage decoder included a stage associated with at least one bit position in the address.

4. The memory system of claim 3, wherein at least one decoder circuit stage is adapted to generate decoded address signals based upon the redundant form address data at the associated bit position and the next lower bit position.

5. The memory system of claim 3, wherein at least one decoder circuit stage is adapted generate a pair of decoded address signals for the associated bit position.

6. The memory system of claim 5, wherein the memory line driver stage includes an AND gate associated with one of the addresses, the AND gate adapted to receive one of the pair of decoded address signals as an input signal, the one decoded address signal determined by the value of the one address at the bit position of the decoder - circuit stage and the next lower bit position

7. The memory system of claim 2, wherein two memory enable lines are provided for each memory line entry, one for a first half of the memory line entry, the other for a second half of the memory line entry.

8. The memory system of claim 7, further comprising a selection switch coupled to each half of the memory line entries, said selection switch capable of being controlled by the address decoder.

9. The memory system of claim 2, wherein the memory line driver stage comprises a plurality of AND gates, each AND gate associated with a unique address in the memory, wherein an AND gate receives predetermined ones of the address lines in accordance with its unique address.

10. A redundant form address decoder, comprising: a redundant form decoder, adapted to receive address data in redundant form and generating decoded address signals on address lines, and a memory line driver, coupled to the address lines and adapted to generate an output signal on memory enable lines.

11. The redundant form address decoder of claim 10, wherein a memory enable line is associated with an address of a predetermined width, and the redundant form decoder comprises redundant form decoding circuits, one provided in association with a bit position of the address.

12. The redundant form address decoder of claim 11, wherein at least one redundant form decoding circuit adapted to generate two differential pairs of address lines in response to redundant form address data input at its associated bit position and _ the adjacent lower bit position.

13. The redundant form address decoder of claim 11 , wherein the redundant form decoding circuit associated with the least significant bit of the address comprises a one bit adder.

14. The redundant form address decoder of claim 10, wherein the memory line driver comprises a plurality of AND gates, an AND gate associated with an address of a predetermined width and selectively coupled to the address lines in accordance with its address.

15. The redundant form address decoder of claim 14, wherein, for at least one bit position of the address, the address lines comprise two differential pairs of address lines.

16. A memory system, comprising: a memory having a plurality of memory line entries, a memory line entry organized into a high order half and a low order half, a high order half and low order half coupled to a respective memory line drive line, an address decoder, receiving address data signals in redundant form, the address decoder having as outputs the memory line drive lines, and a selection switch coupled to the halves of the memory line entry.

17. The memory system of claim 16, wherein the selection switch receives a control signal as an input signal, the control signal being output from the address decoder.

18. The memory system of claim 17, wherein: the control signal comprises a multi-bit control signal identifying one of a plurality of blocks of data within a half of a memory line, and responsive to the multi-bit control signal, the selection switch outputs a selected block from the memory system.

19. The memory system of claim 16, where the address decoder comprises: a multi-bit decoder that decodes the redundant form address data into decoded address lines, and a memory line driver stage coupled to the decoded address lines and including as outputs the memory line drive lines.

20. The memory system of claim 19, wherein at least one stage of the multi-bit decoder is associated with a predetermined bit position of the redundant form address data and the stage receives as input signals the redundant form address data at the bit position and an adjacent lower bit position.

21. A method of controlling a memory system, comprising: receiving on an input redundant form address data signals, generating a memory enable signal based on the redundant form address data signals, applying the memory enable signal to a memory, and reading data from the memory based upon the memory enable signal.

22. The method of claim 21 , wherein the receiving step includes generating decoded address signals based on the redundant form address signals, and the generating step includes generating the memory enable signal from the decoded address signals.

23. The method of claim 22, wherein the redundant form address signals are organized as a plurality of multi-bit bit positions and at least one decoded address signal is generated based upon the value of the redundant form address data at an associated bit position and a next lower bit position.

24. The method of claim 23, wherein the decoded address signals for at least one bit position are generated as a differential pair of decoded address signals.

25. The method of claim 24 , wherein the memory includes memory entries, each associated with a memory enable signal and with a memory address, and

the generating step includes enabling a memory enable signal based upon a predetermined combination of decoded address signals.