WO1999055038A1 - Reseau de communications optique - Google Patents

Reseau de communications optique Download PDF

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Publication number
WO1999055038A1
WO1999055038A1 PCT/GB1999/001159 GB9901159W WO9955038A1 WO 1999055038 A1 WO1999055038 A1 WO 1999055038A1 GB 9901159 W GB9901159 W GB 9901159W WO 9955038 A1 WO9955038 A1 WO 9955038A1
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WIPO (PCT)
Prior art keywords
optical
packet
bit
gate
regenerator
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PCT/GB1999/001159
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English (en)
Inventor
David Cotter
Andrew David Ellis
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British Telecommunications Public Limited Company
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Priority claimed from GBGB9808491.6A external-priority patent/GB9808491D0/en
Priority claimed from GBGB9812162.7A external-priority patent/GB9812162D0/en
Application filed by British Telecommunications Public Limited Company filed Critical British Telecommunications Public Limited Company
Priority to AU36134/99A priority Critical patent/AU3613499A/en
Priority to CA002329717A priority patent/CA2329717A1/fr
Priority to EP99918086A priority patent/EP1074112A1/fr
Publication of WO1999055038A1 publication Critical patent/WO1999055038A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/29—Repeaters
    • H04B10/291—Repeaters in which processing or amplification is carried out without conversion of the main signal from optical form
    • H04B10/299—Signal waveform processing, e.g. reshaping or retiming
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0075—Arrangements for synchronising receiver with transmitter with photonic or optical means

Definitions

  • the present invention relates to an optical communications network, and in particular to the regeneration of optical packets carried on such a network.
  • optical fibre has a huge potential information-carrying capacity.
  • a single fibre could carry more than 2 Tbit/s.
  • the information is carried over fibre in the form of an optical signal at a single wavelength.
  • the data transmission bandwidth of the fibre is therefore limited by the electrical bandwidth of the transmitter and receiver, and this means that only a tiny fraction (a maximum of about 1 %) of the potential bandwidth-carrying capacity of the fibre is being usefully exploited.
  • WDM wavelength-division multiplexing
  • RZ return-to-zero
  • WDM networks can be created in a wide variety of architectures with great flexibility (the main restriction being merely that any pair of photonic transmission paths cannot use the same wavelength on a shared fibre link).
  • An advantage of WDM networks is that they can, in principle, support 'signal transparency', i.e. data signals can be carried using any modulation format.
  • WDM photonic networks are based on 'analogue' transmission. As a result it is not possible for digital signal regeneration techinques in the optical domain, to be used.
  • the signals are carried in 'digital' format in the form of RZ optical pulses, allowing the use of digital signal regeneration techniques in the optical domain such as 3R (Re-amplify, Re-time and Re-shape) regeneration [Lucek J K and Smith K.Optics Letters, 18, 1226-28 (1993)] or soliton-control techniques [ Ellis A D, Widdowson T, Electronics Letters, 31 , 1 171-72 (1995)]. These techniques can maintain the integrity of the signals as they pass through a very large number of nodes.
  • a method of operating a node in an optical communications network including a) receiving at the node an optical packet; and b) generating from the said optical packet received at the said node a regenerated optical packet having a phase determined by a local bit-level clock source and independent of the bit-level phase of the said packet received at the node.
  • the term 'packet' is used to mean a fixed- length or variable-length string of bits which may be routed through a network in a variety of different ways, including self-routing, store-and-forward packet routing, scheduled switched routing and circuit switching
  • W of the gate window is not less than T/ k and not more than T, where T is the bit period and k is the number of optical gates.
  • a single gate means may be used in conjuction with means to shift the phase of the incoming packet to match that of the local free-running optical clock.
  • the optical gate means may comprise a number of distinct physical devices, such as those described in further detail below.
  • the plurality of optical gate means might comprise a single device arranged to gate a plurality of distinct optical signals distinguished, e.g. by their polarisation or wavelength, and references in the description and claims to a number of gate means are to be construed accordingly.
  • the method includes making a measurement of a parameter of an optical signal output from the gate means, and selecting the output of one of the plurality of gates to provide the regenerated optical packet depending on the results of the said measurement.
  • the parameter may be a measure of the total energy of the output signal, and the selection may be made by comparing the energies of the signals from different optical gate means.
  • Other parameters may also be used to make the selection. For example, the bit error level may be measured, and the output selected which has the minimum bit error level.
  • a regenerator for optical packets comprising: an input for receiving an optical packet; a local bit-level optical clock source comprising a free-running local oscillator; means for generating from the optical packet and from a clock signal from the local optical clock source a regenerated optical packet independent in phase from the optical packet received at the input.
  • Figure 1 shows the basic concept for 3R regeneration of a digital data stream consisting of a RZ pulse train encoded by on-off modulation
  • Figure 2 shows the method of 3R regeneration used for OTDM systems in which the bit stream is continuous
  • Figure 3 shows a method of partial regeneration of optical packets
  • Figure 6 a sequence of timing diagrams that illustrate the operation of the dual- gate regenerator
  • Figure 1 0 shows a plot of the maximum bit-error probability B according to ( 1 2), plotted versus the bit-arrival jitter ⁇ , and taking WI T - 0.75 .
  • Figure 14 Diagram of a bit-asynchronous quad-gate packet regenerator
  • Figure 1 8 Plot of the maximum value of the bit-error probability B for any phase angle ⁇ in the range 0 ⁇ ⁇ ⁇ 2 ⁇ , calculated according to (21 ), plotted versus
  • Figure 1 9 show values for the probability that a packet suffers 'slippage' (i.e. a time displacement greater than a specified acceptable limit L T), according to (22), plotted versus N, the number of regenerators passed, for various values of LT.
  • Figure 20 shows a version of the two-gate regenerator which uses only one optical gating device to gate simultaneously two independent clock signals which are distinguishable by their different states of polarisation.
  • Figure 23 Example layout of a portion of a network comprising switching nodes containing routing switches (RS) and bit-asynchronous regenerators (AR), and links between the switching nodes containing bit-synchronous regenerators (SR).
  • Figure 24 Outline diagram of an alternative arrangement of the bit-asynchronous packet regenerator using a single gate to modulate the output of the local source.
  • Figure 25 A further example embodiment of the bit-asynchronous packet regenerator using a single gate to modulate the output of the local source
  • Figure 26 shows a schematic of an optical packet network.
  • an ultrafast optical packet network information is transported across a network in the form of fixed-length bursts (i.e. cells or fixed-length packets) of RZ optical pulses that are encoded with payload data and control information (such as the address of the packet destination).
  • the network may constitute, for example, the core network of a national data/telephony network, or a local area network connecting a number of computing systems, or part of the fabric of a communications switch, or may provide the connection between processors in a multi processor computer. Examples of suitable topologies for such a network are described in the present applicant's co-pending European patent application 97307224.2, the contents of which are incorporated herein by reference.
  • Every transmission path in the network carries a continuous sequence of time slots, synchronised to a packet-level global clock, and each time slot accommodates at most one packet and an appropriate time guard band.
  • This time guard band allows the transmission path to be switched for packet-by-packet routing and also allows continuous and endless synchronisation of the packet streams and network nodes to the packet-level global clock.
  • the packet time slots are synchronised throughout the network.
  • a crucial aspect of our approach is that synchronism between packets at the (picosecond) bit-level is not required. Therefore the portion of the time slot that accommodates the packet can be conveniently defined to be several bit periods longer than the packet duration. This permits a certain amount of slop in the positioning of the packet within the time slot - in other words, the positioning of the packet within the time slot is not made with bit-level precision, and generally successive packets are not bit- synchronous.
  • bit- asynchronous digital optical packet regenerator For such an asynchronous network to have the same near-infinite scalability as bit-synchronous OTDM networks, it is necessary to use a bit- asynchronous digital optical packet regenerator, as is further described below.
  • Figure 1 shows a prior art approach to 3R regeneration of a digital data stream consisting of a RZ pulse train encoded by on-off modulation ('mark' represents a bit value 1 , 'space' represents 0) .
  • the incoming data bits from a distant source are used to modulate a continuous train of high-quality RZ pulses produced by a local source, thus regenerating the original data.
  • the presence of a 'mark' in the incoming data stream causes the gate to open for a time of the order of the bit period, allowing a single pulse from the local source to pass through. In this way the regenerated bits have the same pulse shape, spectral quality, amplitude and timing stability as the local source.
  • FIG. 2 shows a prior art method used for OTDM systems in which the bit stream is continuous.
  • a clock recovery circuit (which may be electronic or optical) derives a clock signal in synchronism with the incoming data bits, and this clock is used to synchronise the local pulse source.
  • the method shown in Figure 2 is less suitable for systems in which the incoming data is not continuous, but is in the form of bursts or packets which are mutually bit-asynchronous.
  • the clock recovery must be performed on a packet-by-packet basis, and therefore the lock-up time of the clock-recovery circuit must be a fraction of the packet duration in order not to waste bandwidth.
  • the need for a fast lock-up time tends to conflict with the requirement for a consistent high-quality pulse train throughout the duration of the packet.
  • each incoming packet contains one or more synchronisation or 'marker' pulses which may be distinguishable by their wavelength, polarisation, amplitude, position, pulse spacing, etc.
  • Figure 3 shows the approach in which a synchronisation pulse is extracted from an incoming packet and then passively replicated to produce a regular burst or pulse pattern. This replicated pulse train can then be used in the processes of demultiplexing, packet header-address recognition.
  • the local pulse source is forced into frequency and phase synchronism with the incoming data stream.
  • the local pulse source is continuously free-running, with the same nominal repetition frequency as the bit rate of the incoming data, but not necessarily in frequency and phase synchronism with the incoming packet. Instead the regenerated packet simply takes up the bit rate and phase of the free- running local source.
  • This new approach allows the data packets to be bit- asynchronous, yet avoids the difficulty of recovering a high-quality clock signal on a packet-by-packet basis.
  • Bit-asynchronous optical packet regeneration Figure 4 is a simplified outline diagram showing a generator of optical packets and a bit-asynchronous packet regenerator.
  • the packet generator creates optical data packets each with a fixed bit rate of M s f s .
  • this packet generator could consist of a source of optical RZ pulses at a repetition frequency f s Hz, whose output is modulated and multiplexed in a fashion similar to that used for OTDM (i.e.
  • the output from the pulse source is split into .parallel paths which are individually encoded with data by on-off modulation at a rate f s bit/s and then recombined by bit-interleaving to form a packet of data bits with a composite rate of M s f s bit/s) .
  • the source of pulses at repetition frequency f s could, as shown in Figure 4, consist of an electronic microwave oscillator at f s which drives an electrically-synchronised laser (such as a gain-switched laser or an actively-mode-locked laser) .
  • a continuously free-running optical pulse source such as a passively-mode-locked laser or a mode-locked ring laser, whose nominal repetition frequency is set (for example, by tuning the laser cavity length).
  • an independent continuously free-running source of RZ optical pulses at a repetition frequency M R f R Hz.
  • This pulse source could, as shown in Figure 4, consist of an independent electronic microwave oscillator at a frequency f R which drives an electrically-synchronised laser (such as a gain-switched laser or an actively-mode-locked laser), followed by a passive splitter and bit-interleaver to produce the required composite frequency M R f R Hz.
  • the source could be a continuously free-running optical source of pulses at the rate f R followed by the x ⁇ splitter and interleaver, or indeed the free-running source could operate at the full repetition frequency M R f R Hz directly without the need for xM R multiplication.
  • bit rate of the incoming data packet and the repetition frequency of the pulse train at the A input to the gate can be considered to be exactly equal, and that the phase difference ⁇ between them can be considered to be constant over the duration of the packet. Nevertheless, for any given packet, this phase difference is an arbitrary value in the range 0 ⁇ ⁇ ⁇ 2 ⁇ .
  • successive packets arriving at a regenerator may originate from different sources and accordingly their phases ⁇ may be entirely uncorrelated. Therefore the bit- asynchronous packet regenerator must be designed to operate correctly on each packet independently, regardless of the phase difference ⁇ .
  • Dual-gate bit-asynchronous optical packet regenerator Principle of operation Figure 5 shows a dual-gate bit-asynchronous packet regenerator.
  • the data bits in the incoming packet are used to control the opening of two gates, G 1 and G2.
  • a data bit with value 1 ('mark') causes each of the two gates to open for a fixed time duration (the gate window), otherwise the gates remain closed. It is preferable, though not essential, that the widths of the time window for gates G 1 and G2 are equal.
  • the output from the local clock (a continuous free-running source of optical RZ pulses at a repetition frequency nominally equal to the packet bit rate X I T) is applied to the inputs of the two gates, one of these inputs being delayed relative to the other by an amount TI 2.
  • the operation of the regenerator is very similar in this case, and the predicted performance described later is the same.
  • the configuration will be assumed to be that in which the packet data bits are connected directly to the control ports of the gates, and the input ports have certain differential delays (as illustrated in Figure 5 for a dual- gate regenerator) .
  • the optical gates may be implemented in different ways.
  • the gate could be a nonlinear optical device such as a fibre loop mirror (as described, for example, by Whitaker et al in Optics Letters, vol. 1 6, page 1 840 ( 1 991 )), in which case the gate width is defined by selecting suitable fibre lengths, dispersion and birefringence.
  • a suitable ultrafast gating device based on the nonlinearity in semiconductor optical amplifiers could be used (as described, for example, by Kang et al in the International Journal of High Speed Electronics and Systems, vol. 7, page 1 25 (1 996)).
  • the gate width may be determined by the positioning of the amplifier in a Sagnac interferometer loop arrangement, or the relative offset of two amplifiers in a Mach-Zehnder interferometer device.
  • Another suitable ultrafast semiconductor-based device is the ultrafast nonlinear interferometer switch described by Hall and Rauschenbach (paper PD5, Proceedings of Conference on Optical Fiber Communication OFC'98, published by the Optical Society of America, February 1 998), which has been shown to operate at a speed of 100 Gbit/s.
  • FIG. 20 shows a version of the two-gate regenerator which uses only one optical gating device to gate simultaneously two independent clock signals which are distinguishable by their different states of polarisation.
  • Figure 6 shows a sequence of timing diagrams that illustrate the operation of the dual-gate regenerator.
  • the packet data bits (an example sequence 1 1 101 is shown) arrive at the control ports of the gates G1 and G2, and each 'mark' causes the gates to open for a time 3T/ 4.
  • Diagram (i) illustrates the case 0 ⁇ ⁇ ⁇ W - 1 /2 , in which the outputs from both gates G 1 and G2 are clock pulses that have been correctly modulated by the incoming data bits.
  • Diagram (ii) illustrates the case W - 1/ 2 ⁇ ⁇ ⁇ 1 /2 , in which the output from gate G 1 (but not G2) are clock pulses that have been correctly modulated by the incoming data bits.
  • Diagram (iii) illustrates the case 1 /2 ⁇ ⁇ ⁇ W , in which again the outputs from both gates G 1 and G2 are correctly modulated.
  • Diagram (iv) illustrates the last possibility, W ⁇ ⁇ ⁇ X , in which the output from gates G2 (but not G 1 ) is correctly modulated.
  • the components shown to the right-hand side of the two gates are used to attempt to select in each time slot whichever gate output gives a regenerated packet with the minimum of bit errors.
  • One technique, shown in Figure 5 is to make the selection in each time slot on the basis of a comparison of the total optical energy emerging from each gate, integrated over the duration of the packet.
  • phase angle ⁇ is such that the output from a gate consists of correctly modulated clock pulses then the total optical energy measured at the output of the gate, integrated over the duration of the packet, will be maximum (in effect, it is a measure of the number of 'marks' appearing in the regenerated data packet) .
  • ⁇ is such that the clock pulses arrive at the gate at a time outside the gate window, then the energy transmitted by the gate will be zero or small.
  • the circuit shown in Figure 5 therefore makes these energy measurements and the result of the comparison is used to set the optical switch S, (for example, an optoelectronic device such as a lithium niobate switch) which performs the physical selection.
  • An alternative method of selecting the most appropriate gate output in each time slot may be to perform a bit-error measurement on the whole or part of the packet that emerges from each gate. For example, a test pattern could be incorporated as part of each packet, and this pattern would be received and any bit errors detected and counted in each time slot at the output of each gate. In a given time slot the output having zero or the least number of bit errors would be selected.
  • the optical delays (labelled L and L + ATI 2 in Figure 5) between the outputs of the gates and the selection switch S are used to allow sufficient time for the circuitry and switch S to operate before the packets arrive at the switch. Typically the delay L will be slightly less than one time slot in duration.
  • the optical delay between the output of gate G 1 and the switch S may be made slightly longer (by an amount T 12 ) than the delay between the output of gate G2 and the switch.
  • the purpose of doing this is to compensate for the delay of 772 at the input of gate G2, thus equalising the delay of both optical paths from the clock source to the output of the selector switch S.
  • One benefit of doing this is that all the regenerated packets are then in precise bit synchronism with each other and with the local clock, and as mentioned earlier, the local clock may therefore be used as a continuous and regular source of pulses for use in subsequent digital optical processing stages.
  • a further important benefit of equalising the delay in this way is to reduce the problem of 'packet slippage' in a large network, as described in section 3.4.3.
  • the first cause is jitter in the arrival time of the incoming packet data bits. It is well known that in high-speed optical transmission systems, jitter in the arrival time of pulses arises from effects such as amplified spontaneous emission noise, the soliton self- frequency shift arising from the Raman effect, soliton short-range interactions, and the complex interplay of these various processes.
  • the second main cause of bit errors is errors in the process used to select the output from one of the gates in each time slot. For example, when the selection is made on the basis of a comparison of the output energy from the gates, noise in the energy measurement and comparator circuits can result in incorrect selection.
  • the bit-error probability arising from timing jitter is analysed in detail under the assumption that the gate selector is perfectly noise-free and has infinitesimal resolution.
  • the gate window will open so as to allow the (z ' - l)thclock pulse to be transmitted, with the possibility of producing an error.
  • the probability that the actual arrival time falls within the heavily shaded region is given by
  • the clock pulses are arranged to arrive later in time by an amount TI 2.
  • bit-error probability for the output from gate / conditional on the phase angle ⁇ :
  • B( ⁇ ) ⁇ X - p( ⁇ )[ ⁇ X - q( ⁇ ) l 2][ X - r( ⁇ ) l 2] ⁇ l 2
  • the expected value of the optical energy measured at the output of the ⁇ h ggaattee,, ⁇ (EE /) ,, iinntteeggrraatteedd oovveerr tthhee duration of the packet, is found by summing the probabilities in the table above:
  • N(e) N ⁇ e ⁇ ))
  • e denotes a random variable that takes the value 1 when a bit error occurs and the value 0 otherwise, and denotes B( ⁇ )t e bit-error probability, conditional on the phase angle ⁇ , for a single regenerator.
  • Figure 1 1 is a plot of the expected bit-error probability for a given packet, per regenerator passed, according to ( 1 5). The curves are plotted against the rms jitter ⁇ , for various values of the gate window width W. For example, with
  • the gate selection technique will be analysed based on comparison of packet energies, as described above, in the case that the energy measurement and comparator circuits are subject to noise and other imperfections.
  • the detectors D 1 and D2 followed by electronic integrators each provide a voltage, V ] and ⁇ respectively, in each time slot which is proportional to the energy of the regenerated packet emerging from gate G 1 and G2, respectively, in that time slot.
  • the comparator C produces a binary output signal according to whether or not jexceeds V 2 , and this signal is used to control the operation of the selector switch S.
  • the comparator output is 0 causing the switch S to select the output from gate G 1 ; and ideally if the energy of the regenerated packet emerging from gate G2 is greater or equal to the energy of the regenerated packet emerging from gate G 1 , then the comparator output is 1 causing the switch S to select the other output.
  • the energy measurement and comparator output are non-ideal. Here we assume that systematic errors are negligible, and model the random errors by assuming that, for any given phase angle ⁇ , the voltage V - V 2 is a normally-distributed random
  • V l or V 2 variable with variance ⁇ c .
  • the normalisation is such that a voltage V l or V 2 equal to 1 represents the energy of a regenerated packet consisting of n 'mark' pulses, where n is the number of bits in the original packet, and the expected number of 'marks' in the original packet is 0.5. Therefore the probability R(Gl) that gate G 1 is selected (i.e. that the comparator output signal is 0) is given by
  • bit-error probability B P(GX)B( ⁇ ) + P(G2)B( ⁇ 2 ) , ( 18) where ⁇ x , ⁇ 2 n ⁇ B( ⁇ ) are given by (6), ( 1 1 ) and (1 2), respectively.
  • Figure 1 3 shows the severe degradation in bit-error probability that occurs when the gate selection is non-ideal, even if the standard deviation ⁇ c / T is very small.
  • Figure 1 4 shows a quad-gate bit-asynchronous packet regenerator.
  • the data bits in the incoming packet are used to control the opening of four gates, G 1 , G2, G3 and G4.
  • a data bit with value 1 ('mark') causes each of the four gates to open for a fixed time duration (the gate window), otherwise the gates remain closed. It is preferable, though not essential, that the widths of the time window for the four gates are equal.
  • the output from the local clock (a continuous free-running source of optical RZ pulses at a repetition frequency nominally equal to the packet bit rate X I T) is applied to the inputs of the four gates, with relative delays in steps of T 14 as shown in Figure 14.
  • the window width W must lie within a particular range of values, which for the quad-gate regenerator is 774 ⁇ W ⁇ T .
  • the incoming data pulses and local clock pulses are represented here by delta impulses. (As described below, when finite pulse widths are taken into account the acceptable range of window widths is somewhat narrower than T 1 ⁇ W ⁇ T) .
  • the dual-gate regenerator we should note, with reference to Figure 14, that there is an alternative and equally valid configuration in which the relative delays in steps of Tl 4 are removed from the input ports A of the gates, and placed instead at the control ports C.
  • the operation of the regenerator is very similar in this case, and the predicted performance described later is the same.
  • the configuration will be assumed to be that in which the packet data bits are connected directly to the control ports of the gates, and the differential delays are in the connections to the input ports.
  • the technique for gate selection shown in Figure 1 4 is based on a comparison of the total optical energy emerging from each gate, integrated over the duration of the packet.
  • the optical switch S must select one of the outputs from the four gates.
  • the 1 x4 switch could consist an arrangement of three 1 x2 switches, S1 , S2 and S3.
  • the controller C measures the outputs from detectors D 1 , D2, D3 and D4 in each time slot, and sets the selector switches accordingly using the strategy described by (20) below.
  • Other practical details are similar to those described above.
  • the optical delays (labelled . , L + ATI 4 , L + ATI 2 and Z + 3 ⁇ 774 in Figure 14) between the outputs of the gates and the selection switch S are used to allow sufficient time for the circuitry and switch S to operate before the packets arrive at the switch.
  • the delay L will be slightly less than one time slot in duration.
  • the optical delays between the outputs of the various gates and the switch S may be made to differ in steps of 774 , as shown in Figure 14.
  • the expected value of the optical energy measured at the output of the ⁇ h gate, ⁇ E ( / , is given by ( 1 3).
  • the quad- gate regenerator the clock pulses that are modulated by the selected gate are positioned further in time from the edges of the gate window, thus reducing the probability that jitter in the arriving data may cause a clock pulse to fall outside the window resulting in a bit error in the regenerated packet.
  • the effect of non-ideal selection of the gate output is now analysed.
  • the detectors D1 to D4 followed by electronic integrators each provide a voltage, V ⁇ to V 4 respectively, in each time slot which is proportional to the energy of the regenerated packet emerging from gate G 1 to G4, respectively, in that time slot.
  • the comparator circuit C produces an output signal which is used to control the operation of the selector switch S.
  • Figure 1 8 shows a plot of the maximum value of the bit-error probability B for any phase angle ⁇ in the range 0 ⁇ ⁇ ⁇ 2 ⁇ , calculated according to (21 ), and plotted versus WI T .
  • Other calculations based on (21 ) show that with ⁇ c I T less than 4%, and ⁇ l T ⁇ 0.032 , the maximum bit-error probability is less than 10 " , regardless of the phase angle ⁇ .
  • bit-error probability will be less than 10
  • the quad-gate regenerator is therefore a preferred embodiment of the invention, and preferably WI T is in the range 0.7-0.85.
  • Figure 1 9 shows values for the probability that a packet suffers 'slippage' (ie. a time displacement greater than the specified limit LT), according to (22).
  • the packet slippage probability is plotted versus Q, the number of regenerators passed, for various values of LT.
  • n 1000 bits, say, these guard bands represent a modest overhead on the network throughput.
  • a network contains of a large number of quad-gate regenerators, as shown in Figure 1 9, in each of which the optical paths between the clock source and the output of the selector switch S differ in delay time from the average value by an amount ⁇ , where ⁇ is a normally-distributed random variable, ⁇ ⁇ N(0, ⁇ D ) .
  • the standard deviation ⁇ D is a measure of the errors in equalising the delays of the optical paths.
  • a tolerance of ⁇ 7 on path delay represents a length tolerance of ⁇ 2 mm in glass, or approximately ⁇ 1 mm on a semiconductor substrate. If the optical components in the regenerator are in the form of an integrated monolithic semiconductor device, or discrete semiconductor devices mounted on a motherboard with planar waveguide interconnections, or discrete semiconductor devices connected by short optical fibre waveguides, these tolerances can be readily achieved. If, however, the optical gates are based on a nonlinear optical fibre device such as a fibre loop mirror, as suggested earlier, the length of fibre used in each loop mirror may be as great as 1 km in order for the required optical intensity of the input data bits to be acceptably low.
  • E denotes the set .
  • Single Gate Regenerator the local clock pulse source is again continuously free-running, but requires only one gate to modulate the output of the clock pulse source so as to regenerate the packet.
  • phase detector measures the phase angle ⁇ between the free-running local pulse source and the incoming packet. This information is used to shift by an appropriate amount the phase of the control signal that is applied to the gate.
  • the effect of the phase shifter is that when a packet data bit of value 1 causes the gate window to open, the window is located as near as possible centrally over the clock pulse (as depicted in Figure 21 ) .
  • the phase detector and phase shifter operate once in each time slot.
  • bit-error probability as a function of the ratio of the gate widow width 11 to the bit period 7, for various values of the rms jitter ⁇ in the arrival time of the packet data bits, is as depicted in Figure 5 of Jinno ( 1 994).
  • the clock pulses are broadened to " 10 ps, for example by passing them through the optical bandpass filter F1 (as shown in Figure 22) or by dispersion in fibre or in a chirped grating.
  • the phase detector could be based on four-wave mixing in a semiconductor optical amplifier SOA FWM (as described for example by O Kanatani, S Kawanashi and M Sarawutari in Electronics Letters, vol.30, no.10, p.807, 1 994) .
  • SOA FWM semiconductor optical amplifier
  • the electronic processing stage (which could include a low noise, high linearity sample-and-hold gate triggered by the global packet-level clock) measures the photodetector output voltage immediately after the arrival of the packet in each time slot, the measured voltage being given approximately by A + Bcos ⁇ , where A and B and constants and ⁇ is the phase difference between the clock and the incoming packet bits.
  • this signal is used to control the wavelength ⁇ cw of the continuous-wave distributed- feedback laser DFB in the phase shifter section.
  • the output of the DFB laser is connected to the input of a date-driven optical switch denoted UNI 1 .
  • This device could be the ultrafast nonlinear interferometer switch described by Hall and Rauschenbach (paper PD5, Proceedings of Conference on Optical Fiber Communication OFC'98, published by the Optical Society of America, February 1 998), which has been shown to operate at a speed of 100 Gbit/s, although any data driven optical switch capable of producing approximately square switching windows with negligible variation in throughput delay would be suitable.
  • the control signal to UNI 1 is the input data packet.
  • the action of UNI 1 is therefore to shift the wavelength of the incoming packet from ⁇ jn to the controlled wavelength ⁇ .
  • This packet with shifted wavelength is then isolated using optical filter F3, and passed through a dispersive optical delay line which imparts a time delay which depends on wavelength.
  • This dispersive delay line could be a fibre grating device or, as shown in Figure 22, a length of optical fibre, such as a length of optical fibre of the type manufactured primarily for use in dispersion compensation.
  • the required minimum amount of phase shift of the control pulses is ⁇ 5 ps (i.e. ⁇ 0.57, where 7 is the bit period). Therefore, if for example the length of dispersion compensating fibre is 20m and the fibre dispersion is 100 ps/nm/km, the required shift in the wavelength ⁇ cw of the DFB laser is ⁇ 2.5 nm, and this must be accomplished within the duration of the guard band between packets (say " 5 ns).
  • control loop may contain means to select one of a number of lasers each having a different fixed wavelength.
  • the optical fibre used as a dispersive delay line is a long device subject to changes in path length due to environmental factors (temperature, strain, etc), it is convenient as in Figure 22 to pass the local clock pulses over the same fibre. This ensures that there is a negligibly small relative change in delay for the clock and control pulses.
  • the error signal could be used to select one of a discrete number of optical paths.
  • a further alternative phase shifter comprises means to select one from a number of optical delay lines each having a different fixed delay.
  • the delay lines could consist of a silicon wafer on which is fabricated a silica-on-silicon planar lightwave circuit.
  • This circuit may be integrated in hybrid fashion with an array of discrete or integrated semiconductor optical switching devices, such as semiconductor optical amplifiers or electroabsorption modulators.
  • the electronic processing stage selects the appropriate delay line by switching on or off the appropriate semiconductor optical switching devices.
  • the resultant optical data bits are then used as the control pulses in the optical gate.
  • the gate denoted UNI2 in Figure 22, which is controlled by the phase-shifted packet data bits, is used to modulate the locally generated clock pulses so as to produce a regenerated packet, synchronous with the local clock.
  • the device UNI2 could be the ultrafast nonlinear interferometer switch described by Hall and Rauschenbach.
  • the regenerator is receiving inputs from a multiple number of sources, if the embodiment shown in Figure 22 is employed, the same length of dispersion- compensating fibre should be used for all inputs to provide appropriate phase shifts, so that all the regenerated packets are bit-synchronous.
  • Figure 23 shows an example of how the bit-asynchronous regenerator may be used in an optical network.
  • Three sources of packets are depicted (sources A, B and C), each of which have independent, uncorrelated clocks.
  • source A, B or C are coloured white, black or shaded, respectively.
  • the link from the output of each source carries only packets from that source, and therefore those packets are bit- synchronous with the clock in the source. This means that if a regenerator is required in the link, it may be a bit-synchronous type, similar for example to that depicted in Figure 2 .
  • Each input to the routing node may pass through a bit-asynchronous packet regenerator AR, and each of these regenerators in a switching node share the same local optical clock pulse source.
  • Each output from the routing switch may carry packets that have originated from more than one source.
  • an output link from routing node 1 may contain packets that have originated from sources A and B (i.e. 'black' and 'white' packets), but the action of the bit-asynchronous packet regenerators AR in the switching node is such that all the packets carried on this output link are now in bit-synchronism with the local clock in routing node 1 , despite their different sources.
  • a regenerator in this output link, it may be a bit-synchronous type.
  • the inputs to routing node 2 are from routing node 1 and from source C, and these inputs are bit-asynchronous.
  • Each of these inputs pass through bit-asynchronous regenerators AR that share the same local optical clock pulse source, so that an output from the routing node 2 may contain packets that originate from various sources, including sources A, B and C, but all the packets on the output links are again in bit-synchronism with the local clock in routing node 2.
  • a node such as that referenced node B, may combine an add/drop function for local traffic as well as regenerating packets for onward transmission.
  • bit-asynchronous packet regenerators in the switching nodes, we have shown that it is possible to design a network in which each individual link carries packets which are bit-synchronous (i.e. which share the same bit-level clock) and which share a standard power level. This allows simpler designs of regenerators in the links, and also removes the need for packet-by-packet power level equalisation. However, by regenerating the packets at each node in bit- asynchronous fashion, this entirely eliminates the need to maintain bit-level synchronism between the different links and routing nodes throughout the network - and thus we have eliminated the major architectural limitation of synchronous OTDM networks.
  • Figure 24 shows the principle of this alternative approach.
  • the phase detector measures the phase angle ⁇ between the free-running local pulse source and the control signal applied to the optical gate (i.e. the packet data bits after the phase shifter). The measured phase angle is then used to control the phase shifter.
  • the control signal to the phase shifter may be either an analogue or digital signal (preferably a digital signal at the packet level), and this control signal would be gated at the rate of once per packet time slot.
  • this is a feed-back, closed loop control system. This has the advantage that the system is free of systematic errors and drift, even if the phase detector is nonlinear.
  • FIG. 25 shows an example embodiment of this alternative form of the bit-asynchronous packet regenerator. The various designated components are as described previously for Figure 22.
  • the description above includes a discussion of the allowable amount of frequency difference between the clock at the packet source and the clock in the asynchronous regenerator.
  • the present embodiment of the asynchronous regenerator using a feed-back, closed-loop arrangement may impose a further restriction on the amount of frequency difference that can be tolerated. It is necessary that the frequency difference between the bit rate of the incoming packet and the full-rate optical clock source in the regenerator is significantly smaller than the effective bandwidth of the control loop (including the electronic bandwidth, the feedback delay and the speed of response of the phase shifter). Following normal engineering practice, the frequency offset should be at least an order of magnitude smaller than the effective bandwidth of the control loop.
  • the phase shifter shown in Figure 25, consisting of DFB laser, switching device UNI 1 , optical filter F3 and dispersion- compensating fibre, could be replaced by a variable optical delay line. Since, in the network scenario discussed above, and illustrated by Figure 23, the packets arriving at the regenerator may be in bit-synchronism. Therefore the bit- asynchronous regenerator merely needs to track the relatively slow variations in the phase difference between the incoming packets and the local clock, rather than abrupt packet-to-packet phase variations.
  • the control loop may therefore be relatively slow acting (much slower than on a packet-by-packet basis). However, the control loop bandwidth should not be so low as to restrict the amount of frequency offset that can be accommodated.
  • the delay line is a variable motor-controlled device, such as a motor-driven fibre stretcher, which is capable of changing the value of the optical delay at a maximum rate of 100 ps per second.
  • a motor-driven fibre stretcher which is capable of changing the value of the optical delay at a maximum rate of 100 ps per second.
  • the maximum allowable frequency offset would be an order of magnitude less than that (to ensure the effective control loop bandwidth is at least 10 times faster than the fastest variations in the signal to be controlled), i.e. " 1 Hz, which is a severe restriction. Therefore a motor-controlled phase shifter may not have sufficient speed of response for this application.
  • Another type of variable optical delay line is a fibre stretcher consisting of a length of fibre coiled tightly around a piezo-electric drum.
  • This type of stretcher is capable of 100 ⁇ m length change at 20 kHz, or approximately 1 ps delay change in 50 ms. in order to achieve a range of ⁇ 5 ps (i.e. ⁇ 0.5 bit periods at 100 Gbit/s), a cascade of piezoelectric drum stretcher units ( 10-20 units) would allow a frequency offset of a few kHz between the local and distant clocks.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Optical Communication System (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

On décrit un régénérateur qui, au niveau d'un noeud d'un réseau de communications optique par exemple, met en oeuvre une source d'horloge locale non asservie, asynchrone au niveau du bit. Un paquet entrant peut être utilisé pour servir de porte à la source d'horloge. Dans certaines formes d'exécution, un certain nombre de portes sont utilisées avec différents retards à l'entrée des instructions et la porte ayant produit une sortie correctement régénérée est choisie. Dans d'autres formes d'exécution, une boucle de régulation est utilisée pour régler la phase de signaux de commande appliqués à une porte.
PCT/GB1999/001159 1998-04-21 1999-04-15 Reseau de communications optique WO1999055038A1 (fr)

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AU36134/99A AU3613499A (en) 1998-04-21 1999-04-15 Optical communications network
CA002329717A CA2329717A1 (fr) 1998-04-21 1999-04-15 Reseau de communications optique
EP99918086A EP1074112A1 (fr) 1998-04-21 1999-04-15 Reseau de communications optique

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GBGB9808491.6A GB9808491D0 (en) 1998-04-21 1998-04-21 Optical communications network
GBGB9812162.7A GB9812162D0 (en) 1998-06-05 1998-06-05 Communications network
GB9812162.7 1998-06-05

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WO2002075446A2 (fr) * 2001-03-16 2002-09-26 University Of Southampton Appareil assurant la modulation optique supportant les gigues d'un premier signal par un deuxieme signal
EP1381178A1 (fr) * 2002-07-11 2004-01-14 Alcatel Démultiplexeur pour signaux optiques temporellement multiplexés
WO2006082418A1 (fr) * 2005-02-02 2006-08-10 The Centre For Integrated Photonics Limited Régénerateur optique asynchrone
US7571320B2 (en) 1999-11-22 2009-08-04 Intel Corporation Circuit and method for providing secure communications between devices
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7571320B2 (en) 1999-11-22 2009-08-04 Intel Corporation Circuit and method for providing secure communications between devices
WO2002075446A2 (fr) * 2001-03-16 2002-09-26 University Of Southampton Appareil assurant la modulation optique supportant les gigues d'un premier signal par un deuxieme signal
WO2002075446A3 (fr) * 2001-03-16 2003-01-03 Univ Southampton Appareil assurant la modulation optique supportant les gigues d'un premier signal par un deuxieme signal
US7003180B2 (en) 2001-03-16 2006-02-21 The University Of Southampton Apparatus for providing timing jitter tolerant optical modulation of a first signal by a second signal
EP1381178A1 (fr) * 2002-07-11 2004-01-14 Alcatel Démultiplexeur pour signaux optiques temporellement multiplexés
US6839159B2 (en) 2002-07-11 2005-01-04 Alcatel Demultiplexer for optical time-division multiplexed signals
WO2006082418A1 (fr) * 2005-02-02 2006-08-10 The Centre For Integrated Photonics Limited Régénerateur optique asynchrone
WO2011057679A1 (fr) * 2009-11-11 2011-05-19 Telefonaktiebolaget Lm Ericsson (Publ) Régénération de signal de données modulé en phase, tout optique
US9025967B2 (en) 2009-11-11 2015-05-05 Telefonaktiebolaget L M Ericsson (Publ) All-optical phase-modulated data signal regeneration

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