WO1999053530A3 - System and method for evaluating genetic programming parse-trees - Google Patents

System and method for evaluating genetic programming parse-trees Download PDF

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Publication number
WO1999053530A3
WO1999053530A3 PCT/US1999/008048 US9908048W WO9953530A3 WO 1999053530 A3 WO1999053530 A3 WO 1999053530A3 US 9908048 W US9908048 W US 9908048W WO 9953530 A3 WO9953530 A3 WO 9953530A3
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WO
WIPO (PCT)
Prior art keywords
parse
primitive
trees
genetic programming
fpga
Prior art date
Application number
PCT/US1999/008048
Other languages
French (fr)
Other versions
WO1999053530A2 (en
Inventor
Robert L Popp
David J Montana
Gordon Vidaver
Suraj Iyer
Sean S B Moore
Original Assignee
Gte Internetworking Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Internetworking Inc filed Critical Gte Internetworking Inc
Publication of WO1999053530A2 publication Critical patent/WO1999053530A2/en
Publication of WO1999053530A3 publication Critical patent/WO1999053530A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Systems and methods consistent with the invention evaluate genetic programming (GP) parse-trees. The system evaluates parse-trees using a field programmable gate array (FPGA) chip (122). The system first provides a primitive transformed from a parse-tree into a format for loading on the FPGA chip (122). The system then loads the primitive on the FPGA chip (122) to evaluate the primitive according to input data corresponding to data executed by the primitive. The system then provides a result of the evaluation of the loaded primitive.
PCT/US1999/008048 1998-04-13 1999-04-13 System and method for evaluating genetic programming parse-trees WO1999053530A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5878698A 1998-04-13 1998-04-13
US09/058,786 1998-04-13

Publications (2)

Publication Number Publication Date
WO1999053530A2 WO1999053530A2 (en) 1999-10-21
WO1999053530A3 true WO1999053530A3 (en) 2000-03-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/008048 WO1999053530A2 (en) 1998-04-13 1999-04-13 System and method for evaluating genetic programming parse-trees

Country Status (1)

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WO (1) WO1999053530A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6668359B1 (en) * 2001-10-31 2003-12-23 Lsi Logic Corporation Verilog to vital translator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867397A (en) * 1996-02-20 1999-02-02 John R. Koza Method and apparatus for automated design of complex structures using genetic programming

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867397A (en) * 1996-02-20 1999-02-02 John R. Koza Method and apparatus for automated design of complex structures using genetic programming

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
"1997 PROJECT SUMMARY EVOLVA WARE BBN SYSTEMS AND TECHNOLOGIES", XP002924519, Retrieved from the Internet <URL:HTTP://WWW.DARPA.MIL/ITO/SUMMARIES97/F287_0.HTML> [retrieved on 19991121] *
KOZA J. R., ET AL.: "EVOLVING SORTING NETWORKS USING GENETIV PROGRAMMING AND RAPIDLY RECONFIGURABLE FIELD-PROGRAMMABLE GATE ARRAYS.", CONFERENCE RECORD OF THE 31ST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS. PACIFIC GROVE, CA., NOV. 2 - 5, 1997., LOS ALAMITOS, CA. : IEEE., US, vol. 01., 1 November 1996 (1996-11-01), US, pages 01 - 06., XP002924517, ISBN: 978-0-8186-8317-6 *
MICCIO C, SANCHEZ E: "PARALLEL GENETIC PROGRAMMING INDUCTION OF BINARY DECISION DIAGRAMS", XP002924520, Retrieved from the Internet <URL:HTTP://WWW.EPFL.CH/SIC/SA/PUBLICATIONS/SCR95/7-95-24A.HTM> [retrieved on 19991121] *
MONTANA D. ET AL.: "EvolvaWare: Genetic Programming for Optimal Design of Hardware-Based Algorithms", PROCEEDINGS OF THE THIRD ANNUAL CONFERENCE ON GENETIC PROGRAMMING., 1998, pages 6, XP002924518 *
POPP R.L. ET AL.: "Automated Hardware Design Using Genetic Programming, VHDL and FPGAs", IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN AND CYBERNETICS., vol. 3, October 1998 (1998-10-01), pages 2184 - 2189, XP002924516 *

Also Published As

Publication number Publication date
WO1999053530A2 (en) 1999-10-21

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