WO1999053530A2

WO1999053530A2 - System and method for evaluating genetic programming parse-trees

Info

Publication number: WO1999053530A2
Application number: PCT/US1999/008048
Authority: WO
Inventors: Robert L. Popp; David J. Montana; Gordon Vidaver; Suraj Iyer; Sean S. B. Moore
Original assignee: Gte Internetworking Incorporated
Priority date: 1998-04-13
Filing date: 1999-04-13
Publication date: 1999-10-21
Also published as: WO1999053530A3

Abstract

Systems and methods consistent with the invention evaluate genetic programming (GP) parse-trees. The system evaluates parse-trees using a field programmable gate array (FPGA) chip (122). The system first provides a primitive transformed from a parse-tree into a format for loading on the FPGA chip (122). The system then loads the primitive on the FPGA chip (122) to evaluate the primitive according to input data corresponding to data executed by the primitive. The system then provides a result of the evaluation of the loaded primitive.

Description

SYSTEM AND METHOD FOR EVALUATING GENETIC PROGRAMMING PARSE-TREES

Technical Field The present invention relates to methods and systems for evaluating genetic programming parse-trees and, more particularly, to methods and systems for evaluating parse-trees using a field programmable gate array (FPGA) chip.

Background Art

As the size of large scale integrated circuits has increased in recent years, design of digital circuits including integrated circuits has become very complicated.

For any particular application, a circuit designer may develop a wide number of possible hardware design solutions. However, the number of hardware designs that the designer may arrive at are limited by the designer's skill and experience. In particular, hardware designs developed by a human designer are often based on simplified models that are prone to inconsistencies and inaccuracies for more complex applications.

To assist hardware designers in the development process, automated design systems have been developed, such as logic synthesis tools, timing correctness tools, and place and route tools. Logic synthesis tools transform a higher-level design description of hardware (e.g., a VHDL behavioral-level model) to a structural description of the hardware (e.g., a gate-level netlist description). Logic synthesis tools can typically back-annotate timing, power, or area usage constraints directly to a VHDL source code. The transformation often occurs indirectly via Boolean logic equations, and various optimizations can be performed on the mapping of the logic equations, the equations themselves, or on the netlist after the mapping to device cells.

Hardware designers use simulation tools to verify that the logic structures in a behavioral-level and gate -level netlist description of hardware design is correct and to verify that the intended functionality, timing and area constraints are met. Current VHDL simulation tools can support timing propagation delays, accurate wire interconnect delays, and conditional timing constraint checks.

Field programmable gate array (FPGA) place and route tools are used to place and route (i.e., map) the logic corresponding to the synthesized gate-level netlist description on an FPGA device itself. These tools may evaluate and verify the reliability, accuracy and timing of FPGA logic when physically realized on an actual device. These tools may also verify chip-level pin interconnect strategies.

FPGA logic download tools can program, on an FPGA device, the logic that is generated by the FPGA place and route tools. This logic would correspond to the hardware description after being transformed from a behavioral-level model to a format for loading on the FPGA device.

However, each of these automated design systems and tools are dependent upon data entered by the user, such as data specifying initial settings of the automation process. If the designs developed by the automated design system are inadequate, the user must change these initial settings to hopefully produce more optimal solutions. Thus, these automated design systems are still constrained by the skill of the human designer.

Therefore, it is desired to have a system and method for automatically designing a hardware design without intervention by a user and that can operate at a high speed. Diclosure of Invention

Systems and methods consistent with the present invention automatically determine hardware designs without user intervention and at a high speed. To achieve these and other advantages, a genetic programming parse-tree evaluation system consistent with the present invention uses a field programmable gate array (FPGA) chip to evaluate the parse-tree. The system then provides a primitive transformed from a parse-tree into a format for loading on the FPGA chip.

The system then loads the primitive on the FPGA chip to evaluate the primitive according to input data corresponding to data executed by the primitive. The system then provides a result of the evaluation of the loaded primitive. Both the foregoing general description and the following Detailed

Description are exemplary and are intended to provide further explanation of the invention as claimed.

Brief Description Of The Drawings

In the drawings: Fig. 1 is a block diagram of a GP parse-tree evaluating system consistent with the present invention;

Fig. 2 illustrates a simplified example of a GP parse-tree that may be evaluated and scored by the GP parse-tree evaluating system of Fig. 1; and

Fig. 3 is a flow diagram of a method consistent with the present invention for evaluating and scoring a parse-tree.

Best Mode for Carrying Out the Invention

A. Introduction

Methods and systems consistent with the invention evaluate parse-trees generated by a genetic programming (GP) processing engine. A GP parse-tree represents a possible hardware design to solve a particular design problem. The GP processing engine typically generates a multiple of GP parse-trees. Using standard

GP techniques, the system then evaluates and scores each parse-tree to eventually determine a parse-tree that represents the optimal solution for solving the design problem. Each GP parse-tree further includes a plurality of nodes. A GP primitive represents the logic of a node of the parse-tree that executes a logical operation. In systems consistent with the invention, the system evaluates nodes of the parse-tree by loading the corresponding GP primitives on a field programmable gate array (FPGA) chip. The FPGA then executes the GP primitive using the data processed by that node of the parse-tree. The GP parse-tree evaluation system can then evaluate the parse-tree in a node-by-node manner. B. System Organization

Fig. 1 is a block diagram of a GP parse-tree evaluating system 100 consistent with the present invention. As shown in Fig. 1, GP parse-tree evaluating system 100 includes a computer 110 communicating with a printed circuit board (PCB) 120 over a bus 125. While computer 110 preferably evaluates parse-tree primitives loaded on PCB 120, alternative embodiments may include a PCB having an on-board processor for evaluating the loaded primitives.

Computer 110 further includes a GP processing engine 112, a very high speed integrated circuit hardware description language (VHDL) toolset 114, an FPGA primitive database 116, and an evaluation and scoring unit 118. In systems consistent with the invention, GP processing engine 112 and evaluation and scoring unit 118 are computer programs resident on computer 110. Such programs may be written in object-oriented languages, such as C++, or non-object-oriented languages. GP processing engine 112 generates GP parse-trees using genetic algorithm or GP processing techniques known to those skilled in the art, such as those disclosed in "Genetic Programming", John R. Koza, MIT Press, Cambridge, Massachusetts,

(1992). Each GP parse-tree represents a computer algorithm for solving a predefined problem.

For purposes of discussion, Fig. 2 illustrates a simplified example of a GP parse-tree that may be evaluated and scored by a GP parse-tree evaluating system consistent with the present invention. In particular, Fig. 2 shows a parse-tree representing a computer algorithm for solving the equation F = (A*B) + C/(D+E). Each node of the tree represents either an operator (i.e., +, -, *, or -) or an operand (i.e., A, B, C, D, or E) of the equation.

GP primitives are the logic of nodes of the parse-tree that execute a logical operation. In the example of Fig. 2, the GP primitives are the nodes corresponding to one of the operators of the equation. The parse-tree of Fig. 2 has a root node that corresponds to the node having the GP primitive "+" as its value. This root node has two children, namely, the left subtree with the GP primitive "*" as the value of its root node and the right subtree with the GP primitive "/" as the value of its root node. When the GP parse-tree evaluating system executes the GP primitive "*", the GP primitive will multiply the data of operands A and B. The result of GP primitive "*" is then passed to the GP primitive "+" for addition with the result of the GP primitive "/", corresponding to the right subtree.

Returning to Fig. 1, VHDL toolset 114 contains VHDL transformation tools for transforming a GP primitive into an FPGA program file equivalent to the GP primitive. In particular, the GP primitive is first transformed into a VHDL program specification. Using a VHDL synthesis tool, the VHDL program specification is then transformed into a gate-level netlist, which is then transformed into a technology-specific FPGA(s) description using an FPGA place and route tool. Finally, a PCB schematic capture tool transforms the technology-specific FPGA(s) description into the FPGA program file capable of being loaded on an FPGA chip. Each of these transformations are known in the art and are performed off-line.

However, systems consistent with the invention may perform these transformations on-line as well.

FPGA primitive database 116 stores the generated FPGA program files for the entire set of GP primitives included in parse-trees generated by GP processing engine 112. Evaluation and scoring unit 118 evaluates each node of a parse-tree generated by GP processing engine 112 and computes a score for that parse-tree after all nodes have been evaluated. Evaluation and scoring unit 118 computes the score or fitness measure of the parse-tree using well known GP techniques, such as those disclosed in "Genetic Programming", John R. Koza, MIT Press, Cambridge, Massachusetts, (1992).

PCB 120 further includes an FPGA chip 122 and a communication interface 124. FPGA chip 122 is preferably a commercial off-the-shelf FPGA chip that can be reprogrammed by computer processor 110. FPGA chip 122 receives, through communication interface 124, FPGA primitives from primitive database 116 over bus 125. Each primitive reprograms FPGA chip 122 to model different types of hardware configurations that execute the logic of the respective primitive. Communication interface 124 sends to evaluation and scoring unit 116, over bus

125, results of each primitive computed by FPGA chip 122. B. Method Process

Fig. 3 is a flow diagram of a method consistent with the present invention for evaluating and scoring a parse-tree. As shown in Fig. 3, the method begins with evaluation and scoring unit 118 determining whether the GP primitive of a respective node of the parse-tree is loaded on the FPGA chip 122 (step 305). If the GP primitive is not loaded on FPGA chip 122, then computer 1 10, via communication interface 124, loads the FPGA program file from FPGA primitive database 116 that corresponds to the GP primitive (step 310). Evaluation and scoring unit 118 preferably determines which node to evaluate, and thus which GP primitives are to be loaded, using standard recursive tree traversal techniques, such as pre-fix, post-fix, and in-fix order. Additionally, computer 1 10 may load more than one GP primitive, or even all the GP primitives of the parse-tree, on FPGA chip 122 at a time when FPGA chip 122 has enough memory space available. In such a case, computer 110 loads the GP primitive(s) corresponding to the node(s) to be evaluated next by GP parse-tree evaluation system 100. FPGA database 116 preferably stores each GP primitive in a memory page using a paging scheme known to those skilled in the art. Each memory page is an FPGA data file that can be loaded onto FPGA chip 122. Further, each memory page may include more than one GP primitive. By using such a paging scheme, the amount of overhead associated with repetitively loading GP primitives can be reduced. For instance, a GP primitive required to evaluate a particular node may be stored on a page already loaded onto FPGA chip 122. Thus, the need to load that GP primitive is eliminated. A paging scheme also allows evaluation and scoring unit 118 to load a plurality of GP primitives onto FPGA chip 122 at the same time. GP processing engine 112 then loads input data on FPGA chip 122, via communication interface 124, for the node being evaluated (step 315). Evaluation and scoring unit 118 evaluates parse-trees node-by-node. Accordingly, the loaded input data is the data processed by a GP primitive at a node of the parse-tree under evaluation. For the parse-tree of Fig. 2, for example, the GP processing engine 112 would load data A and B when the GP parse-tree evaluating system is evaluating the node having the GP primitive "*" as its value.

Once the input data has been loaded, FPGA chip 122 executes the GP primitive using the inputted test data and evaluation and scoring unit 118 scores the results (step 320). Typically, the results of the GP primitive are first stored in a buffer resident on FPGA chip 122. The buffered result data is then sent, via communication interface 124, to evaluation and scoring unit 118. Evaluation and scoring unit 118 stores the results of each node in a memory (not shown) for possible use as input data when evaluating a node higher up on the parse-tree.

Evaluation and scoring unit 118 then determines whether all input data has been input to FPGA chip 122 for execution by the GP primitive loaded thereon (step

325). More specifically, evaluation and scoring unit 118 determines whether there exists another node in the parse-tree having the same GP primitive as its value. If so, processing returns to step 315 where GP processing engine 1 12 loads the required input data for this node on FPGA chip 122, via communication interface 124.

If all input data has been processed, evaluation and scoring unit 118 then determines whether all nodes of the parse-tree have been evaluated (step 330). If not, processing returns to step 305 where evaluation and scoring unit 118 determines whether the GP primitive of the next node to be evaluated is loaded on FPGA chip 122. Otherwise, evaluation and scoring unit 118 outputs the results to GP processing engine 112 (step 335). GP processing engine 112 then evaluates the results of the parse-tree using GP or genetic algorithm techniques known to those skilled in the art, such as those disclosed in "Genetic Programming", John R. Koza, MIT Press, Cambridge, Massachusetts, (1992). For the parse-tree of Fig. 2, for example, the result of the parse tree would be the result of the root node having the GP primitive "+" as its value. Here, the result of GP primitive "+" would be equal to the value of the equation F = (A*B) + C/(D+E).

C. Conclusion

It will be apparent to those skilled in the art that various modifications and variations can be made to the system and method of the present invention without departing from the spirit or scope of the invention. The present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

Claims;

1. A method for evaluating a parse-tree using a field programmable gate array (FPGA) chip, the method comprising the steps of: providing a primitive transformed from a parse-tree into a format for loading on the FPGA chip; receiving input data corresponding to data executed by the primitive; loading the primitive on the FPGA chip to evaluate the primitive according to the input data; and providing a result of the evaluation of the loaded primitive.

2. The method of claim 1, wherein the step of loading the primitive includes the following substeps: determining whether the primitive is already loaded on the FPGA chip; and loading the primitive on the FPGA chip when the primitive is not already loaded on the FPGA chip.

3. The method of claim 1, wherein the parse- tree includes a plurality of interconnected nodes, and wherein the step of loading the primitive includes the following substep: determining which node of the parse-tree to evaluate using a recursive tree traversal technique.

4. The method of claim 1 , further including the step of: storing the transformed primitive in a memory using a paging scheme.

5. The method of claim 4, wherein the storing step further includes the following substep: storing a transformed primitive for each primitive occurring in the parse-tree.

6. The method of claim 1 , wherein the parse-tree includes a plurality of interconnected nodes, and wherein the step of loading the primitive includes the following substeps: determining whether any other nodes of the parse-tree correspond to the transformed primitive loaded on the FPGA chip; and loading input data for other nodes of the parse-tree corresponding to the transformed primitive loaded on the FPGA chip.

7. A system for evaluating a parse-tree using a field programmable gate array (FPGA) chip, the system comprising: means for providing a primitive transformed from a parse-tree into a format for loading on the FPGA chip; means for receiving input data corresponding to data executed by the primitive; means for loading the primitive on the FPGA chip to evaluate the primitive according to the input data; and means for providing a result of the evaluation of the loaded primitive.

8. The system of claim 7, wherein the means for loading the primitive further includes: means for determining whether the primitive is already loaded on the FPGA chip; and means for loading the primitive on the FPGA chip when the primitive is not already loaded on the FPGA chip.

9. The system of claim 7, wherein the parse-tree includes a plurality of interconnected nodes, and wherein the means for loading the primitive further includes: means for determining which node of the parse-tree to evaluate using a recursive tree traversal technique.

10. The system of claim 7, further including: means for storing the transformed primitive in a memory using a paging scheme.

11. The system of claim 10, wherein the means for storing further includes: means for storing a transformed primitive for each primitive occurring in the parse-tree.

12. The system of claim 7, wherein the parse-tree includes a plurality of interconnected nodes, and wherein the means for loading the primitive further includes: means for determining whether any other nodes of the parse-tree correspond to the transformed primitive loaded on the FPGA chip; and means for loading input data for other nodes of the parse-tree corresponding to the transformed primitive loaded on the FPGA chip.