Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L45/00—Routing or path finding of packets in data switching networks
  • H04L45/48—Routing tree calculation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L45/00—Routing or path finding of packets in data switching networks
  • H04L45/74—Address processing for routing
  • H04L45/742—Route cache; Operation thereof

Definitions

• the present invention relates to a network relay device such as a router in a computer network system, and more particularly, to a network relay device suitable for quickly searching for a packet transfer destination address from a bucket destination address that has entered the network relay device. It relates to the device and the method of searching for the next transfer destination on the network. Background art
• a network relay device such as a router is used to connect a plurality of subnets.
• the router checks the destination address of the bucket received from the connected subnet, determines the destination of the bucket, and forwards the received packet to the subnet to which the destination router or host is connected.
• Figure 1 shows the configuration of a general network system in which multiple subnets are connected by a router.
• R1 and R2 are routers
• SN1 is a subnetwork connected to a port P11 of router R1
• SN2 is a port P12 and a router R of router R1.
• H10 and H11 are hosts connected to subnet SN1
• H20 and H21 are connected to subnet SN2.
• the connected hosts, H30 and H31, are the hosts connected to subnet SN3.
• router R1 When sending a bucket from host H10 to host H21, router R1
• the router R1 When sending a bucket from the host H10 to the host H31, the router R1 looks at the destination address DA stored as header information in the bucket, and the destination host H31 sends the subnet. It recognizes that it is on SN3 and that subnet SN3 is not directly connected to router R1, but is connected via router R2. Router R1 outputs the bucket to port P21, which is connected to subnet SN2 to which router R2 is connected, and outputs the next address (next hop address) to be forwarded to when output. Assume 2. In this case, when the router R2 receives the packet, the router R2 looks at the destination address DA and transfers the packet to the host H31, similarly to the router R1.
• TBL is a route search table. This table is created from configuration definition information manually input and information obtained by exchanging connection information between routers.
• the route search table TBL uses the combination of the subnet address and the subnet mask length as a search key, and uses the output port, the next hop address, and information on whether the subnet is directly connected (hereinafter, the next hop). (Called information).
• the subnet bears from the most significant bit side.
• the Radish algorithm maps a path entry to each node of a tree structure composed of a tree in which a plurality of vertices (nodes) with pointers on the left and right are connected by a pointer. By moving one of the pointers to the next node, the target route entry reaches the mapped node.
• Fig. 3 describes the address length as 3 bits for easy understanding.
• each node is assigned a mask length of 0 bits from the top of the tree
• node N 0000 with a mask length of 0 bit the 0th bit of the destination address; according to 0, the left and right pointers are used to form nodes N 000 1 and N 1001 with a mask length of 1 bit.
• the left and right pointers are entered according to whether the first bit is 0 or 1, and the 2-bit mask length node N0002 NO 102, N 100
• N1 102 Move to the left and right pointers according to whether the second bit is 0 or 1 at the 2-bit mask length node, and set the 3-bit mask length node N 000 3, N00 1 Move on to 3, N0103, N0113, N103, N103, N103, 1113.
• the node with the mask length of 0 bit is the destination address.
• the nodes N 000 1 and N 1001 with a mask length of 1 bit pass from left to right when each bit of the destination address is 0 XX and 1 XX.
• Nodes N000 2, N0 102, N 1002, and N 1102 pass from left to right when each bit of the destination address is 00X, 01X, 10X, 11X, Nodes with a mask length of 3 bits N0003, NO013, N01103, N0113, N001003, N103, Nil03, N1113 from left Each bit of the destination address is 0 ⁇ 0, 0
• X indicates that the bit value can be either 0 or 1.
• a node N 0000 having a mask length of 0 bit is passed when the destination address belongs to the subnet address 0 0 ⁇ , and nodes N000 1 and N 1001 having a mask length of 1 bit are transmitted to the destination.
• ⁇ 1102 passes if the destination address belongs to the subnetwork address 000/2, 0100/2, 100/2, 110 12, and a node with a mask length of 3 bits ⁇ 0003 , ⁇ 00 1 3, ⁇ 0 1 0 3, ⁇
• each node in this tree has a one-to-one correspondence with all subnets with different mask lengths and subnet addresses.
• the destination address DA 0 1 1 to be passed is passed when the pointer is entered according to whether each bit is 0 or 1 from the top of this tree. Nodes with "*" marked N 00.00, NO 102 Force with mask It is found that the search corresponds to the matching entry. Therefore, when multiple route entries match, the subnetwork with the longest mask length is selected. According to the rules, the most terminal node among the matching nodes NO 000 and NO 102 with "*" is selected.
• the route information allocated to the node NO102 close to is set as the search result of the route table.
• nodes N 0003, N 0 1 0 3 N N 0 1 1 3 and N 1 00 are not attached and are not on the way to reach the node with. 3, N1013, N111, and N1002 do not affect the search results even if they are removed from the tree. Rather, when is not attached to the bottom node, it is more efficient because the search ends without moving to the bottom. Then, nodes that are not attached and that are not on the way to reach the node marked with "*" are removed from the tree as shown in Fig. 5.
• the address length is 32 bits and the routing table shown in Figure 6
• the comparison results in a match it means that the correct node has been reached.In other words, it means that the node has been reached even after comparing one bit at a time in a non-degenerate tree. It means that there is no destination in a tree that does not degenerate.
• the 0th bit has already been tested, and the branch having the 0th bit being equal has been selected, and therefore always matches.
• every time you reach a certain node every time you reach a certain node,
• the bits from the 0th bit to the mask length of the node are guaranteed to be equal in the destination address and the subnet address of the node.
• the bits from bit 0 to the mask length of the node are the same as the destination address and the node's subnet quad, regardless of which bit was previously tested. You can check if they are the same with the Les. Disclosure of the invention
• the destination address is checked one bit at a time from the top in order to search for a route, and there is a problem that it takes time for the route search process.
• An object of the present invention is to provide a network relay device, particularly a router, which executes a high-speed path search process at the time of transfer for transferring a bucket.
• Another object of the present invention is to provide a network next transfer destination search method in which a network relay device such as a router quickly searches for a transfer destination address of a bucket from a destination address of a received bucket.
• a network relay device such as a router quickly searches for a transfer destination address of a bucket from a destination address of a received bucket.
• the upper few bits of the search tree are incorporated in the LSI that performs search processing
• the number of branches in the search tree is increased from the binary tree node in the prior art by a quadratic tree, an octal tree, or more, by a power of two, and the number of branches is increased by one. It checks not only one bit but two, three, or more consecutive bits at the same time to reduce the number of nodes before the end of the search.
• an 8-tree when forming a quadtree, an 8-tree, or generally a 2 p-th power tree, one 2-minute tree is used.
• the 2p-th binary tree node is transformed into a binary tree of 2 (p-1 )
• the node mask length must be known before reading the node data.
• Each node has the mask length of the node immediately below that node. To be stored. At the head of each node, a flag indicating whether or not a route is assigned to the node is provided. First, this flag is read, and for a node to which no route is assigned, the route information is set. By not reading the data, the data reading time is reduced.
• FIG. 1 is a configuration diagram of a general network system based on the present invention.
• Fig. 2 illustrates the route search specification in the router
• Fig. 3 illustrates a binary tree with all nodes when the address length is 3 bits
• Fig. 4 when the address length is 3 bits.
• FIG. 5 is a diagram illustrating a tree in which no route is assigned and a node that is not an intermediate route to a node with a route is removed.
• Fig. 6 is a diagram showing an example of a route table in the case where the end length is 32 bits
• Fig. 7 is a diagram for explaining a tree corresponding to the route table shown in Fig. 6, and Fig. It is a figure explaining the tree which removed the node which has not been allocated.
• Fig. 1 is a configuration diagram of a general network system based on the present invention.
• Fig. 2 illustrates the route search specification in the router
• Fig. 3 illustrates a binary tree with all nodes when the address length is
• FIG. 9 is a diagram illustrating a tree with 2-bit mask length expanded in the memory and excluding the search time for the 0th to 1st bits.
• Fig. 10 is a route search for nodes up to the kth bit of the mask length. Diagram of memory configuration when placed in LSI, Fig. 11 shows a time chart of conventional route search processing without performing pipeline processing, and Fig. 12 shows route search for nodes up to the k-th bit of mask length.
• FIG. 9 is a diagram showing a time chart showing a pipeline process of a route search when the device is placed in an LSI.
• FIGS. 13 to 15 are diagrams illustrating trees surrounding a binary tree node, which are combined into one octal node when the binary tree is transformed into an octal tree.
• Figure 1 ⁇ explains the tree that searches for bits up to the separation position by expanding the first node in the memory when the bit position is divided so that the mask length does not start from 0 bit
• FIGS. 18 to 20 combine FIGS. 9 with FIGS. 16 and 17, respectively, to illustrate a tree excluding the search time for a larger number of bits at the beginning
• FIG. FIG. 8 is a diagram illustrating a tree in which three binary tree nodes that are combined into one quadtree node when a binary tree is transformed into a quadtree node are crushed into two binary tree nodes.
• Figures 22 to 30 are grouped into one quadtree node.
• Figure 3 shows how two binary tree nodes are crushed into two binary tree nodes.
• Figure 31 shows four binary tree nodes that are combined into one octal tree node.
• Fig. 3 illustrates the tree expansion model when estimating the amount of memory required for the tree configuration.
• Fig. 32 illustrates the tree expansion model when estimating the amount of memory required for the tree configuration.
• Fig. 3 shows a comparison of the amount of memory considering the existence probability of the nodes when the node is configured and when it is composed of 4 and 8 tree node nodes.
• Fig. 34 shows the structure of the binary tree node.
• Figure 36 shows the structure of the branch node.
• Figure 36 shows a part of the node without reading the entire node to prevent the node data read time from increasing when the node size increases.
• Figure 37 shows how to read only elements. Figure 37 shows that elements that do not need to be read depending on conditions are not read according to the conditions. Ru Figure der illustrating a method to increase the speed by reducing the loading time and this.
• FIG. 38 is a block diagram showing an example of the configuration of the router, and
• FIG. 39 is a block diagram showing another example of the configuration of the router.
• 100 is a router device
• 110 is a routing control unit
• 120 is a router bus
• 130 is a network interface unit
• 140 is a port
• 15 ⁇ is a sub-unit.
• the network interface unit 130 receives a bucket from the sub-network connected to the port 140, and sends the received bucket to the routing control unit 110 via the router bus 120.
• the routing control unit 110 is a routing controller that holds routing information.
• FIG. 39 is a block diagram illustrating another configuration example of the router device. Fig. 3
• 200 is a router device
• 210 is a notifying processor (RP)
• 220 is communication means in the router device
• 230 is a network interface unit
• 240 is a port
• 2 50 is a subnetwork
• 260 is a router management unit.
• the routing control unit 110 of the configuration shown in FIG. 38 manages the routing port processor 210 and the router device 200 which execute the routing function. It is divided into 0, and includes a plurality of portions each including a network interface unit 230 and a routing processor 210 corresponding to the configuration shown in FIG.
• the routing management unit 260 has a management function of the entire router device 200 and distributes routing information to each routing processor 210.
• the communication means 220 in the router device is a crossbar switch or a bus, and performs communication between the routing processors 210 and communication between the routing processor 210 and the routing management unit 260. .
• the routing processor 210 transfers packets between the network interface unit 230 connected to itself as in the case of the routing control unit 110 in Fig. 38.
• routing control unit 110 and the routing processor 2 1 are identical to the routing control unit 110 and the routing processor 2 1
• FIG. 9 shows an example in which nodes N0002, N0102, N1002, and Nil02 each having a mask length of 2 bits are developed at a fixed position in the memory.
• the nodes N 000 2, N 0 102, N 1002, and N 1102 having a mask length of 2 bits are developed from the values of the 0th bit and the 1st bit. Find the address and jump directly to one of the two-bit mask length nodes NO002, N0102, N1002, and N102. As a result, the search time is reduced by the time required for two node searches.
• the search time is reduced by the amount of time required to cross the nodes a total of m times.
• the nodes up to k bits in the mask length are expanded to the internal memory ML1 of LSIL1 that performs a path search, and the nodes with mask lengths of k + 1 bits or less are stored in the memory M1 outside LSIL1. expand. By doing so, high-speed access to the memory ML 1 inside the LSIL 1 and pipeline processing can be performed because the memory ML 1 inside the LSIL 1 and the external memory M 1 are independent memories.
• Fig. 11 shows a time chart of the conventional case without pipeline processing.
• Fig. 12 shows a pipe for route search processing between the memory ML 1 inside the LSIL 1 and the external memory M 1 according to the present invention. Time charts when line processing is performed are shown. Conventionally, as shown in Fig. 11, when a route search of a certain packet (packets 1, 2, and 3) is performed, node search processing PR 10 up to k bits of the mask length of bucket 1 is performed.
• the search processing PR11 of the node after the mask length k + 1 bits of the bucket 1 is performed using the memory M1 outside the LSIL1.
• the search process PR20 for nodes up to the mask length k bits of the bucket 2 is started using the memory ML1 inside the LSIL1.
• the search processing PR 21 for the node after the mask length k + 1 bit of the packet 2 is started using the memory Ml external to LSIL 1 and the LSIL (1) Using the internal memory ML1, search processing for nodes up to k bits of mask length in packet 3 PR20 is started. Thereafter, the packet search processing is similarly performed by pipeline processing.
• the third method of speeding up is to set two p-th branch destinations to one node, instead of one node that previously had two branch destinations and searched one bit at a time. By searching p bits at a time, the search time is reduced to 1 compared to the past.
• a node that has a branch destination of 2 p to one node is referred to as a 2 p-th tree node.
• the 2nd p-th tree node is created by deforming a tree composed of a binary tree node, which is a conventional method.
• the method of tree transformation is as follows: one binary tree node at the n-th bit, and the binary tree at the n + 1 to n + p-1 bit below the binary tree node
• the node is made to correspond to one 2 p-th tree node.
• FIGS. 13 to 15 show a method of transforming a binary tree into an octant tree.
• the second to fourth, 5 to 7, 8 to 10, 11 to 13, 14 to 16, 17 to: 19, 20 to 22, 23 to 25, 26-28, 29-31, and 32-bit nodes are each one octree node.
• the entire tree uses one of the above three ways of dividing the bit positions so that routes can be easily added or deleted.
• FIG. 9 shows the method shown in Fig. 9 to expand a node with a mask length of m bits into memory.
• Figures 16 and 17 show the tree structures in which the nodes of the first bit of the octree corresponding to the break positions shown in Figs. 14 and 15 are expanded in memory.
• nodes N8013 and N8113 with a mask length of 1 to 3 bits are arranged at fixed positions in the memory, and each is selected according to whether the 0th bit is 0 or 1.
• the nodes N80024, N80124, N81024, and N8124 with a mask length of 2 to 4 bits are arranged at fixed positions in the memory, and Select 0 to 1 bit power 00 power 01 power 1 0 power 11 power.
• the number of nodes to be arranged first is not 1, 2, or 4 but 8 times these 8, 16, 32, or 8 to the power of 64, 128, 256, or generally 8 to the q-th power, the first time, twice, or generally 2 to the power of p It is possible to eliminate the search time for q times of tree nodes.
• Figure 18, Figure 19, and Figure 20 show how to expand nodes into memory for the case of a break position.
• Figure 21 shows a quadtree with one binary tree node A, B, C, D, and E and two binary tree nodes AO, Al, BO, Bl, C0, and Cl immediately below it. , D 0, D l, E 0, and E l for a total of three binary tree nodes to form one quad tree node N 401, 4023, N 4123, N 4223, N 4 423 Then, a total of three binary tree nodes are crushed to make the size of the lower binary tree node only.
• the route is searched according to the route search specification that adopts the route with the longer mask length. In such a case, the condition that the route search result is the same is satisfied.
• Figures 22 to 30 show how to collapse this node in the case of a quadtree.
• route information is assigned to all nodes.
• route information * A is assigned to the upper node A and the route is not assigned only to A1 of the lower nodes A0 and A1 (Fig. 23), the route information of A1 is assigned to the route information of A1.
• Route information * Insert A is assigned to the same applies to a case where a route is not assigned to A0 of the lower nodes A0 and A1.
• the route information contains the route information * A of the upper node A. Since no node is connected below node A1, Insert NULL into the pointer to the node under node A1. The same applies to the case where the route is not assigned only to AO of the lower nodes AO and A1.
• route information * A is not assigned to the upper node A and no route is assigned to A 1 of the lower nodes A 0 and Al (Fig. 28), There is no route information for A1.
• Figure 31 (a) shows an example in which there are all seven binary tree nodes that are combined into one, but only some of them have routing information. Of the four nodes at the bottom, nodes A 0 1 and A 10 to which no route information is assigned are assigned to the lowest node to which the route information is assigned among the nodes connected above that node. That is, the route information * A, * a1 of the node with the longest mask length (A, A1, respectively) is entered.
• Figure 3 1 (b) shows an example in which only some of the seven binary tree nodes that combine into one node exist, and nodes AO 1 and A 10 that do not exist are nodes to which no route is assigned first. And insert the route information according to the same rules as in Figure 31 (a). Of the bottom four nodes AO 0, A01, A10, All, supplemented nodes A01, A10, no nodes are connected below, so a pointer to the lower node Is set to NULL. In general, in the case of a 2 p-th power tree, do the same in the same way. Combine them into 2 p -th power. Crush one binary tree node, and leave only the bottom 2 (p-1) power nodes. To the size of.
• the number of routes is approximately 10 k routes.
• Figure 32 shows the tree shape constructed under this approximation. According to this approximation, the extent of the tree every 1 bit down is 1 Ok to the (1/32) th power, or about 1.33 times.
• Fig. 33 (a) a comparison of the amount of memory when this tree is composed of a binary tree node and when it is composed of a quadtree node will be described. Focusing on the upper one node N2 of the three binary tree nodes constituting the quadtree node, about 1.33 nodes are directly below. That is, nodes N20 and N21 are attached with a probability of ⁇ . Therefore, the average of the binary tree nodes N 2, N 20, and N 2 1 that make up the quadtree node, taking into account the existence probability of the node with the total memory amount, is the binary tree node (1 + 1.33) This is the number of pieces, that is, 2.33 pieces. When a tree is composed of quadtree nodes, these three quadtree nodes become one quadtree node N4, and the memory usage of this single quadtree node is the binary tree nodes N20 and N2. 1 for 2
• Quadrant 2.33 2 0 86 times
• 2-branch tree 8-branch tree 2. 4.1 1 4 0 97 times
• 2-branch tree 1 28-branch-1 9.49 64 3 28 times
• the spread of the tree every lbit is 1 M (1Z32), that is, about 1.54 times.
• the ratio of the amount of memory in the case of 8, 16, 32, 64, 128, and 256 trees is as follows.
• the memory usage efficiency is better if it is up to an 8-ary tree in the 10k path and up to a 16-ary tree in the 1M path. Even with a 256-tree tree, the memory usage increases only to 3.28 times for the 10 k path and 2.26 times for the 1M path. The reasons why the memory usage efficiency does not become so bad are as follows.
• the nodes after aggregation are more compact than the sum of the nodes before aggregation. That is,
• the three binary trees become quad trees twice as large as the nodes of the binary tree.
• the binary tree nodes are 2, 4,
• the memory size of the branch node can be further reduced.
• the only elements that need to be kept between the binary tree nodes that are combined into one are the subnet mask address and the subnet mask length, but the subnet mask length is the subnet of the node itself as described later. Since the subnetwork mask length of the node immediately below this node is used instead of the workmask length, there is no effect of reducing the amount of memory.
• Figures 34 and 35 show this.
• Figure 34 shows the structure of the binary tree node.
• the mask lengths 0 and 1 of the next node are not the subnetwork mask length of this node itself, but the subnodes of the node immediately below this node.
• Network mask length The reason for setting the mask length of the node immediately below instead of the node itself is to increase the speed, and a description thereof will be given later with reference to FIG.
• Flag O and Flagl are bits indicating whether the sub-network corresponding to this node is directly connected to this router or connected via one or more other routers, and FIG. 37.
• a flag indicating whether or not this node is a node to which a route is assigned, that is, in the example of the tree shown in FIG. Other. Enter the same value for F l a g O and F l a g l. This is so that only one of code W0 and code W1 needs to be read. The speedup by reading a part of the nodes instead of reading them all will be described later using Fig. 36.
• the pointers 0 and 1 to the next node are pointers to the next node when the value of the bit position indicated by the mask length of this node of the destination address is 0 and 1, respectively.
• the subnet address is the subnet address corresponding to this node.
• the output port number and next hop address are the routing information assigned to this node, and the address of the port to which the incoming bucket should be output and the router to which the bucket on that port should be sent. It is.
• FIG. 35 shows the structure of the quadtree node created by this method.
• the binary tree node is slightly larger than 16 bytes, which is a power of 2, but the quadtree node is By keeping only one subnetwork address in one node, it can be just fit in 32 bytes, which is a power of two. If the node is an octant node and one node has only one subnet network address, it will fit in the size of 64 bytes and have a margin of 4 bytes. Can be used to insert information. Increasing the number of binary trees to be combined further reduces the size of one node to the power of two.
• the configuration of hZw can be made very simple.
• the following is an example that can simplify the h / w configuration and its advantages.
• the advantage is that it does not fall. .
• the address of each element in a node when finding the address of each element in a node, the upper bits of the address are replaced by the pointer value and the lower bits are not added to the pointer to the node and the offset from the pointer.
• Can be offset for example, if a quadtree node fits in 32 bytes, then the address of an element in a node is As described above, the advantage is that it is only necessary to assign the harmful U and the offset to the element in the node from the 2 0th bit card to the 2 4th bit of the address.
• the first byte address 32 of the next node is used as a pointer to the next node held in each node.
• the advantage is that data can be reduced by 5 bits per pointer in one node.
• Fig. 36 shows an example of a quadtree.As shown in Figs. 34 and 35, a quadtree node with a mask length of m bits has a value of 0 for the mth bit of the destination address. Since the binary tree node corresponding to the case and the binary tree node corresponding to the case of 1 are combined, look at the value of the m-th bit of the destination address, and By reading only the tree node part, the same as the case of the binary tree node even if the node size becomes large
• the subnet primary address which is the only element between the binary tree nodes that are combined into one, is read regardless of the value of the m-th bit of the destination address. I do.
• the amount of data to be read can be further increased. Reduce.
• This method can be used for binary trees. For example, in the case of a binary tree at the m-th bit, look at the value of the m-th bit of the destination address and read only one of the pointers to the two next nodes.
• the method of reading the mask length m of the node at the beginning of reading the data of one node is the gate delay in the search processing LSI for extracting the value of the m-th bit of the destination, and the method of reading the next part.
• the time from when the address is output to the memory until the data from the memory is read into the search processing LSI.
• the time from when the mask length m is read for the memory read latency to when the next part to be read is selected and read. The effect of improving performance by reading only a part of the node is small.
• the order in which the data of one node is read is as follows: first, the mask length m of the next node, the pointer to the next node, and then the subnetwork address.
• the address of the first part to be read by the next node can be calculated fastest.
• the pointer to the next node points to the beginning of the memory area of the next node, and the offset of the address from the beginning of the next node to the first part to be read reads the mask length m of the next node. It can be obtained by checking the value of the corresponding bit position of the destination address.
• Fig. 37 shows how to reduce the time required for reading by not reading elements that do not need to be read depending on conditions within one node, according to the conditions. And explain.
• Figure 37 is an example of a quadtree case.
• routes are not assigned to all nodes, and nodes need to be provided at branch branches even if no routes are assigned.
• information indicating whether this node is a node to which a route is assigned is included in the flag read at the beginning of the node data, and no route is assigned. By not reading the output port and the next hop address at the node, the reading time can be reduced.
• the information as to whether or not this node is a node to which a route is assigned can be represented by 1 bit, so the increase in read time due to reading this information is small.
• the present invention relates to a network next transfer destination search method suitable for a network relay device such as a router, and a network relay device using the same, and a packet received by the network relay device.
• the address of the transfer destination can be searched at high speed, and the bucket processing performance of the network relay device can be improved.

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