WO1999047941A3 - Verbindungstestvorrichtung zum testen der elektrischen verbindungen zwischen chips oder chip-modulen - Google Patents

Verbindungstestvorrichtung zum testen der elektrischen verbindungen zwischen chips oder chip-modulen Download PDF

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Publication number
WO1999047941A3
WO1999047941A3 PCT/DE1999/000704 DE9900704W WO9947941A3 WO 1999047941 A3 WO1999047941 A3 WO 1999047941A3 DE 9900704 W DE9900704 W DE 9900704W WO 9947941 A3 WO9947941 A3 WO 9947941A3
Authority
WO
WIPO (PCT)
Prior art keywords
chips
chip modules
connection
testing device
testing
Prior art date
Application number
PCT/DE1999/000704
Other languages
English (en)
French (fr)
Other versions
WO1999047941A2 (de
Inventor
Albrecht Mayer
Original Assignee
Siemens Ag
Albrecht Mayer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Albrecht Mayer filed Critical Siemens Ag
Publication of WO1999047941A2 publication Critical patent/WO1999047941A2/de
Publication of WO1999047941A3 publication Critical patent/WO1999047941A3/de

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Der von der Verbindungstestvorrichtung durchgeführte Verbindungstest erfolgt unter Veranlassung der Chips oder Chip-Module zur Ausgabe bestimmter Signale über deren Ein- und/oder Ausgabeanschlüsse und zur Weitergabe von über die Ein- und/oder Ausgabeanschlüsse empfangenen Signalen zur Verbindungstestvorrichtung, und unter Vergleichen der von den Chips oder Chip-Modulen empfangenen Signale mit Soll-Empfangssignalen. Hierzu bedient sich die Verbindungstestvorrichtung eines in den Chips oder Chip-Modulen untergebrachten Testmoduls, das dazu ausgelegt ist, Komponenten des die Chips oder Chip-Module enthaltenden Systems selektiv individuell anzusprechen.
PCT/DE1999/000704 1998-03-17 1999-03-15 Verbindungstestvorrichtung zum testen der elektrischen verbindungen zwischen chips oder chip-modulen WO1999047941A2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1998111576 DE19811576C1 (de) 1998-03-17 1998-03-17 Verbindungstestvorrichtung zum Testen der elektrischen Verbindungen zwischen Chips oder Chip-Modulen
DE19811576.8 1998-03-17

Publications (2)

Publication Number Publication Date
WO1999047941A2 WO1999047941A2 (de) 1999-09-23
WO1999047941A3 true WO1999047941A3 (de) 1999-11-18

Family

ID=7861207

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1999/000704 WO1999047941A2 (de) 1998-03-17 1999-03-15 Verbindungstestvorrichtung zum testen der elektrischen verbindungen zwischen chips oder chip-modulen

Country Status (2)

Country Link
DE (1) DE19811576C1 (de)
WO (1) WO1999047941A2 (de)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0636976A1 (de) * 1993-07-28 1995-02-01 Koninklijke Philips Electronics N.V. Mikrokontroller mit hardwaremässiger Fehlerbeseitigungsunterstützung nach dem Baundary-Scanverfahren
US5410686A (en) * 1993-11-01 1995-04-25 Motorola, Inc. Methods for scan path debugging

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0578858A1 (de) * 1992-07-17 1994-01-19 International Business Machines Corporation AC-Verbindungsprüfung für integrierte Schaltungsbausteine
JPH06249919A (ja) * 1993-03-01 1994-09-09 Fujitsu Ltd 半導体集積回路装置の端子間接続試験方法
US5691991A (en) * 1995-03-17 1997-11-25 International Business Machines Corporation Process for identifying defective interconnection net end points in boundary scan testable circuit devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0636976A1 (de) * 1993-07-28 1995-02-01 Koninklijke Philips Electronics N.V. Mikrokontroller mit hardwaremässiger Fehlerbeseitigungsunterstützung nach dem Baundary-Scanverfahren
US5410686A (en) * 1993-11-01 1995-04-25 Motorola, Inc. Methods for scan path debugging

Also Published As

Publication number Publication date
DE19811576C1 (de) 1999-09-09
WO1999047941A2 (de) 1999-09-23

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