WO1999034443A9 - Ceramic microelectronics package with co-planar waveguide feed-through - Google Patents

Ceramic microelectronics package with co-planar waveguide feed-through

Info

Publication number
WO1999034443A9
WO1999034443A9 PCT/US1998/026263 US9826263W WO9934443A9 WO 1999034443 A9 WO1999034443 A9 WO 1999034443A9 US 9826263 W US9826263 W US 9826263W WO 9934443 A9 WO9934443 A9 WO 9934443A9
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
ceramic
circuit substrate
patterns
ground
Prior art date
Application number
PCT/US1998/026263
Other languages
French (fr)
Other versions
WO1999034443A1 (en
Inventor
Timothy J Going
Alan W Lindner
Original Assignee
Stratedge Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stratedge Corp filed Critical Stratedge Corp
Priority to AU18149/99A priority Critical patent/AU1814999A/en
Publication of WO1999034443A1 publication Critical patent/WO1999034443A1/en
Publication of WO1999034443A9 publication Critical patent/WO1999034443A9/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching

Definitions

  • the present invention generally relates to the field of microelectronic packages for high-frequency electronic devices, and specifically relates to a ceramic microelectronic package with co-planar waveguide feed-through for use as an electronic interconnect housing for a high-frequency electronic device.
  • a key requirement for the packaging of a microelectronic device is that signals move through the package's conductive interconnects such that the electrical interconnection causes minimal change in the signals. It is difficult, however, to fabricate microelectronic packages to achieve minimal signal change at higher frequencies, i.e., greater than 20 Gigahertz (GHz) . Along with limited frequency ranges, conventional microelectronic packages have excessive transmitted and reflective loss, limited input/output isolation, high cost, and limited reliability, resulting in a lack of general applicability. The above-listed related applications and patents disclose improved ceramic microelectronic packages that address one or more of the problems due to limitations and disadvantages of the related art. For example, U .S. Pat. No.
  • 5,448,826 shows a ceramic microelectronics package 1 00 suitable for housing high-frequency electronic devices, as shown in FIGs. 1 -3 herein.
  • Package 1 00 includes a base 1 02, first attaching means 1 04, a ceramic radio-frequency (RF) circuit substrate 1 06, second attaching means 1 08, a ceramic seal ring substrate 1 1 0, non-conducting third attaching means 1 1 2, and a ceramic lid 1 1 4.
  • Package 1 00 is used as an electronic interconnect housing for a high-frequency (i.e., beyond 20 GHz) electronic device or component 1 1 6 mounted to base 1 02.
  • Device 1 1 6 is received within a cavity 1 20 formed within circuit substrate 1 06.
  • a plurality of conductive traces 1 22 patterned on circuit substrate 1 06 provide electrical connections between device 1 1 6 and an external device (not shown) .
  • Seal ring substrate 1 1 0 has a cavity 1 24 larger than cavity 1 20.
  • Device 1 1 6 is an exemplary high-frequency electronic device housed within package 1 00, and it is understood that device 1 1 6 represents any high-frequency electronic device or component.
  • Package 1 00, and the process for making package 1 00, are fully disclosed in the '826 patent, which is incorporated herein by reference.
  • Each conductive trace 1 22 in package 1 00 forms a portion of a microstrip transmission line.
  • "Microstrip transmission line" is defined herein as being a conductor suspended above a ground plane and separated from the ground plane by a dielectric.
  • Each conductive trace 1 22 is a conductor, base 1 02 forms a ground plane, ceramic circuit substrate 1 06 is a dielectric, and each trace 1 22 is suspended above base 1 02 and is separated from base 1 02 by substrate 1 06.
  • each conductive trace 1 22 forms a portion of a microstrip transmission line which propagates a signal between the external device and device 1 1 6 as electric and magnetic fields.
  • the impedance of microstrip transmission lines is a function of the dielectric value of substrate 1 06, the width of traces 1 22, the gap to the top surface of the ground plane formed by base 1 02, and the thickness of substrate 1 06 below traces 1 22. Mathematical formula are known which approximate the impedance for given dielectric and conductor parameters and geometries.
  • Each microstrip transmission line in package 1 00 has the form of a microstrip, embedded microstrip, microstrip transmission line as the line transitions from outside package 1 00, beneath seal ring substrate 1 1 0, to inside package 1 00.
  • "Embedded microstrip transmission line” is defined herein as being a microstrip transmission line embedded beneath a second dielectric.
  • each microstrip transmission line passing beneath seal ring substrate 1 1 0 has the form of an embedded microstrip transmission line, and the portions of each microstrip transmission line on either side of substrate 1 1 0 (i.e., not beneath substrate 1 1 0) have the form of regular (i.e., non-embedded) microstrip transmission lines.
  • microstrip transmission lines in package 1 00 transition through microstrip feed-throughs when entering and exiting the package.
  • "Feed-through” is defined herein as an area having different dielectric surroundings through which a conductor passes.
  • the presence of seal ring substrate 1 1 0 causes the microstrip transmission lines to pass through such an area as the transmission lines transition from outside package 1 00 to inside package 1 00.
  • the feed-throughs of package 1 00 can be referred to as microstrip feed-throughs.
  • microelectronics package 1 00 has advantages over the related art, it can still be improved upon as shown by the present invention.
  • electrical testing probes for use with package 1 00 extend the signals on traces 1 22 along the plane of the package. Such probes are relatively difficult to design and are relatively unreliable.
  • package 1 00 houses a high-frequency gallium arsenide (GaAs) integrated circuit (IC) device having microstrip transmission lines
  • GaAs gallium arsenide
  • IC integrated circuit
  • it can be difficult to maintain proper geometry when connecting the microstrip transmission lines of package 1 00 with the microstrip transmission lines of the GaAs device because the ground traces are not on the same plane as the signal traces.
  • GaAs devices having co-planar waveguide (CPW) transmission lines thereon.
  • CPW co-planar waveguide
  • this enhancement can be achieved by providing internal connections between ground traces deposited on the ceramic circuit substrate and the base of the package. These connections are made by wire or ribbon bonds passing through ears cut into the substrate. The incremental cost of these additional connections is small since bonds are already used to connect the electronic device to the package, or to connect the package to an external device.
  • the composite or low-expansion metal base 1 02 of package 1 00 is a relatively expensive material which also limits the options available for the material used for attaching means 1 04, thereby increasing its cost.
  • Base 102 also limits manufacturing process options since means 104 cannot be used while package 1 00 is under construction in the array form. It would be desirable to decrease the costs associated with base 1 02, including the costs of the materials used for base 1 02 and attaching means 1 04, and the impact of the limits imposed on the manufacturing process.
  • the composite or low-expansion metal base 1 02 of package 1 00 also limits the frequency performance of package 1 00.
  • higher frequencies can be achieved by decreasing the thickness of ceramic circuit substrate 1 06 and using correspondingly narrower conductive signal traces 1 22.
  • thin ceramic layers can be difficult to reliably process.
  • the thickness of ceramic circuit substrate 1 06 is limited to a minimum thickness of 0.01 0" . It would be desirable to provide a ceramic microelectronics package suitable for housing a high-frequency device wherein frequency performance is not limited by the practical limits on the thickness of the circuit substrate. This advantage is also realized in the fifth embodiment of the present invention.
  • These advantages include being compatible with electrical testing probes which can connect vertically to the package with the transmission lines extending upwardly, having transmission lines in the same plane as the CPW transmission lines of certain GaAs devices, having enhanced grounding implemented at little or no incremental cost, having a base material made of a lower-cost material which can be attached using less expensive means and manufacturing process options, and providing improved frequency performance which is not limited by the thickness of the ceramic circuit substrate.
  • One embodiment of the present invention relates to a ceramic microelectronic package suitable for housing a high-frequency electronic device.
  • the package includes a base, a ceramic circuit substrate attached to a top surface of the base and having a cavity for receiving the electronic device, and a plurality of conductive patterns deposited on a surface of the ceramic circuit substrate.
  • the conductive patterns include at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a co-planar waveguide (CPW) transmission line.
  • CPW co-planar waveguide
  • Another embodiment of the present invention relates to a ceramic microelectronic package suitable for housing a high-frequency electronic device.
  • the package includes a base, a ceramic circuit substrate attached to a top surface of the base and having a first cavity for receiving the electronic device, and a plurality of conductive patterns deposited on a surface of the ceramic circuit substrate.
  • the conductive patterns include at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a CPW transmission line.
  • a ceramic seal ring substrate is attached to the ceramic circuit substrate and has a second cavity larger than the first cavity, and a ceramic lid is attached to the ceramic seal ring substrate.
  • a middle portion of the CPW transmission line passes beneath the ceramic seal ring substrate such that the CPW transmission line forms a CPW, embedded CPW, and CPW transmission line.
  • the package includes a base, an RF circuit substrate attached to a top surface of the base and having a cavity for receiving the electronic device, and a plurality of conductive patterns deposited on a surface of the RF circuit substrate.
  • the conductive patterns include at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a CPW transmission line.
  • a dielectric sealing cap is attached to the RF circuit substrate and has a chamber larger than the cavity of the RF circuit substrate. A middle portion of the CPW transmission line passes beneath the sealing cap such that the CPW transmission line forms a CPW, embedded CPW, and CPW transmission line.
  • Another embodiment of the present invention relates to a process for assembling a ceramic microelectronic package for retaining a high-frequency integrated circuit.
  • the package has a base and a ceramic circuit substrate.
  • the process includes depositing a plurality of conductive patterns on a top surface of the ceramic circuit substrate, the patterns including a plurality of conductive signal patterns and a plurality of conductive ground patterns, each of the conductive signal patterns being flanked by a pair of the conductive ground patterns to form at least a portion of a plurality of CPW transmission lines for providing electrical connections between the integrated circuit and an external device.
  • the process also includes cutting a cavity having dimensions for receiving the integrated circuit into the ceramic circuit substrate, attaching a top surface of the base to a bottom surface of the ceramic surface substrate to form an assembly, and firing the assembly.
  • FIG. 1 is an exploded view of a ceramic microelectronics package with microstrip transmission lines for use as an electronic interconnect housing for a high-frequency electronic device, the package of FIG. 1 being part of the background of the present invention;
  • FIG. 2 is a top view of the ceramic microelectronics package shown in FIG. 1 with the lid removed;
  • FIG . 3 is a cross-sectional view of the ceramic microelectronics package shown in FIG. 2 with the lid removed taken along line 3-3 in FIG. 2;
  • FIG. 4 is an exploded view of a ceramic microelectronics package with co-planar waveguide (CPW) transmission lines for use as an electronic interconnect housing for a high-frequency electronic device in accordance with a first embodiment of the present invention, wherein each CPW transmission line includes a signal trace and flanking ground traces, each ground trace having a portion exposed outside the package for external connection to electrical ground;
  • CPW co-planar waveguide
  • FIG . 5 is a top view of the ceramic microelectronics package shown in FIG. 4 with the lid removed;
  • FIG. 6 is a cross-sectional view of the ceramic microelectronics package shown in FIG. 4 with the lid removed taken along line 6-6 in FIG. 5;
  • FIG . 7 is a perspective view of a ceramic circuit substrate for use in a microelectronics package with CPW transmission lines in accordance with a second embodiment of the present invention, wherein each CPW transmission line includes a signal trace and flanking ground planes;
  • FIG. 8 is a perspective view of a ceramic circuit substrate for use in a microelectronics package with CPW transmission lines in accordance with a third embodiment of the present invention, wherein each CPW transmission line includes a signal trace and flanking ground traces, and each ground trace is electrically connected to the package base by a conductive via opening;
  • FIG. 9A is a perspective view of a ceramic circuit substrate for use in a microelectronics package with CPW transmission lines in accordance with a fourth embodiment of the present invention, wherein each CPW transmission line includes a signal trace and flanking ground traces deposited on the substrate, and the substrate has "ears" cut into its outer perimeter to allow wire bonding of the ground traces to the base of the package;
  • FIG. 9B is a magnified view showing the substrate of FIG. 9A, after assembly to the base, and also showing bonding wires passing through the ears at the substrate's perimeter to bond the ground traces to the base;
  • FIG. 1 0 is an exploded view of a microelectronics package with CPW transmission lines for use as an electronic interconnect housing for a high- frequency electronic device in accordance with a sixth embodiment of the present invention which includes a sealing cap;
  • FIG. 1 1 is a top view of the microelectronics package shown in FIG.
  • FIG . 1 2 is a cross-sectional view of the microelectronics package shown in FIG . 1 0 taken along line 1 2- 1 2 in FIG . 1 1 .
  • a ceramic microelectronics package 200 in accordance with a first embodiment of the present invention includes a base 1 02, first attaching means 1 04, a ceramic radio-frequency (RF) circuit substrate 1 06, second attaching means 1 08, a ceramic seal ring substrate 1 1 0, non-conducting third attaching means 1 1 2, and a ceramic lid 1 1 4.
  • Package 200 is used as an electronic interconnect housing for a high- frequency (i.e., beyond 20 GHz) electronic device or component 1 1 6 mounted to base 1 02.
  • Device 1 1 6 is received within a cavity 1 20 formed within circuit substrate 1 06.
  • Seal ring substrate 1 1 0 has a cavity 1 24 larger than cavity 1 20.
  • Device 1 1 6 is an exemplary high-frequency electronic device housed within package 200, and it is understood that device 1 1 6 represents any high-frequency electronic device or component. Thus, package 200 includes some of the same components as package 1 00. A comparison between package 1 00 (FIGs. 1 -3) and package 200
  • FIGs. 4-6 reveals that conductive traces 1 22 formed on the top surface of ceramic circuit substrate 1 06 in package 1 00 are replaced by a plurality of conductive patterns 202 and 204 formed on the top surface of circuit substrate 1 06 in package 200.
  • Patterns 202 are conductive signal patterns or traces for providing electrical connections between the electrical signals on device 1 1 6 and an external device.
  • FIGs. 4-6 show four signal patterns 202 extending from the four sides of device 1 1 6 for electrically connecting device 1 1 6 to the external device.
  • Patterns 204 are conductive ground patterns, traces, or rails for connection to electrical ground. Patterns 204 are arranged on ceramic circuit substrate 1 06 such that each signal pattern 202 is flanked by a pair of ground patterns 204. Signal patterns 202 and flanking ground patterns 204 are co-planar with each other and with the top surface of ceramic circuit substrate 1 06 since they are formed on the top surface of substrate 1 06.
  • Base 1 02 has multiple uses, including providing a mechanical mount for package 200 onto a circuit board or carrier (not shown), a thermal and electrical mount for high-frequency electronic device 1 1 6 to be housed in the package, and as an electrical ground reference (i.e., "ground plane"), for the high frequency conductors and other signal traces used as the interconnect.
  • base 102 can be made from either of two different types of materials.
  • base 1 02 can be made of a conductive metal, such as Kovar ® , Invar ® , copper, copper-tungsten, copper-molybdenum, or molybdenum.
  • Each metal offers advantages in electrical and thermal conductivity, structural strength, low coefficient of thermal expansion, and compatibility to electroplated conductors (for example, nickel, silver, silver- platinum, silver-palladium, or gold).
  • electroplated conductors for example, nickel, silver, silver- platinum, silver-palladium, or gold.
  • the choice of these metals is only exemplary, and one skilled in the art will recognize that other metals can be used for base 1 02.
  • Base 1 02 can alternatively be made from a ceramic material, compatible with the remainder of the materials used in package 200. Use of such a ceramic base, however, requires some form of metallization to be applied to certain areas, such as the die attach area for device mounting, for the ground connection, or the bottom of base 1 02 for attaching package 200 to a circuit board or carrier. Examples of such ceramic material are aluminum oxide, aluminum nitride, beryllium oxide, fosterite, cordierite, quartz, fused silica, or other ceramics that would have a composition making them usable as a packaging material. Other ceramic materials not enumerated herein, but providing acceptable electrical and physical properties, can be used and would be known to those skilled in the art.
  • Attaching means 1 04 comprises some form of adhesive material which will differ depending on whether base 1 02 is metal or ceramic.
  • a metallic solder made from some composition providing good adhesion between metals would be applied either to the top surface of base 1 02 or the bottom surface of circuit substrate 106.
  • An example of such a composition would be gold-germanium or gold-tin composite, although other suitable compositions will be apparent to those skilled in the art.
  • circuit substrate 1 06 is made of a ceramic material, such as one of the ceramic materials enumerated above with respect to base 1 02.
  • Circuit substrate 1 06 has cavity area 1 20 cut out of it such that, when attached to base 1 02, the circuit substrate and base together provide a planar interconnect for device 1 1 6 or devices mounted on the base.
  • circuit substrate 106 has conductive patterns 202 and 204 deposited on its surface to form conductive signal and ground patterns as described above. The design of the specific shapes used for patterns 202 and 204 can be accomplished through the use of various electrical modeling and simulation software tools, as well as through experimentation. As described above with respect to attaching means 1 04, depending on the material chosen for base 1 02, the bottom surface of circuit substrate 1 06 may have metallization applied to it in order to attach the circuit substrate to the base.
  • Second attaching means 1 08 is a glass material (e.g., seal glass) deposited on either or both circuit substrate 1 06 and seal ring substrate 1 1 0. If seal glass is to be deposited on circuit substrate 1 06, it is formed such that the dimensions of the glass deposited on the circuit substrate will substantially match those of the seal ring substrate.
  • seal glass e.g., seal glass
  • Seal ring substrate 1 1 0 is made of the same or similar material as that used for circuit substrate 1 06. As described above for second attaching means 1 08, if seal glass is to be deposited on seal ring substrate 1 1 0, it is applied to the bottom surface of the seal ring substrate, which, when fused to circuit substrate 1 06 or to glass deposited on circuit substrate 1 06, creates a hermetic seal between the two substrates. To attain the proper hermeticity and lamination of seal ring substrate 1 1 0 and circuit substrate 1 06, when fusing the two substrates together by firing the seal glass, they can be weighted. Cavity 1 24 is formed in seal ring substrate 1 1 0 which is larger than cavity 1 20 formed in circuit substrate 106. This can be seen in the overhead view provided by FIG.
  • Seal ring substrate cavity 1 24 is made larger so that a portion of each conductive signal pattern 202 and ground pattern 204 is exposed inside cavity 1 24, as shown in FIG. 5.
  • the outer dimensions of seal ring substrate 1 1 0 vary to expose a portion of each conductive signal pattern 202 and ground pattern 204 on the outside of package 200, as also shown in FIG. 3.
  • These exposed portions of signal patterns 202 are used as connection points for electronic device 1 1 6 housed inside package 200 to the next component external to the package, and the exposed portions of ground patterns 204 are used as connection points to externally connect ground patterns 204 to electrical ground, or to the ground conductors of CPW transmission lines of the next external component.
  • ceramic lid 1 1 4 may be made of the same or a similar material as that used for circuit substrate 1 06 and/or seal ring substrate 1 1 0.
  • Third attaching means 1 1 2 a non-conductive polymer adhesive (e.g., epoxy) is affixed to the bottom of ceramic lid 1 1 4 in a window frame fashion to adhere ceramic lid 1 1 4 to seal ring substrate 1 1 0.
  • third attaching means 1 1 2 may be a low-temperature seal glass.
  • Either the bottom or top surface of ceramic lid 1 1 4 may be coated with a material that reduces cavity resonances.
  • Package 200 transmits and receives electrical signals with minimal loss and uses a minimal amount of conductive and non-conductive materials.
  • the package also eliminates the need for a stripline type of transmission line through a ceramic wall, as is used in some related packages.
  • the package construction is not limited to a single material combination, but can use a variety of materials, both conductive and dielectric, to produce a package suitable for high-frequency electronic devices.
  • the inventive package 200 satisfies the requirements for a microelectronics package suitable for high-frequency electronic devices, using a minimum of conductive materials.
  • the package satisfies the structural requirements of resistance to thermal and mechanical shock, moisture, salt atmosphere, vibration, and acceleration, as well as having the characteristic of solderability.
  • the package also satisfies several electrical requirements, including low parasitic effects (i.e., inductance and capacitance), minimal discontinuity reactances, low dissipation loss, and minimal interaction with surrounding devices and environment.
  • an impedance match low-loss interconnect for the device to the outside of the package is required.
  • Such an interconnect minimizes or eliminates the need for tuning the device for optimal performance.
  • a package must have low insertion loss (less than 0.02 f(GHz) dB and high return loss (greater than 1 5 dB) over the operating frequency band.
  • the feed-through structure should be planar, provide a good match for the electrical and magnetic fields at all interfaces, have a minimum number of transitions along the signal path, have a minimum number of discontinuities in the ground path, have a minimum feed-through length (but long enough to reduce interaction between discontinuities), and have minimum ground inductance.
  • Each conductive signal pattern 202 and flanking ground patterns 204 forms a portion of a CPW transmission line.
  • CPW transmission line is defined herein as being a conductor flanked by two ground patterns (e.g., traces, rails or planes) and separated from the flanking ground patterns by a dielectric. Such a CPW transmission line forms a regular CPW transmission line when located above a ground plane, and forms a suspended CPW transmission line when not located above a ground plane.
  • Each signal pattern 202 is a conductor flanked by a pair of ground patterns 204, and patterns 202 and 204 are separated by circuit substrate 1 06.
  • each signal pattern 202 and flanking ground patterns 204 forms a portion of a CPW transmission line which propagates a signal between the external device and device 1 1 6 as electric and magnetic fields.
  • the transmission lines in package 200 are regular CPW transmission lines since patterns 202 and 204 are located above a ground plane formed by conductive base 1 02.
  • Each CPW transmission line in package 200 has the form of a CPW, embedded CPW, CPW transmission line as the line transitions from outside package 200, beneath seal ring substrate 1 1 0, to inside package 200.
  • "Embedded CPW transmission line” is defined herein as being a CPW transmission line embedded beneath a second dielectric.
  • each CPW transmission line passing beneath substrate 1 1 0 has the form of an embedded CPW transmission line, and the portions of each CPW transmission line on either side of substrate 1 1 0 (i.e., not beneath substrate 1 1 0) have the form of regular CPW transmission lines.
  • the CPW transmission lines in package 200 including signal patterns
  • Feed-through is defined herein as an area having different dielectric surroundings through which a conductor passes.
  • seal ring substrate 1 1 0 causes the CPW transmission lines to pass through such an area.
  • the feed-throughs of package 200 can be referred to as CPW feed-throughs.
  • Another aspect of the present invention is a process for assembling a microelectronic package.
  • the process includes the following steps: Screen printing patterns of conductive paste on the top surface of the circuit substrate; drying and firing the conductive paste; etching to further define the conductive patterns in the conductive paste; screen printing a first seal glass layer on the top surface of the circuit substrate; drying and glazing the first seal glass layer; screen printing a second seal glass layer on the bottom surface of the seal ring substrate; drying and glazing the second seal glass layer; assembling the circuit substrate to the seal ring substrate; and attaching the top surface of the base to the bottom surface of the circuit substrate.
  • fully fired (i.e. , hardened) ceramics are selected for circuit substrate 1 06, ceramic seal ring substrate 1 1 0, and ceramic lid 1 1 4.
  • the same ceramic is selected for each component.
  • base 1 02 if it is made of a ceramic, it could be the same fully fired ceramic selected for the other components, or it could be a different ceramic material which is compatible with circuit substrate 1 06 but may have either better electrical or thermal properties.
  • any of the ceramic substrates may be alumina (Al 2 0 3 ) of various purities (e.g., 96%, 99.6%), berrylia (BeO), Barium Titanate (BaTi0 3 ), fused silica (Si0 2 ), or aluminum nitride (AIN), the material being selected to meet the specialized requirements of the product to be assembled.
  • alumina Al 2 0 3
  • purities e.g., 96%, 99.6%
  • BeO berrylia
  • BaTi0 3 Barium Titanate
  • Si0 2 fused silica
  • aluminum nitride and berrylia are desirable for high power, heat dissipative applications.
  • Circuit substrate 1 06 preferably 96% pure alumina, is fabricated as follows. Circuit substrate 1 06 is cleaned ultrasonically using a detergent suitable for electronic applications and rinsed with deionized water, then fired to burn out any residues from the detergent. Preferably, an Alconox detergent is used, although those skilled in the art will recognize that other detergents can be used. Next, a conductive paste is screen printed over the top surface of the circuit substrate 106.
  • a first method of defining the conductive patterns or traces is to provide preliminary conductive patterns which have significantly larger dimensions than the desired final dimensions of conductive patterns 202 and 204. Those skilled in the art will recognize that thin film techniques may also be used to deposit the conductive patterns. The photolithography/etch sequence described below will then be used to define the final dimensions of the conductive patterns.
  • a second possible method is to screen print the conductive paste using a screen that provides the actual final dimensions of the conductive patterns 202 and 204. If the second method is selected, no etch step is required.
  • the method of forming the preliminary conductive patterns uses thick film screen printing techniques, as are known in the art. Depending on the application and the type of conductor used, it may be desirable to repeat the printing sequence at least once to attain greater thickness and more uniform density of material, with each printing step being followed by drying and firing steps.
  • the firing temperature, time, and conditions depend on the type of conductive material used, the appropriate parameters being provided by the supplier of the conductive paste. Preferably, the printing, drying, and firing steps will be performed twice in the present invention.
  • the second method for defining the conductive patterns 202 and 204 requires similar processing after the conductive paste is printed onto circuit substrate 1 06.
  • a large number of conductive pastes are available, and the selection of such a paste will depend upon the product being fabricated. Many pastes are combinations of gold and glass, with variations in the mixtures providing various levels of hermeticity, wire bondability, solderability, etchability, and adhesion. Other possible pastes include silver or copper. Selection of the appropriate paste for the desired product quality falls within the level of skill in the art. Preferably, however, an etchable gold conductor is used in the present invention, and the preferred embodiment is described accordingly. When preliminary conductive patterns with dimensions larger than the desired final dimensions are in place on circuit substrate 1 06, a photolithographic process is used to more precisely define the dimensions of the conductors after which an etch is performed to remove the excess conductive material.
  • This patterning step follows the process as is known in thin film technology in which a photoresist (PR) layer is spun or otherwise coated onto the surface of the preliminary conductive patterns; the PR is exposed to ultraviolet light modulated by a mask bearing the desired patterns; and the unexposed PR is rinsed away using a developer, leaving the areas to be etched exposed.
  • the etch solution which is used for gold conductors is a mixture of potassium-iodine and iodine. After etching, the PR is stripped, and a clean/fire step is performed to burn away any chemical or organic residues remaining after the etching step.
  • seal glass is screen printed on the top surface of circuit substrate 1 06 to form second attaching means 108.
  • seal glass may be deposited on either or both of seal ring substrate 1 1 0 and circuit substrate 106. If seal glass is to be deposited on the top surface of circuit substrate 1 06, it will substantially match the dimensions of seal ring substrate 1 1 0, which has a larger cavity 1 24 than the cavity 1 20 of circuit substrate 1 06. Thus, the seal glass will not completely cover the top surface of circuit substrate 106.
  • seal glass may be done in order to obtain the desired total thickness, with the preferred embodiment including three such printing steps.
  • the seal glass paste is dried and glazed.
  • a seal glass may be printed onto the bottom surface of circuit substrate 1 06 if the base is ceramic.
  • the bottom surface of circuit substrate 1 06 may be metallized or may have a seal glass layer placed on it.
  • the glazing temperature is selected to be high enough that volatile materials (organics) within the glass are burned off, but not so high that the conductor on the substrates will melt or flow. The temperature depends on the type of material used, and appropriate temperature ranges are provided by the glass manufacturer.
  • the selection of the seal glass is dominated by the type of product to be fabricated.
  • the seal glass is selected to have a coefficient of thermal expansion (CTE) and dielectric constant that match as close as possible the CTE and dielectric constant of the ceramic selected for the substrates. Matching of the CTEs eliminates differential thermal stress between each layer of a multilayer structure.
  • seal ring substrate 1 1 0 is fabricated. As with circuit substrate 1 06, a ceramic material is selected which is fully fired and thus already hardened, the preferred ceramic being 96% pure alumina. The ceramic is the same as that selected for circuit substrate 1 06.
  • seal ring substrate 1 1 0 is cut to create cavity 1 24 at its center. This machining is generally performed by laser ablation using a C0 2 laser, which is the industry standard machining technique. Other machining techniques that may be used are ultrasonic machining or wire cutting. Other types of lasers may be used as well. Cavity 1 24 cut into seal ring substrate 1 1 0 is larger than the corresponding cavity 1 20 that will be cut into circuit substrate 1 06, as is apparent from the drawings. The resulting ceramic seal ring substrate 1 1 0 may then be mechanically scrubbed to remove any laser slag that may have built up on the substrate.
  • seal ring substrate 1 1 0 is cleaned ultrasonically using a detergent, preferably Alconox, and fired to burn off any residues from the detergent.
  • a detergent preferably Alconox
  • second attaching means 1 08 may be formed by deposition of seal glass on one or both of circuit substrate 1 06 and seal ring substrate 1 1 0, the following step is incorporated only if seal glass is to be deposited on the bottom surface of seal ring substrate 1 10.
  • a seal glass layer is applied to the bottom surface of seal ring substrate 1 1 0.
  • application of the seal glass layer requires screen printing, drying and glazing, which steps may be performed a number of times, depending on the materials used, to attain the desired thickness.
  • circuit substrate 1 06 and seal ring substrate 1 1 the two substrates are subassembled, requiring several steps. First, substrates 1 06 and 1 10 are aligned and mated for proper assembly, then the subassembly is fired, during which it may be weighted or clamped together to promote proper lamination and hermeticity between the two substrates. After firing, it may be desirable to check the hermeticity of the seal. The subassembly may be cleaned and inspected, then laser machined to create center cavity 1 20 in circuit substrate 1 06, after which it is inspected again. The laser slag is removed by scrubbing.
  • the subassembly is cleaned ultrasonically using a detergent, preferably 1 1 1 - trichloroethylene, to remove any grease and is rinsed with deionized water. The subassembly is then fired to burn away any residues left from the detergent.
  • a conductive paste is applied to the bottom surface of the subassembly (i.e., the bottom surface of circuit substrate 1 06), and the screen printed conductive paste is then dried and fired, as described above.
  • the preferred conductive paste is a gold paste, and the print-dry-fire step can be performed multiple times to achieve the desired thickness.
  • the subassembly may be singulated by sawing; that is, each independent subassembly separated from the blank.
  • base 1 02 is made from Kovar ® .
  • a hermeticity check may be performed on the subassembly before final assembly; and the subassembly may be cleaned and fired as necessary.
  • the bottom surface of circuit substrate 1 06 may be smoothed in order to prepare the subassembly for soldering. Preparation techniques may vary, depending on the type of solder used. These techniques may affect the amount of solder flow, hermeticity, and visual quality of the assembly.
  • base 1 02 and the subassembly are fitted together with attaching means 1 04 therebetween, and the fitted assembly is fired.
  • a final hermeticity check may be run; the assembly may be cleaned using an acetone or other detergent to remove grease and other residues; and electrical testing may be performed on sample packages.
  • the microelectronic circuit 1 1 6 to be packaged therein is attached using die attach techniques as known in the art.
  • Ceramic lid 1 1 4 is then attached to the top surface of seal ring substrate 1 1 0 by a non-conductive polymer adhesive 1 1 2, such as epoxy, or a seal glass which can be fired and glazed at a sufficiently low temperature to avoid damaging microelectronic circuit 1 1 6.
  • the process for using a non- conductive polymer adhesive 1 1 2 comprises screen printing the polymer onto the bottom surface of lid 1 1 4, then pre-baking lid 1 1 4 to partially cure the adhesive.
  • lid 1 1 4 is aligned with seal ring substrate 1 1 0 and then clamped in place, after which a final cure is performed at a temperature low enough to avoid damage to microelectronic circuit 1 1 6.
  • the signal leads of circuit 1 1 6 may then be attached to conductive signal patterns 202 by wire bonds.
  • Ceramic circuit substrate 300 for use in a microelectronics package in accordance with a second embodiment of the present invention is shown.
  • Ceramic circuit substrate 300 is the same as substrate 1 06 in the first embodiment, except for the shapes of conductive patterns deposited on the top surface of the substrate using the same process as described above. These patterns include conductive signal traces 302, each flanked by a pair of conductive ground planes 304. Each ground plane 304 is adjacent to a pair of signal traces 302, and is common to the pair of traces 302. Ground planes 304 can be referred to as continuous ground planes and, as would be apparent to a person of skill in the art, they can provide enhanced electrical noise suppression on signal traces 302.
  • the remaining layers in the microelectronics package, and the process for making them, are the same as described above in relation to the first embodiment.
  • FIGs. 8 and 9 show third and fourth embodiments of the present invention which use internal grounding connections for enhanced grounding.
  • FIG. 8 a ceramic circuit substrate 400 for use in a microelectronics package in accordance with a third embodiment of the present invention is shown.
  • Ceramic circuit substrate 400 is the same as substrate 1 06 in the first embodiment, except that each conductive ground pattern 204 has a conductive via opening 402 formed therein.
  • Via openings 402 are electrically connected to conductive base 1 02.
  • FIG. 8 shows one via opening 402 formed near the end of each ground pattern 204 near the outer perimeter of substrate 400.
  • via openings 402 may also be formed on patterns 204 at other locations (e.g., the middle of each pattern 204, or near the inner perimeter of substrate 400 adjacent cavity 1 20) .
  • each ground pattern 204 could include more than one via opening, and substrate 400 may also include external ground connections as used by the first embodiment.
  • Via openings 402 may also be used to connect ground planes 304 (FIG. 7) to conductive base 1 02.
  • Via openings 402 may be formed by machining ceramic circuit substrate 400. This machining is generally performed by laser ablation using, for example, a C0 2 laser, which is an industry standard machining technique. Other machining techniques may also be used, such as ultrasonic machining or other types of lasers. Laser slag that may build up around the machined area is removed by mechanically scrubbing or scraping substrate 400. Electrical connections between ground patterns 204 and base 1 02 are provided by filling or coating via openings 402 with a metallic conductor. First, a dielectric paste is screen printed over the top surface of substrate 400, with a pattern corresponding to the locations of the via openings. A high volume vacuum can be applied to the bottom surface of substrate 400 to help the paste flow into via openings 402.
  • the paste is then dried. Any excess paste remaining on the top and bottom surfaces of substrate 400 may be removed by scraping the surfaces, and wiping the surfaces with a lint-free cloth dampened with a solvent. All remaining paste is located within via openings 402 to coat the sidewalls, with the vias remaining open. Substrate 400 is then fired according to the specifications provided by the manufacturer of the dielectric paste.
  • the glass via coating helps to strengthen any microcracks that may have formed around openings 402 during machining and assists in adhesion of a gold conductor.
  • the glass coated sidewalls are then coated with the gold conductor by screen printing a gold paste using the same screen pattern as was used for the dielectric paste.
  • the gold paste is pulled into the openings and dried, with excess paste being removed from the surfaces by scraping and wiping the surfaces.
  • the only remaining gold paste is then in the via openings. Again, the vias should remain open following this step.
  • the via openings are then filled with a gold conductor by screen printing a gold paste over the top surface of substrate 400 using a dry/scrape/wipe process to fill the via openings while removing all paste from the surfaces.
  • the printing sequence can be repeated to thicken the conductive layer within the via openings, with the gold paste being fired following each printing sequence.
  • the sequence can be repeated until the conductive coating reaches a desired thickness, or until the via opening is filled with conductor.
  • the process of forming conductive via openings is generally known in the art, and other alternatives are available.
  • the remaining layers in the microelectronics package, and the process for making them, are the same as described above in relation to the first embodiment. Referring to FIG. 9A-9B, a ceramic circuit substrate 500 for use in a microelectronics package in accordance with a fourth embodiment of the present invention is shown.
  • Substrate 500 is the same as substrate 1 06 in the first embodiment, except that an aperture or "ear” 502 has been cut into substrate 500 proximate to each ground pattern 204.
  • FIG . 9A-9B shows ears 502 cut at the outer perimeter of substrate 500. Alternatively, ears 502 could be cut into substrate 500 at its inner perimeter surrounding cavity 1 20. As shown in the magnified view of FIG. 9B, ears 502 provide apertures for bonding wires 504 or ribbons, to pass through. Wires 504 internally connect ground patterns 204 to conductive base 1 02. Bonding wires 504 are attached to patterns 204 and base 1 02 after substrate 500 is attached to base 1 02 by the above-described process. Ears 502 are also formed by machining ceramic circuit substrate 500 as described above.
  • a ceramic microelectronics package with CPW transmission lines in accordance with a fifth embodiment of the invention appears as shown in FIGs. 4-6, except that base 1 02 is made from a non-conductive or dielectric material such as ceramic.
  • base 1 02 is made from a non-conductive or dielectric material such as ceramic.
  • substrate 106 is made of alumina
  • base 1 02 is made of alumina or beryllia. Since the CPW transmission line formed by each conductive signal pattern 202 flanked by two ground patterns 204 is no longer located above a ground plane, the CPW transmission lines of the fifth embodiment are suspended CPW transmission lines. Similarly, if base 1 02 of the second embodiment of the present invention shown in FIG. 7 were made of a non-conductive material, then the CPW transmission lines would also be suspended CPW transmission lines.
  • FIGs. 1 0-1 2 a ceramic microelectronics package 600 in accordance with a sixth embodiment of the present invention is shown.
  • Package 600 includes a base 1 02, attaching means 1 04, an RF circuit substrate 1 06 with conductive signal patterns 202 and ground patterns 204 formed thereon, second attaching means 602, and a sealing cap 604. Patterns 202 and 204 are the same as in package 200. Package 600 is also used as an electronic interconnect housing for high-frequency devices.
  • Base 1 02 has multiple uses, including providing a mechanical mount for package 600 onto a circuit board or carrier (not shown), a thermal and electrical mount for high-frequency electronic device 1 1 6 to be housed in the package, and as a ground reference for high-frequency conductive patterns 202 and 204 and other signal traces used as the interconnect.
  • base 1 02 can be made from either of two different types of materials.
  • the base can be made of a conductive metal, such as Kovar ® , Invar ® , copper, cold rolled steel, copper-tungsten, copper- molybdenum, and molybdenum.
  • base 1 02 may be made of several low expansion iron-nickel alloys, having a nickel content ranging from 42-52%, with the balance being predominantly iron.
  • One such alloy is identified as Alloy 46, which consists of a combination of 46% nickel with the balance predominantly iron, and is available in commercial quantities from several sources, including National Electronic Alloys of Oakland, New Jersey. Specifications for the metallurgical properties of Alloy 46 are found in American Society for Test Methods (ASTM) Publication F30. Alloy 46 is a prime material for a low cost package 600, ideal for lower power devices where thermal dissipation is not a significant requirement. The choice of these metals is only exemplary, and one skilled in the art will recognize that other metals can be used.
  • Base 1 02 can alternatively be made from a ceramic material, compatible with the remainder of the materials used in package 600. Use of such a ceramic base, however, requires some form of metallization to be applied to certain areas, such as the die attach area for device mounting, for the ground connection, or the bottom surface of base 1 02 for attaching package 600 to a circuit board or carrier. Examples of such ceramic material are aluminum oxide, aluminum nitride, beryllium oxide, fosterite, cordierite, quartz, fused silica, or other ceramics that would have a composition making them usable as a packaging material. Other ceramic materials not enumerated herein, but providing acceptable electrical and physical properties, can be used and would be known to those skilled in the art.
  • Attaching means 104 comprises an adhesive material which may differ depending on whether base 1 02 is metal or ceramic.
  • a metallic solder made from a composition providing good adhesion between metals would be applied either to the top surface of base 1 02 or the bottom surface of RF circuit substrate 106.
  • An example of such a composition would be copper-silver joining alloy, although other suitable composites will be apparent to those skilled in the art.
  • a variety of attaching materials may be used. Specifically, the ceramic base may be attached with the same options set out above for use with a metal base. Any preparation of the ceramic base for attachment is obvious to those skilled in the art. For example, if the ceramic base is to be attached with metal solder, the base must be metallized so that the solder will adhere. As an alternative to solder, a glass material, e.g., seal glass, could be applied between base 1 02 and RF circuit substrate 1 06 in order to adhere the base to substrate 1 06.
  • solder a glass material, e.g., seal glass, could be applied between base 1 02 and RF circuit substrate 1 06 in order to adhere the base to substrate 1 06.
  • Organic adhesives are an ideal low cost alternative as its use eliminates several process steps and many expensive materials listed above. For example, even if metallization of the ceramic base is required for electrical considerations, use of the organic adhesives eliminate the need to prepare the bottom surface of RF circuit substrate 1 06 for attachment to base 1 02.
  • organic adhesives may include metal filled adhesives such as conductive polymers for higher frequency applications, polyimide, polyvinyl acetate, polyvinyl alcohol, acrylic, phenolic, phenol-resorcinol, epoxy, urea formaldehyde, melamine, alkyd, phenolic-vinyl, phenolic-polyvinyl butyrate, phenolic-nylon, and phenolic neoprene.
  • metal filled adhesives such as conductive polymers for higher frequency applications, polyimide, polyvinyl acetate, polyvinyl alcohol, acrylic, phenolic, phenol-resorcinol, epoxy, urea formaldehyde, melamine, alkyd, phenolic-vinyl, phenolic-polyvinyl butyrate, phenolic-nylon, and phenolic neoprene.
  • metal filled adhesives such as conductive polymers for higher frequency applications, polyimide, polyvinyl acetate, polyvinyl
  • RF circuit substrate 1 06 may be made of a ceramic material, such as one of the ceramic materials enumerated above with respect to base 1 02. Additionally, substrate 1 06 may also be made from a number of other dielectrics including teflon, glass, low cost electronic grade ceramic, and several plastics, depending on the electrical requirements. More specifically, the glass dielectric materials suitable for substrate 1 06 include soda lime (float or lamp bulb), alumina silicate, borosilicate (low loss electrical) 99.5% silica for high temperatures. Further, the plastic dielectric materials may be filled or unfilled. The filler could be in the form of a glass matt (for example, G 1 0 printed circuit board material).
  • the ceramics listed above could be used in powdered form as an amorphous filler in the plastic.
  • the plastics could include any of those commonly used in electrical applications, such as epoxy molding compounds and thermoset molding compounds. Specific choices for such plastics include nylon, resins, novalacks, phenolics, polysulfones, polyetherimides, and liquid crystal plastics. Those skilled in the art will recognize that any plastic which provides acceptable electrical and physical properties can also be used.
  • RF circuit substrate 1 06 has a cavity area 1 20 cut out of it such that, when attached to base 1 02, the substrate and base together provide a planar interconnect for high-frequency electronic device 1 1 6 or devices mounted on the base. Moreover, substrate 1 06 has a number of conductive patterns 202 and 204 deposited on its surface. Patterns 202 and 204 have a specific shape designed to maintain a uniform characteristic impedance from end to end of the conductor. This is done through use of various electrical modeling and simulation software tools, as well as through experimentation. As described above with respect to attaching means 1 04, depending on the material chosen for base 1 02, the bottom surface of substrate 1 06 may have metallization applied to it in order to attach the substrate to the base.
  • Second attaching means 602 for the sixth embodiment is an epoxy deposited on either or both RF circuit substrate 1 06 and sealing cap 604. If epoxy is to be deposited on substrate 1 06, it is formed so that the dimensions of the epoxy deposited on the substrate will substantially match those of sealing cap 604.
  • Sealing cap 604 may be made of the same or similar material as that used on RF circuit substrate 1 06. More specifically, sealing cap 604 can be made from a number of dielectric materials including teflon, glass, low cost electronic grade ceramic, and several plastics, depending on the electrical requirements.
  • the glass dielectric materials may include soda lime (float or lamp bulb), alumina silicate, borosilicate (low loss electrical) 99.5% silica for high temperatures.
  • the plastic dielectric materials may be filled or unfilled.
  • the filler could be in the form of a glass matt (e.g., G 1 0 printed circuit board material) .
  • the ceramics listed above could be used in powdered form as an amorphous filler in the plastic.
  • the plastics could include any of those commonly used in electrical applications, such as epoxy molding compounds and thermoset molding compounds. Specific choices for such plastics include nylon, resins, novalacks, phenolics, polysulfones, polyetherimides, and liquid crystal plastics. It is to be appreciated, however, that those skilled in the art will recognize that any plastic which provides acceptable electrical and physical properties can also be used.
  • sealing cap 604 As described above for second attaching means 602, if seal glass is to be deposited on sealing cap 604, it is applied to the bottom surface of the sealing cap, which, when fused to RF circuit substrate 106 or to glass deposited on substrate 1 06, creates a hermetic seal between substrate 1 06 and sealing cap 604. To attain the proper hermeticity and lamination of sealing cap 604 and substrate 1 06, when fusing the two surfaces together by firing the seal glass, they can be weighted.
  • the outer dimensions of sealing cap 604 are selected so as to expose a portion of each conductive pattern 202 and 204 on the outside of package 600.
  • the exposed portions of signal patterns 202 are used as connection points for device 1 1 6 housed inside package 600 to the next component or trace external to package 600, and the exposed portions of ground patterns 204 are used as connection points to externally connect patterns 204 to electrical ground, or to the ground conductors of CPW transmission lines on the next external component.
  • ground patterns 204 on package 600 can be connected in the same way that signal patterns 202 are connected.
  • sealing cap 604 is formed with a chamber 606 having a larger diameter than cavity 1 20 formed in RF circuit substrate 1 06.
  • the process for assembling a microelectronic package in accordance with the sixth embodiment includes the steps of: screen printing conductive patterns 202 and 204 on RF circuit substrate 1 06; screen printing first attaching means 1 04 on the top surface of base 1 02; and attaching the top surface of base 1 02 to the bottom surface of substrate 1 06.
  • the material for RF circuit substrate 1 06 is selected. If substrate 1 06 is made of a ceramic material, it could be the same fully fired ceramic which may be selected for the other components.
  • any of the ceramic substrates may be alumina (AI 2 O 3 ) of various purities (e.g., 96%, 99.6%), berrylia (BeO), barium titanate (BaTi0 3 ), fused silica (Si0 2 ), or aluminum nitride (AIN), the material being selected to meet the specialized requirements of the product to be assembled, which will be within the level of skill in the art.
  • berrylia BeO
  • barium titanate BaTi0 3
  • fused silica Si0 2
  • aluminum nitride aluminum nitride
  • AIN aluminum nitride
  • RF circuit substrate 1 06 may be made from a number of dielectrics including teflon, glass, low cost electronic grade ceramic, and several plastics, depending on the electrical requirements.
  • soda lime float or lamp bulb
  • alumina silicate borosilicate
  • filled or unfilled plastics including nylon, resins, novalacks, phenolics, polysulfones, polyetherimides, and liquid crystal plastics.
  • RF circuit substrate 106 is cleaned ultrasonically using a detergent suitable for electronic applications and rinsed with deionized water, then fired to burn out any residues from the detergent.
  • a detergent suitable for electronic applications Preferably, an Alconox detergent is used, although other detergents can be used.
  • conductive patterns or traces 202 and 204 are formed on the top surface of RF circuit substrate 1 06.
  • Such patterns may be formed using a variety of methods.
  • One method of defining the patterns is to screen print preliminary conductive patterns using thick film screen printing techniques. The patterns would have significantly larger dimensions than the desired final dimensions of patterns 202 and 204.
  • a photolithographic process is used to more precisely define the dimensions of the patterns after which an etch is performed to remove excess conductive material.
  • This patterning step follows the process as is known in thin film technology in which a photoresist (PR) layer is spun or otherwise coated onto the surface of the preliminary conductive patterns; the PR is exposed to ultraviolet light modulated by a mask bearing the desired patterns; and the unexposed PR is rinsed away using a developer, leaving the areas to be etched exposed.
  • the RF circuit substrate is then immersed in an etch solution for etching.
  • This etch solution typically used for gold conductors, is a mixture of potassium- iodine and iodine.
  • the PR is stripped, and a clean/fire step is performed to burn away any chemical or organic residues remaining after the etching step.
  • This technique defines the ultimate dimensions of conductive patterns 202 and 204 to assure that all dimensions, including thickness, are uniform and within the tolerances desired for reliable operation.
  • Another possible method of defining conductive patterns 202 and 204 is to screen print the conductive paste using a screen that provides the actual final dimensions of the conductive patterns. This method does not require the use of an etching process. After the conductive paste is printed over the substrate, it is dried. RF circuit substrate 1 06 is then fired according to the specifications provided by the manufacturer of the paste.
  • Yet another possible method of defining the conductive patterns when ceramic is selected for RF circuit substrate 1 06 involves the application of metal foil directly on the surface of the ceramic.
  • metal foil may be directly bonded to alumina and other ceramics through a process known as direct bond copper. After bonding the copper foil to the ceramic, the copper foil may be etched using the photolithography/etch sequence as described below to define the final dimensions of the conductive patterns.
  • Another method of defining the conductive patterns, particularly useful for low-cost packages involves the implementation of the printed wiring board industry's method of printing a polymer thick film on a substrate. Using this approach, it is possible to incorporate a filled polymer substrate material, instead of alumina ceramic.
  • Substrates 106 may then be printed and/or etched with conductive patterns 202 and 204 for subsequent separation into single substrates.
  • the thick film printed on the polymer substrate may be repeatedly plated using electroplate or electrodeless plate techniques. For example, a high volume approach is to print a silver polymer thick film on a polymer substrate, followed by plated nickel, and plated gold.
  • Second attaching means 602 is screen printed on the top surface of RF circuit substrate 1 06.
  • Second attaching means 1 08 in the sixth embodiment consists of a non-conductive polymer adhesive, such as epoxy.
  • the epoxy may be deposited on either or both of sealing cap 604 and substrate 1 06. If epoxy is to be deposited on the top surface of substrate 106, it will substantially match the dimensions of sealing cap 604. Multiple printings of epoxy may be done to obtain the desired total thickness.
  • sealing cap 604 is fabricated. As discussed above, the sealing cap may be made from a number of dielectric materials including teflon, glass, low cost electronic grade ceramic, and several plastics, depending on the electrical requirements.
  • the glass dielectric materials include soda lime (float or lamp bulb), alumina silicate, borosilicate (low loss electrical) 99.5% silica for high temperatures.
  • the plastic dielectric materials may be filled or unfilled.
  • the filler could be in the form of a glass matt (for example, G 1 0 printed circuit board material) .
  • the ceramics listed above could be used in powdered form as an amorphous filler in the plastic.
  • the plastics could include any of those commonly used in electrical applications, such as epoxy molding compounds and thermoset molding compounds. Specific choices for such plastics include Nylon, resins, novalacks, phenolics, polysulfones, polyetherimides, and liquid crystal plastics. It is to be appreciated, however, that those skilled in the art will recognize that any plastic which provides acceptable electrical and physical properties can also be used.
  • base 1 02 is selected from the materials listed above.
  • base 1 02 is preferably made of Alloy 52.
  • a hermeticity check may be performed on the subassembly before final assembly; and the subassembly may be cleaned and fired as necessary.
  • the bottom surface of the substrate may be smoothed to facilitate the attachment. Preparation techniques may vary, depending on the type of base material used.
  • attaching means 1 04 for the sixth embodiment is an organic adhesive.
  • Such adhesive is, perhaps, a more simple method of attaching substrate 1 06 to base 1 02. However, any of the adhesives discussed above will retain substrate 1 06 and base 1 02 together.
  • the device 1 1 6 to be packaged therein is attached to substrate 1 06 using die attach techniques as are known in the art.
  • Sealing cap 604 is then sealed to the upper surface of substrate 106 by a non-conductive polymer adhesive 602, such as epoxy.
  • the process for using a non-conductive polymer adhesive 602 comprises screen printing the adhesive onto the bottom surface of sealing cap 604, then pre-baking the sealing cap to partially cure the adhesive.
  • sealing cap 604 is aligned with substrate 106. Sealing cap 604 is then clamped in place on the surface of substrate 1 06, after which a final cure is performed at a temperature low enough to avoid damage to microelectronic device 1 1 6.
  • flanking ground planes described in relation to the second embodiment may be electrically connected to the base of the package by conductive via openings as in the third embodiment, or by bonding wires passing through ears as in the fourth embodiment, and may form a portion of suspended CPW transmission lines as in the fifth embodiment.
  • flanking ground traces of the first embodiment or the flanking ground planes of the second embodiment may be electrically connected to ground by external connections, by conductive via openings to the package base as in the third embodiment, by bonding wires passing through ears as in the fourth embodiment, or by a combination of such external connections, via openings and bonding wires.

Abstract

A ceramic microelectronic package (200) suitable for housing high-frequency electronic devices, and a process for making such a package, are disclosed herein. The package includes a base (102), a ceramic circuit substrate (106) attached to a top surface of the base and having a first cavity for receiving a high-frequency electronic device (116), and conductive patterns (202) deposited on a surface of the circuit substrate. The patterns (204) include signal patterns and flanking ground patterns forming at least a portion of co-planar waveguide (CPW) transmission lines. Each signal pattern is preferably a signal trace, and each ground pattern may be a ground trace or plane. The ground patterns may each have a portion exposed outside the package for external connection to electrical ground. Alternately, the ground patterns may be internally connected to a ground plane formed by the base, when the base is at least partially conductive, by conductive via openings or bonding wires passing through ears cut into a perimeter of the circuit substrate. The base may also be non-conductive such that the transmission line is a suspended CPW transmission line. The package may include a ceramic seal ring (110) substrate attached to the circuit substrate and having a second cavity larger than the first cavity, and a ceramic lid (114) attached thereto such that the transmission line forms a CPW, embedded CPW, and CPW transmission line. Alternatively, the package may include a dielectric sealing cap attached to the circuit substrate and having a chamber larger than the first cavity such that the line again forms a CPW, embedded CPW, and CPW transmission line.

Description

CERAMIC MICROELECTRONICS PACKAGE WITH CO-PLANAR WAVEGUIDE FEED-THROUGH
RELATED APPLICATIONS This application is related to application S/N 08/231 ,492, now issued as U .S. Pat. No. 5,448,826, which was a divisional of application S/N 08/1 34,269, now issued as U.S. Pat. No. 5,465,008. This application is also related to application S/N 08/645,848, which was a continuation in part of application S/N 08/526,535, now issued as U.S. Pat. No. 5,692,298, which was a continuation of application S/N 08/1 34,269, now issued as U .S. Pat. No. 5,465,008. The subject matter of each of these related applications is incorporated herein by reference.
FIELD OF THE INVENTION The present invention generally relates to the field of microelectronic packages for high-frequency electronic devices, and specifically relates to a ceramic microelectronic package with co-planar waveguide feed-through for use as an electronic interconnect housing for a high-frequency electronic device.
BACKGROUND OF THE INVENTION A key requirement for the packaging of a microelectronic device is that signals move through the package's conductive interconnects such that the electrical interconnection causes minimal change in the signals. It is difficult, however, to fabricate microelectronic packages to achieve minimal signal change at higher frequencies, i.e., greater than 20 Gigahertz (GHz) . Along with limited frequency ranges, conventional microelectronic packages have excessive transmitted and reflective loss, limited input/output isolation, high cost, and limited reliability, resulting in a lack of general applicability. The above-listed related applications and patents disclose improved ceramic microelectronic packages that address one or more of the problems due to limitations and disadvantages of the related art. For example, U .S. Pat. No. 5,448,826 shows a ceramic microelectronics package 1 00 suitable for housing high-frequency electronic devices, as shown in FIGs. 1 -3 herein. Package 1 00 includes a base 1 02, first attaching means 1 04, a ceramic radio-frequency (RF) circuit substrate 1 06, second attaching means 1 08, a ceramic seal ring substrate 1 1 0, non-conducting third attaching means 1 1 2, and a ceramic lid 1 1 4. Package 1 00 is used as an electronic interconnect housing for a high-frequency (i.e., beyond 20 GHz) electronic device or component 1 1 6 mounted to base 1 02. Device 1 1 6 is received within a cavity 1 20 formed within circuit substrate 1 06. A plurality of conductive traces 1 22 patterned on circuit substrate 1 06 provide electrical connections between device 1 1 6 and an external device (not shown) . Seal ring substrate 1 1 0 has a cavity 1 24 larger than cavity 1 20. Device 1 1 6 is an exemplary high-frequency electronic device housed within package 1 00, and it is understood that device 1 1 6 represents any high-frequency electronic device or component. Package 1 00, and the process for making package 1 00, are fully disclosed in the '826 patent, which is incorporated herein by reference. Each conductive trace 1 22 in package 1 00 forms a portion of a microstrip transmission line. "Microstrip transmission line" is defined herein as being a conductor suspended above a ground plane and separated from the ground plane by a dielectric. Each conductive trace 1 22 is a conductor, base 1 02 forms a ground plane, ceramic circuit substrate 1 06 is a dielectric, and each trace 1 22 is suspended above base 1 02 and is separated from base 1 02 by substrate 1 06. Thus, each conductive trace 1 22 forms a portion of a microstrip transmission line which propagates a signal between the external device and device 1 1 6 as electric and magnetic fields. The impedance of microstrip transmission lines is a function of the dielectric value of substrate 1 06, the width of traces 1 22, the gap to the top surface of the ground plane formed by base 1 02, and the thickness of substrate 1 06 below traces 1 22. Mathematical formula are known which approximate the impedance for given dielectric and conductor parameters and geometries.
Each microstrip transmission line in package 1 00 has the form of a microstrip, embedded microstrip, microstrip transmission line as the line transitions from outside package 1 00, beneath seal ring substrate 1 1 0, to inside package 1 00. "Embedded microstrip transmission line" is defined herein as being a microstrip transmission line embedded beneath a second dielectric. Since ceramic circuit substrate 1 06 and seal ring substrate 1 1 0 are both dielectrics, the middle portion of each microstrip transmission line passing beneath seal ring substrate 1 1 0 has the form of an embedded microstrip transmission line, and the portions of each microstrip transmission line on either side of substrate 1 1 0 (i.e., not beneath substrate 1 1 0) have the form of regular (i.e., non-embedded) microstrip transmission lines.
The microstrip transmission lines in package 1 00, including conductive traces 1 22, transition through microstrip feed-throughs when entering and exiting the package. "Feed-through" is defined herein as an area having different dielectric surroundings through which a conductor passes. The presence of seal ring substrate 1 1 0 causes the microstrip transmission lines to pass through such an area as the transmission lines transition from outside package 1 00 to inside package 1 00. Thus, the feed-throughs of package 1 00 can be referred to as microstrip feed-throughs.
Although microelectronics package 1 00 has advantages over the related art, it can still be improved upon as shown by the present invention. First, to connect a testing instrument to conductive traces 1 22 and electrical ground, electrical testing probes for use with package 1 00 extend the signals on traces 1 22 along the plane of the package. Such probes are relatively difficult to design and are relatively unreliable. It would be desirable to provide a ceramic microelectronics package suitable for housing a high- frequency electronic device wherein testing probes can be connected vertically to the package with transmission lines extending upwardly from the package/device combination. Such probes would be easier to design and more reliable than probes extending the signals along the package plane.
Second, when package 1 00 houses a high-frequency gallium arsenide (GaAs) integrated circuit (IC) device having microstrip transmission lines, it can be difficult to maintain proper geometry when connecting the microstrip transmission lines of package 1 00 with the microstrip transmission lines of the GaAs device because the ground traces are not on the same plane as the signal traces. However, there are GaAs devices having co-planar waveguide (CPW) transmission lines thereon. Thus, it would be desirable to provide a ceramic microelectronics package suitable for housing a GaAs device wherein the transmission lines of the package are in the same plane as the CPW transmission lines of the GaAs device. This would make it easier to maintain proper geometry in the ground-signal-ground-portion of the device-to-package transition since much or all of the ground would be co-planar with the signal.
Third, it would be desirable to provide a ceramic microelectronics package suitable for housing a high-frequency electronic device wherein grounding is enhanced for relatively little or no incremental cost. In the fourth embodiment of the present invention, described below, this enhancement can be achieved by providing internal connections between ground traces deposited on the ceramic circuit substrate and the base of the package. These connections are made by wire or ribbon bonds passing through ears cut into the substrate. The incremental cost of these additional connections is small since bonds are already used to connect the electronic device to the package, or to connect the package to an external device.
Fourth, the composite or low-expansion metal base 1 02 of package 1 00 is a relatively expensive material which also limits the options available for the material used for attaching means 1 04, thereby increasing its cost. Base 102 also limits manufacturing process options since means 104 cannot be used while package 1 00 is under construction in the array form. It would be desirable to decrease the costs associated with base 1 02, including the costs of the materials used for base 1 02 and attaching means 1 04, and the impact of the limits imposed on the manufacturing process. These advantages are realized in the fifth embodiment of the present invention.
Fifth, the composite or low-expansion metal base 1 02 of package 1 00 also limits the frequency performance of package 1 00. With the microstrip transmission lines of package 1 00, higher frequencies can be achieved by decreasing the thickness of ceramic circuit substrate 1 06 and using correspondingly narrower conductive signal traces 1 22. However, thin ceramic layers can be difficult to reliably process. Practically, the thickness of ceramic circuit substrate 1 06 is limited to a minimum thickness of 0.01 0" . It would be desirable to provide a ceramic microelectronics package suitable for housing a high-frequency device wherein frequency performance is not limited by the practical limits on the thickness of the circuit substrate. This advantage is also realized in the fifth embodiment of the present invention.
BRIEF SUMMARY OF THE INVENTION It is an advantage of the present invention to provide an improved ceramic microelectronics package suitable for housing a high-frequency device which realizes the above-listed advantages. These advantages include being compatible with electrical testing probes which can connect vertically to the package with the transmission lines extending upwardly, having transmission lines in the same plane as the CPW transmission lines of certain GaAs devices, having enhanced grounding implemented at little or no incremental cost, having a base material made of a lower-cost material which can be attached using less expensive means and manufacturing process options, and providing improved frequency performance which is not limited by the thickness of the ceramic circuit substrate. Each of these advantages is realized by one or more embodiments of the present invention.
One embodiment of the present invention relates to a ceramic microelectronic package suitable for housing a high-frequency electronic device. The package includes a base, a ceramic circuit substrate attached to a top surface of the base and having a cavity for receiving the electronic device, and a plurality of conductive patterns deposited on a surface of the ceramic circuit substrate. The conductive patterns include at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a co-planar waveguide (CPW) transmission line. Another embodiment of the present invention relates to a ceramic microelectronic package suitable for housing a high-frequency electronic device. The package includes a base, a ceramic circuit substrate attached to a top surface of the base and having a first cavity for receiving the electronic device, and a plurality of conductive patterns deposited on a surface of the ceramic circuit substrate. The conductive patterns include at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a CPW transmission line. A ceramic seal ring substrate is attached to the ceramic circuit substrate and has a second cavity larger than the first cavity, and a ceramic lid is attached to the ceramic seal ring substrate. A middle portion of the CPW transmission line passes beneath the ceramic seal ring substrate such that the CPW transmission line forms a CPW, embedded CPW, and CPW transmission line.
Another embodiment of the invention relates to a microelectronic package suitable for housing a high-frequency electronic device. The package includes a base, an RF circuit substrate attached to a top surface of the base and having a cavity for receiving the electronic device, and a plurality of conductive patterns deposited on a surface of the RF circuit substrate. The conductive patterns include at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a CPW transmission line. A dielectric sealing cap is attached to the RF circuit substrate and has a chamber larger than the cavity of the RF circuit substrate. A middle portion of the CPW transmission line passes beneath the sealing cap such that the CPW transmission line forms a CPW, embedded CPW, and CPW transmission line.
Another embodiment of the present invention relates to a process for assembling a ceramic microelectronic package for retaining a high-frequency integrated circuit. The package has a base and a ceramic circuit substrate. The process includes depositing a plurality of conductive patterns on a top surface of the ceramic circuit substrate, the patterns including a plurality of conductive signal patterns and a plurality of conductive ground patterns, each of the conductive signal patterns being flanked by a pair of the conductive ground patterns to form at least a portion of a plurality of CPW transmission lines for providing electrical connections between the integrated circuit and an external device. The process also includes cutting a cavity having dimensions for receiving the integrated circuit into the ceramic circuit substrate, attaching a top surface of the base to a bottom surface of the ceramic surface substrate to form an assembly, and firing the assembly.
BRIEF DESCRIPTION OF THE DRAWINGS
Understanding of the present invention will be facilitated by consideration of the following detailed description of a preferred embodiment of the present invention, taken in conjunction with the accompanying drawings, in which like reference numerals refer to like parts and in which: FIG. 1 is an exploded view of a ceramic microelectronics package with microstrip transmission lines for use as an electronic interconnect housing for a high-frequency electronic device, the package of FIG. 1 being part of the background of the present invention;
FIG. 2 is a top view of the ceramic microelectronics package shown in FIG. 1 with the lid removed;
FIG . 3 is a cross-sectional view of the ceramic microelectronics package shown in FIG. 2 with the lid removed taken along line 3-3 in FIG. 2;
FIG. 4 is an exploded view of a ceramic microelectronics package with co-planar waveguide (CPW) transmission lines for use as an electronic interconnect housing for a high-frequency electronic device in accordance with a first embodiment of the present invention, wherein each CPW transmission line includes a signal trace and flanking ground traces, each ground trace having a portion exposed outside the package for external connection to electrical ground;
FIG . 5 is a top view of the ceramic microelectronics package shown in FIG. 4 with the lid removed;
FIG. 6 is a cross-sectional view of the ceramic microelectronics package shown in FIG. 4 with the lid removed taken along line 6-6 in FIG. 5;
FIG . 7 is a perspective view of a ceramic circuit substrate for use in a microelectronics package with CPW transmission lines in accordance with a second embodiment of the present invention, wherein each CPW transmission line includes a signal trace and flanking ground planes;
FIG. 8 is a perspective view of a ceramic circuit substrate for use in a microelectronics package with CPW transmission lines in accordance with a third embodiment of the present invention, wherein each CPW transmission line includes a signal trace and flanking ground traces, and each ground trace is electrically connected to the package base by a conductive via opening;
FIG. 9A is a perspective view of a ceramic circuit substrate for use in a microelectronics package with CPW transmission lines in accordance with a fourth embodiment of the present invention, wherein each CPW transmission line includes a signal trace and flanking ground traces deposited on the substrate, and the substrate has "ears" cut into its outer perimeter to allow wire bonding of the ground traces to the base of the package;
FIG. 9B is a magnified view showing the substrate of FIG. 9A, after assembly to the base, and also showing bonding wires passing through the ears at the substrate's perimeter to bond the ground traces to the base;
FIG. 1 0 is an exploded view of a microelectronics package with CPW transmission lines for use as an electronic interconnect housing for a high- frequency electronic device in accordance with a sixth embodiment of the present invention which includes a sealing cap; FIG. 1 1 is a top view of the microelectronics package shown in FIG.
1 0 with the sealing cap installed; and
FIG . 1 2 is a cross-sectional view of the microelectronics package shown in FIG . 1 0 taken along line 1 2- 1 2 in FIG . 1 1 . DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
Referring to FIGs. 4-6, a ceramic microelectronics package 200 in accordance with a first embodiment of the present invention includes a base 1 02, first attaching means 1 04, a ceramic radio-frequency (RF) circuit substrate 1 06, second attaching means 1 08, a ceramic seal ring substrate 1 1 0, non-conducting third attaching means 1 1 2, and a ceramic lid 1 1 4. Package 200 is used as an electronic interconnect housing for a high- frequency (i.e., beyond 20 GHz) electronic device or component 1 1 6 mounted to base 1 02. Device 1 1 6 is received within a cavity 1 20 formed within circuit substrate 1 06. Seal ring substrate 1 1 0 has a cavity 1 24 larger than cavity 1 20. Device 1 1 6 is an exemplary high-frequency electronic device housed within package 200, and it is understood that device 1 1 6 represents any high-frequency electronic device or component. Thus, package 200 includes some of the same components as package 1 00. A comparison between package 1 00 (FIGs. 1 -3) and package 200
(FIGs. 4-6) reveals that conductive traces 1 22 formed on the top surface of ceramic circuit substrate 1 06 in package 1 00 are replaced by a plurality of conductive patterns 202 and 204 formed on the top surface of circuit substrate 1 06 in package 200. Patterns 202 are conductive signal patterns or traces for providing electrical connections between the electrical signals on device 1 1 6 and an external device. FIGs. 4-6 show four signal patterns 202 extending from the four sides of device 1 1 6 for electrically connecting device 1 1 6 to the external device. However, it will be appreciated by a person of skill in the art that more or fewer signal patterns 202 may be used, that conductive signal patterns 202 may extend from device 1 1 6 using other geometries, and that the geometry of the traces used for signal patterns 202 may change. Patterns 204 are conductive ground patterns, traces, or rails for connection to electrical ground. Patterns 204 are arranged on ceramic circuit substrate 1 06 such that each signal pattern 202 is flanked by a pair of ground patterns 204. Signal patterns 202 and flanking ground patterns 204 are co-planar with each other and with the top surface of ceramic circuit substrate 1 06 since they are formed on the top surface of substrate 1 06.
Base 1 02 has multiple uses, including providing a mechanical mount for package 200 onto a circuit board or carrier (not shown), a thermal and electrical mount for high-frequency electronic device 1 1 6 to be housed in the package, and as an electrical ground reference (i.e., "ground plane"), for the high frequency conductors and other signal traces used as the interconnect. As embodied herein, base 102 can be made from either of two different types of materials. First, base 1 02 can be made of a conductive metal, such as Kovar®, Invar®, copper, copper-tungsten, copper-molybdenum, or molybdenum. Each metal offers advantages in electrical and thermal conductivity, structural strength, low coefficient of thermal expansion, and compatibility to electroplated conductors (for example, nickel, silver, silver- platinum, silver-palladium, or gold). The choice of these metals is only exemplary, and one skilled in the art will recognize that other metals can be used for base 1 02.
Base 1 02 can alternatively be made from a ceramic material, compatible with the remainder of the materials used in package 200. Use of such a ceramic base, however, requires some form of metallization to be applied to certain areas, such as the die attach area for device mounting, for the ground connection, or the bottom of base 1 02 for attaching package 200 to a circuit board or carrier. Examples of such ceramic material are aluminum oxide, aluminum nitride, beryllium oxide, fosterite, cordierite, quartz, fused silica, or other ceramics that would have a composition making them usable as a packaging material. Other ceramic materials not enumerated herein, but providing acceptable electrical and physical properties, can be used and would be known to those skilled in the art.
Attaching means 1 04 comprises some form of adhesive material which will differ depending on whether base 1 02 is metal or ceramic. For a metal base, a metallic solder made from some composition providing good adhesion between metals would be applied either to the top surface of base 1 02 or the bottom surface of circuit substrate 106. An example of such a composition would be gold-germanium or gold-tin composite, although other suitable compositions will be apparent to those skilled in the art.
For a ceramic base, either of two types of attaching material may be used. If metallization is applied to the top surface of base 1 02 and the bottom surface of circuit substrate 1 06, a metal solder would be applied as described above in the case of a metal base. Alternatively, a glass material, e.g. , seal glass, would be applied between base 1 02 and circuit substrate 1 06 in order to adhere the base to the circuit substrate. Those skilled in the art will recognize that other materials not enumerated herein, but providing acceptable electrical and physical properties, can also be used. Circuit substrate 1 06 is made of a ceramic material, such as one of the ceramic materials enumerated above with respect to base 1 02. Circuit substrate 1 06 has cavity area 1 20 cut out of it such that, when attached to base 1 02, the circuit substrate and base together provide a planar interconnect for device 1 1 6 or devices mounted on the base. Moreover, circuit substrate 106 has conductive patterns 202 and 204 deposited on its surface to form conductive signal and ground patterns as described above. The design of the specific shapes used for patterns 202 and 204 can be accomplished through the use of various electrical modeling and simulation software tools, as well as through experimentation. As described above with respect to attaching means 1 04, depending on the material chosen for base 1 02, the bottom surface of circuit substrate 1 06 may have metallization applied to it in order to attach the circuit substrate to the base.
Second attaching means 1 08 is a glass material (e.g., seal glass) deposited on either or both circuit substrate 1 06 and seal ring substrate 1 1 0. If seal glass is to be deposited on circuit substrate 1 06, it is formed such that the dimensions of the glass deposited on the circuit substrate will substantially match those of the seal ring substrate.
Seal ring substrate 1 1 0 is made of the same or similar material as that used for circuit substrate 1 06. As described above for second attaching means 1 08, if seal glass is to be deposited on seal ring substrate 1 1 0, it is applied to the bottom surface of the seal ring substrate, which, when fused to circuit substrate 1 06 or to glass deposited on circuit substrate 1 06, creates a hermetic seal between the two substrates. To attain the proper hermeticity and lamination of seal ring substrate 1 1 0 and circuit substrate 1 06, when fusing the two substrates together by firing the seal glass, they can be weighted. Cavity 1 24 is formed in seal ring substrate 1 1 0 which is larger than cavity 1 20 formed in circuit substrate 106. This can be seen in the overhead view provided by FIG. 5, and the cross-sectional view provided in FIG. 6. Seal ring substrate cavity 1 24 is made larger so that a portion of each conductive signal pattern 202 and ground pattern 204 is exposed inside cavity 1 24, as shown in FIG. 5. The outer dimensions of seal ring substrate 1 1 0 vary to expose a portion of each conductive signal pattern 202 and ground pattern 204 on the outside of package 200, as also shown in FIG. 3. These exposed portions of signal patterns 202 are used as connection points for electronic device 1 1 6 housed inside package 200 to the next component external to the package, and the exposed portions of ground patterns 204 are used as connection points to externally connect ground patterns 204 to electrical ground, or to the ground conductors of CPW transmission lines of the next external component. For example, if package 200 is to be bonded to a circuit board, ground patterns 204 on package 200 can be connected in the same way that signal patterns 202 are connected. Referring again to FIG . 4, ceramic lid 1 1 4 may be made of the same or a similar material as that used for circuit substrate 1 06 and/or seal ring substrate 1 1 0. Third attaching means 1 1 2, a non-conductive polymer adhesive (e.g., epoxy) is affixed to the bottom of ceramic lid 1 1 4 in a window frame fashion to adhere ceramic lid 1 1 4 to seal ring substrate 1 1 0. Alternatively, third attaching means 1 1 2 may be a low-temperature seal glass. Either the bottom or top surface of ceramic lid 1 1 4 may be coated with a material that reduces cavity resonances. Package 200 transmits and receives electrical signals with minimal loss and uses a minimal amount of conductive and non-conductive materials. The package also eliminates the need for a stripline type of transmission line through a ceramic wall, as is used in some related packages. The package construction is not limited to a single material combination, but can use a variety of materials, both conductive and dielectric, to produce a package suitable for high-frequency electronic devices.
The inventive package 200 satisfies the requirements for a microelectronics package suitable for high-frequency electronic devices, using a minimum of conductive materials. First, the package satisfies the structural requirements of resistance to thermal and mechanical shock, moisture, salt atmosphere, vibration, and acceleration, as well as having the characteristic of solderability. The package also satisfies several electrical requirements, including low parasitic effects (i.e., inductance and capacitance), minimal discontinuity reactances, low dissipation loss, and minimal interaction with surrounding devices and environment.
In accordance with the conventional wisdom in the art, in order to meet the requirements for a high frequency feed-through, an impedance match low-loss interconnect for the device to the outside of the package is required. Such an interconnect minimizes or eliminates the need for tuning the device for optimal performance. To meet this requirement, a package must have low insertion loss (less than 0.02 f(GHz) dB and high return loss (greater than 1 5 dB) over the operating frequency band. To meet the requirements for high frequency feed-through, the feed-through structure should be planar, provide a good match for the electrical and magnetic fields at all interfaces, have a minimum number of transitions along the signal path, have a minimum number of discontinuities in the ground path, have a minimum feed-through length (but long enough to reduce interaction between discontinuities), and have minimum ground inductance.
Each conductive signal pattern 202 and flanking ground patterns 204 forms a portion of a CPW transmission line. "CPW transmission line" is defined herein as being a conductor flanked by two ground patterns (e.g., traces, rails or planes) and separated from the flanking ground patterns by a dielectric. Such a CPW transmission line forms a regular CPW transmission line when located above a ground plane, and forms a suspended CPW transmission line when not located above a ground plane. Each signal pattern 202 is a conductor flanked by a pair of ground patterns 204, and patterns 202 and 204 are separated by circuit substrate 1 06. Thus, each signal pattern 202 and flanking ground patterns 204 forms a portion of a CPW transmission line which propagates a signal between the external device and device 1 1 6 as electric and magnetic fields. The transmission lines in package 200 are regular CPW transmission lines since patterns 202 and 204 are located above a ground plane formed by conductive base 1 02. Each CPW transmission line in package 200 has the form of a CPW, embedded CPW, CPW transmission line as the line transitions from outside package 200, beneath seal ring substrate 1 1 0, to inside package 200. "Embedded CPW transmission line" is defined herein as being a CPW transmission line embedded beneath a second dielectric. Since ceramic circuit substrate 1 06 and seal ring substrate 1 1 0 are both dielectrics, the middle portion of each CPW transmission line passing beneath substrate 1 1 0 has the form of an embedded CPW transmission line, and the portions of each CPW transmission line on either side of substrate 1 1 0 (i.e., not beneath substrate 1 1 0) have the form of regular CPW transmission lines.
The CPW transmission lines in package 200, including signal patterns
202 and ground patterns 204, transition through CPW feed-throughs when entering and exiting the package. "Feed-through" is defined herein as an area having different dielectric surroundings through which a conductor passes.
The presence of seal ring substrate 1 1 0 causes the CPW transmission lines to pass through such an area. Thus, the feed-throughs of package 200 can be referred to as CPW feed-throughs.
Another aspect of the present invention is a process for assembling a microelectronic package. The process includes the following steps: Screen printing patterns of conductive paste on the top surface of the circuit substrate; drying and firing the conductive paste; etching to further define the conductive patterns in the conductive paste; screen printing a first seal glass layer on the top surface of the circuit substrate; drying and glazing the first seal glass layer; screen printing a second seal glass layer on the bottom surface of the seal ring substrate; drying and glazing the second seal glass layer; assembling the circuit substrate to the seal ring substrate; and attaching the top surface of the base to the bottom surface of the circuit substrate.
Before beginning the process, fully fired (i.e. , hardened) ceramics are selected for circuit substrate 1 06, ceramic seal ring substrate 1 1 0, and ceramic lid 1 1 4. Preferably, the same ceramic is selected for each component. As for base 1 02, if it is made of a ceramic, it could be the same fully fired ceramic selected for the other components, or it could be a different ceramic material which is compatible with circuit substrate 1 06 but may have either better electrical or thermal properties. Any of the ceramic substrates may be alumina (Al203) of various purities (e.g., 96%, 99.6%), berrylia (BeO), Barium Titanate (BaTi03), fused silica (Si02), or aluminum nitride (AIN), the material being selected to meet the specialized requirements of the product to be assembled. For example, aluminum nitride and berrylia are desirable for high power, heat dissipative applications.
Fully fired (hardened) ceramics are commercially available from ceramic vendors. A fully fired ceramic substrate is typically purchased in one inch to 4.5 inch blanks, with the size selected according to the product to be assembled and the quantity of product desired. Circuit substrate 1 06, preferably 96% pure alumina, is fabricated as follows. Circuit substrate 1 06 is cleaned ultrasonically using a detergent suitable for electronic applications and rinsed with deionized water, then fired to burn out any residues from the detergent. Preferably, an Alconox detergent is used, although those skilled in the art will recognize that other detergents can be used. Next, a conductive paste is screen printed over the top surface of the circuit substrate 106. A first method of defining the conductive patterns or traces is to provide preliminary conductive patterns which have significantly larger dimensions than the desired final dimensions of conductive patterns 202 and 204. Those skilled in the art will recognize that thin film techniques may also be used to deposit the conductive patterns. The photolithography/etch sequence described below will then be used to define the final dimensions of the conductive patterns. A second possible method is to screen print the conductive paste using a screen that provides the actual final dimensions of the conductive patterns 202 and 204. If the second method is selected, no etch step is required.
After the conductive paste is printed over circuit substrate 1 06, it is dried. Circuit substrate 1 06 is then fired according to the specifications provided by the manufacturer of the conductive paste. With respect to the first method of defining conductive patterns 202 and 204, the method of forming the preliminary conductive patterns uses thick film screen printing techniques, as are known in the art. Depending on the application and the type of conductor used, it may be desirable to repeat the printing sequence at least once to attain greater thickness and more uniform density of material, with each printing step being followed by drying and firing steps. The firing temperature, time, and conditions depend on the type of conductive material used, the appropriate parameters being provided by the supplier of the conductive paste. Preferably, the printing, drying, and firing steps will be performed twice in the present invention. The second method for defining the conductive patterns 202 and 204 requires similar processing after the conductive paste is printed onto circuit substrate 1 06.
A large number of conductive pastes are available, and the selection of such a paste will depend upon the product being fabricated. Many pastes are combinations of gold and glass, with variations in the mixtures providing various levels of hermeticity, wire bondability, solderability, etchability, and adhesion. Other possible pastes include silver or copper. Selection of the appropriate paste for the desired product quality falls within the level of skill in the art. Preferably, however, an etchable gold conductor is used in the present invention, and the preferred embodiment is described accordingly. When preliminary conductive patterns with dimensions larger than the desired final dimensions are in place on circuit substrate 1 06, a photolithographic process is used to more precisely define the dimensions of the conductors after which an etch is performed to remove the excess conductive material. This patterning step follows the process as is known in thin film technology in which a photoresist (PR) layer is spun or otherwise coated onto the surface of the preliminary conductive patterns; the PR is exposed to ultraviolet light modulated by a mask bearing the desired patterns; and the unexposed PR is rinsed away using a developer, leaving the areas to be etched exposed. The etch solution which is used for gold conductors is a mixture of potassium-iodine and iodine. After etching, the PR is stripped, and a clean/fire step is performed to burn away any chemical or organic residues remaining after the etching step. This technique is used to define the ultimate dimensions of the conductive patterns 202 and 204 to assure that all of the patterns' dimensions, including thickness, are uniform and within the tolerances desired for reliable operation. After the clean/fire step, a seal glass is screen printed on the top surface of circuit substrate 1 06 to form second attaching means 108. Note that seal glass may be deposited on either or both of seal ring substrate 1 1 0 and circuit substrate 106. If seal glass is to be deposited on the top surface of circuit substrate 1 06, it will substantially match the dimensions of seal ring substrate 1 1 0, which has a larger cavity 1 24 than the cavity 1 20 of circuit substrate 1 06. Thus, the seal glass will not completely cover the top surface of circuit substrate 106. Multiple printings of seal glass may be done in order to obtain the desired total thickness, with the preferred embodiment including three such printing steps. After each printing step, the seal glass paste is dried and glazed. Because circuit substrate 1 06 is also to be joined to base 1 02, a seal glass may be printed onto the bottom surface of circuit substrate 1 06 if the base is ceramic. As described above, depending on the material chosen for base 1 02, the bottom surface of circuit substrate 1 06 may be metallized or may have a seal glass layer placed on it. The glazing temperature is selected to be high enough that volatile materials (organics) within the glass are burned off, but not so high that the conductor on the substrates will melt or flow. The temperature depends on the type of material used, and appropriate temperature ranges are provided by the glass manufacturer. Some slight adjustments in temperature may be necessary due to variations between different types of ovens. Such adjustments are within the level of skill in the art. The selection of the seal glass is dominated by the type of product to be fabricated. In the preferred embodiment, the seal glass is selected to have a coefficient of thermal expansion (CTE) and dielectric constant that match as close as possible the CTE and dielectric constant of the ceramic selected for the substrates. Matching of the CTEs eliminates differential thermal stress between each layer of a multilayer structure.
Separate from the fabrication of circuit substrate 1 06, ceramic seal ring substrate 1 1 0 is fabricated. As with circuit substrate 1 06, a ceramic material is selected which is fully fired and thus already hardened, the preferred ceramic being 96% pure alumina. The ceramic is the same as that selected for circuit substrate 1 06. In the preferred embodiment, seal ring substrate 1 1 0 is cut to create cavity 1 24 at its center. This machining is generally performed by laser ablation using a C02 laser, which is the industry standard machining technique. Other machining techniques that may be used are ultrasonic machining or wire cutting. Other types of lasers may be used as well. Cavity 1 24 cut into seal ring substrate 1 1 0 is larger than the corresponding cavity 1 20 that will be cut into circuit substrate 1 06, as is apparent from the drawings. The resulting ceramic seal ring substrate 1 1 0 may then be mechanically scrubbed to remove any laser slag that may have built up on the substrate.
After removing the laser slag (if necessary), seal ring substrate 1 1 0 is cleaned ultrasonically using a detergent, preferably Alconox, and fired to burn off any residues from the detergent.
As previously mentioned, since second attaching means 1 08 may be formed by deposition of seal glass on one or both of circuit substrate 1 06 and seal ring substrate 1 1 0, the following step is incorporated only if seal glass is to be deposited on the bottom surface of seal ring substrate 1 10.
A seal glass layer is applied to the bottom surface of seal ring substrate 1 1 0. As with circuit substrate 1 06, application of the seal glass layer requires screen printing, drying and glazing, which steps may be performed a number of times, depending on the materials used, to attain the desired thickness.
Upon fabricating circuit substrate 1 06 and seal ring substrate 1 1 0, the two substrates are subassembled, requiring several steps. First, substrates 1 06 and 1 10 are aligned and mated for proper assembly, then the subassembly is fired, during which it may be weighted or clamped together to promote proper lamination and hermeticity between the two substrates. After firing, it may be desirable to check the hermeticity of the seal. The subassembly may be cleaned and inspected, then laser machined to create center cavity 1 20 in circuit substrate 1 06, after which it is inspected again. The laser slag is removed by scrubbing.
Second, the subassembly is cleaned ultrasonically using a detergent, preferably 1 1 1 - trichloroethylene, to remove any grease and is rinsed with deionized water. The subassembly is then fired to burn away any residues left from the detergent. Third, a conductive paste is applied to the bottom surface of the subassembly (i.e., the bottom surface of circuit substrate 1 06), and the screen printed conductive paste is then dried and fired, as described above. Again, the preferred conductive paste is a gold paste, and the print-dry-fire step can be performed multiple times to achieve the desired thickness. After applying the conductive paste, the subassembly may be singulated by sawing; that is, each independent subassembly separated from the blank.
After completing the subassembly, final assembly of package 200 is performed. First, an appropriate base 1 02 is selected. In the preferred embodiment, base 1 02 is made from Kovar®. A hermeticity check may be performed on the subassembly before final assembly; and the subassembly may be cleaned and fired as necessary. Before attaching base 1 02 to the subassembly, the bottom surface of circuit substrate 1 06 may be smoothed in order to prepare the subassembly for soldering. Preparation techniques may vary, depending on the type of solder used. These techniques may affect the amount of solder flow, hermeticity, and visual quality of the assembly. Next, base 1 02 and the subassembly are fitted together with attaching means 1 04 therebetween, and the fitted assembly is fired. After firing, a final hermeticity check may be run; the assembly may be cleaned using an acetone or other detergent to remove grease and other residues; and electrical testing may be performed on sample packages.
After completion of the package, the microelectronic circuit 1 1 6 to be packaged therein is attached using die attach techniques as known in the art. Ceramic lid 1 1 4 is then attached to the top surface of seal ring substrate 1 1 0 by a non-conductive polymer adhesive 1 1 2, such as epoxy, or a seal glass which can be fired and glazed at a sufficiently low temperature to avoid damaging microelectronic circuit 1 1 6. The process for using a non- conductive polymer adhesive 1 1 2 comprises screen printing the polymer onto the bottom surface of lid 1 1 4, then pre-baking lid 1 1 4 to partially cure the adhesive. Once microelectronic circuit 1 1 6 is mounted inside the package, lid 1 1 4 is aligned with seal ring substrate 1 1 0 and then clamped in place, after which a final cure is performed at a temperature low enough to avoid damage to microelectronic circuit 1 1 6. The signal leads of circuit 1 1 6 may then be attached to conductive signal patterns 202 by wire bonds.
Referring to FIG . 7, a ceramic circuit substrate 300 for use in a microelectronics package in accordance with a second embodiment of the present invention is shown. Ceramic circuit substrate 300 is the same as substrate 1 06 in the first embodiment, except for the shapes of conductive patterns deposited on the top surface of the substrate using the same process as described above. These patterns include conductive signal traces 302, each flanked by a pair of conductive ground planes 304. Each ground plane 304 is adjacent to a pair of signal traces 302, and is common to the pair of traces 302. Ground planes 304 can be referred to as continuous ground planes and, as would be apparent to a person of skill in the art, they can provide enhanced electrical noise suppression on signal traces 302. The remaining layers in the microelectronics package, and the process for making them, are the same as described above in relation to the first embodiment.
In the first embodiment of the invention shown in FIGs. 4-6, the two ground patterns 204 adjacent to the signal pattern 202 in each transmission line are at the same electrical potential as conductive base 1 02, and are connected externally to base 1 02. Some high-frequency circuits may require an RF ground closer than can be achieved by external ground connections. FIGs. 8 and 9 show third and fourth embodiments of the present invention which use internal grounding connections for enhanced grounding.
Referring to FIG. 8, a ceramic circuit substrate 400 for use in a microelectronics package in accordance with a third embodiment of the present invention is shown. Ceramic circuit substrate 400 is the same as substrate 1 06 in the first embodiment, except that each conductive ground pattern 204 has a conductive via opening 402 formed therein. Via openings 402 are electrically connected to conductive base 1 02. FIG. 8 shows one via opening 402 formed near the end of each ground pattern 204 near the outer perimeter of substrate 400. However, via openings 402 may also be formed on patterns 204 at other locations (e.g., the middle of each pattern 204, or near the inner perimeter of substrate 400 adjacent cavity 1 20) . Further, each ground pattern 204 could include more than one via opening, and substrate 400 may also include external ground connections as used by the first embodiment. Via openings 402 may also be used to connect ground planes 304 (FIG. 7) to conductive base 1 02.
Via openings 402 may be formed by machining ceramic circuit substrate 400. This machining is generally performed by laser ablation using, for example, a C02 laser, which is an industry standard machining technique. Other machining techniques may also be used, such as ultrasonic machining or other types of lasers. Laser slag that may build up around the machined area is removed by mechanically scrubbing or scraping substrate 400. Electrical connections between ground patterns 204 and base 1 02 are provided by filling or coating via openings 402 with a metallic conductor. First, a dielectric paste is screen printed over the top surface of substrate 400, with a pattern corresponding to the locations of the via openings. A high volume vacuum can be applied to the bottom surface of substrate 400 to help the paste flow into via openings 402. The paste is then dried. Any excess paste remaining on the top and bottom surfaces of substrate 400 may be removed by scraping the surfaces, and wiping the surfaces with a lint-free cloth dampened with a solvent. All remaining paste is located within via openings 402 to coat the sidewalls, with the vias remaining open. Substrate 400 is then fired according to the specifications provided by the manufacturer of the dielectric paste. The glass via coating helps to strengthen any microcracks that may have formed around openings 402 during machining and assists in adhesion of a gold conductor.
The glass coated sidewalls are then coated with the gold conductor by screen printing a gold paste using the same screen pattern as was used for the dielectric paste. In a similar manner, the gold paste is pulled into the openings and dried, with excess paste being removed from the surfaces by scraping and wiping the surfaces. The only remaining gold paste is then in the via openings. Again, the vias should remain open following this step. The via openings are then filled with a gold conductor by screen printing a gold paste over the top surface of substrate 400 using a dry/scrape/wipe process to fill the via openings while removing all paste from the surfaces. The printing sequence (print/dry/scrape/wipe) can be repeated to thicken the conductive layer within the via openings, with the gold paste being fired following each printing sequence. The sequence can be repeated until the conductive coating reaches a desired thickness, or until the via opening is filled with conductor. The process of forming conductive via openings is generally known in the art, and other alternatives are available. The remaining layers in the microelectronics package, and the process for making them, are the same as described above in relation to the first embodiment. Referring to FIG. 9A-9B, a ceramic circuit substrate 500 for use in a microelectronics package in accordance with a fourth embodiment of the present invention is shown. Substrate 500 is the same as substrate 1 06 in the first embodiment, except that an aperture or "ear" 502 has been cut into substrate 500 proximate to each ground pattern 204. FIG . 9A-9B shows ears 502 cut at the outer perimeter of substrate 500. Alternatively, ears 502 could be cut into substrate 500 at its inner perimeter surrounding cavity 1 20. As shown in the magnified view of FIG. 9B, ears 502 provide apertures for bonding wires 504 or ribbons, to pass through. Wires 504 internally connect ground patterns 204 to conductive base 1 02. Bonding wires 504 are attached to patterns 204 and base 1 02 after substrate 500 is attached to base 1 02 by the above-described process. Ears 502 are also formed by machining ceramic circuit substrate 500 as described above. A ceramic microelectronics package with CPW transmission lines in accordance with a fifth embodiment of the invention appears as shown in FIGs. 4-6, except that base 1 02 is made from a non-conductive or dielectric material such as ceramic. For example, if substrate 106 is made of alumina, then base 1 02 is made of alumina or beryllia. Since the CPW transmission line formed by each conductive signal pattern 202 flanked by two ground patterns 204 is no longer located above a ground plane, the CPW transmission lines of the fifth embodiment are suspended CPW transmission lines. Similarly, if base 1 02 of the second embodiment of the present invention shown in FIG. 7 were made of a non-conductive material, then the CPW transmission lines would also be suspended CPW transmission lines.
Referring to FIGs. 1 0-1 2, a ceramic microelectronics package 600 in accordance with a sixth embodiment of the present invention is shown.
Package 600 includes a base 1 02, attaching means 1 04, an RF circuit substrate 1 06 with conductive signal patterns 202 and ground patterns 204 formed thereon, second attaching means 602, and a sealing cap 604. Patterns 202 and 204 are the same as in package 200. Package 600 is also used as an electronic interconnect housing for high-frequency devices.
Base 1 02 has multiple uses, including providing a mechanical mount for package 600 onto a circuit board or carrier (not shown), a thermal and electrical mount for high-frequency electronic device 1 1 6 to be housed in the package, and as a ground reference for high-frequency conductive patterns 202 and 204 and other signal traces used as the interconnect. As embodied herein, base 1 02 can be made from either of two different types of materials. First, the base can be made of a conductive metal, such as Kovar®, Invar®, copper, cold rolled steel, copper-tungsten, copper- molybdenum, and molybdenum. Each metal offers advantages in electrical and thermal conductivity, structural strength, low coefficient of thermal expansion, and compatibility to electroplated conductors (for example, nickel, silver, silver-platinum, silver-palladium, or gold). In addition to the metals listed above, base 1 02 may be made of several low expansion iron-nickel alloys, having a nickel content ranging from 42-52%, with the balance being predominantly iron. One such alloy is identified as Alloy 46, which consists of a combination of 46% nickel with the balance predominantly iron, and is available in commercial quantities from several sources, including National Electronic Alloys of Oakland, New Jersey. Specifications for the metallurgical properties of Alloy 46 are found in American Society for Test Methods (ASTM) Publication F30. Alloy 46 is a prime material for a low cost package 600, ideal for lower power devices where thermal dissipation is not a significant requirement. The choice of these metals is only exemplary, and one skilled in the art will recognize that other metals can be used.
Base 1 02 can alternatively be made from a ceramic material, compatible with the remainder of the materials used in package 600. Use of such a ceramic base, however, requires some form of metallization to be applied to certain areas, such as the die attach area for device mounting, for the ground connection, or the bottom surface of base 1 02 for attaching package 600 to a circuit board or carrier. Examples of such ceramic material are aluminum oxide, aluminum nitride, beryllium oxide, fosterite, cordierite, quartz, fused silica, or other ceramics that would have a composition making them usable as a packaging material. Other ceramic materials not enumerated herein, but providing acceptable electrical and physical properties, can be used and would be known to those skilled in the art. Attaching means 104 comprises an adhesive material which may differ depending on whether base 1 02 is metal or ceramic. For a metal base, a metallic solder made from a composition providing good adhesion between metals would be applied either to the top surface of base 1 02 or the bottom surface of RF circuit substrate 106. An example of such a composition would be copper-silver joining alloy, although other suitable composites will be apparent to those skilled in the art.
For a ceramic base, a variety of attaching materials may be used. Specifically, the ceramic base may be attached with the same options set out above for use with a metal base. Any preparation of the ceramic base for attachment is obvious to those skilled in the art. For example, if the ceramic base is to be attached with metal solder, the base must be metallized so that the solder will adhere. As an alternative to solder, a glass material, e.g., seal glass, could be applied between base 1 02 and RF circuit substrate 1 06 in order to adhere the base to substrate 1 06.
Another material suitable for either a metal or ceramic base 1 02 is an organic adhesive. Organic adhesives are an ideal low cost alternative as its use eliminates several process steps and many expensive materials listed above. For example, even if metallization of the ceramic base is required for electrical considerations, use of the organic adhesives eliminate the need to prepare the bottom surface of RF circuit substrate 1 06 for attachment to base 1 02. These organic adhesives may include metal filled adhesives such as conductive polymers for higher frequency applications, polyimide, polyvinyl acetate, polyvinyl alcohol, acrylic, phenolic, phenol-resorcinol, epoxy, urea formaldehyde, melamine, alkyd, phenolic-vinyl, phenolic-polyvinyl butyrate, phenolic-nylon, and phenolic neoprene. Those skilled in the art will recognize that the use of a polymer adhesive will permit use of a polymer or a ceramic-filled polymer for base 1 02. It is to be appreciated, however, that those skilled in the art will recognize that any adhesive providing acceptable electrical and physical properties can also be used.
RF circuit substrate 1 06 may be made of a ceramic material, such as one of the ceramic materials enumerated above with respect to base 1 02. Additionally, substrate 1 06 may also be made from a number of other dielectrics including teflon, glass, low cost electronic grade ceramic, and several plastics, depending on the electrical requirements. More specifically, the glass dielectric materials suitable for substrate 1 06 include soda lime (float or lamp bulb), alumina silicate, borosilicate (low loss electrical) 99.5% silica for high temperatures. Further, the plastic dielectric materials may be filled or unfilled. The filler could be in the form of a glass matt (for example, G 1 0 printed circuit board material). Also, the ceramics listed above could be used in powdered form as an amorphous filler in the plastic. The plastics could include any of those commonly used in electrical applications, such as epoxy molding compounds and thermoset molding compounds. Specific choices for such plastics include nylon, resins, novalacks, phenolics, polysulfones, polyetherimides, and liquid crystal plastics. Those skilled in the art will recognize that any plastic which provides acceptable electrical and physical properties can also be used.
RF circuit substrate 1 06 has a cavity area 1 20 cut out of it such that, when attached to base 1 02, the substrate and base together provide a planar interconnect for high-frequency electronic device 1 1 6 or devices mounted on the base. Moreover, substrate 1 06 has a number of conductive patterns 202 and 204 deposited on its surface. Patterns 202 and 204 have a specific shape designed to maintain a uniform characteristic impedance from end to end of the conductor. This is done through use of various electrical modeling and simulation software tools, as well as through experimentation. As described above with respect to attaching means 1 04, depending on the material chosen for base 1 02, the bottom surface of substrate 1 06 may have metallization applied to it in order to attach the substrate to the base.
Second attaching means 602 for the sixth embodiment is an epoxy deposited on either or both RF circuit substrate 1 06 and sealing cap 604. If epoxy is to be deposited on substrate 1 06, it is formed so that the dimensions of the epoxy deposited on the substrate will substantially match those of sealing cap 604.
Sealing cap 604 may be made of the same or similar material as that used on RF circuit substrate 1 06. More specifically, sealing cap 604 can be made from a number of dielectric materials including teflon, glass, low cost electronic grade ceramic, and several plastics, depending on the electrical requirements. The glass dielectric materials may include soda lime (float or lamp bulb), alumina silicate, borosilicate (low loss electrical) 99.5% silica for high temperatures. Further, the plastic dielectric materials may be filled or unfilled. The filler could be in the form of a glass matt (e.g., G 1 0 printed circuit board material) . Also, the ceramics listed above could be used in powdered form as an amorphous filler in the plastic. The plastics could include any of those commonly used in electrical applications, such as epoxy molding compounds and thermoset molding compounds. Specific choices for such plastics include nylon, resins, novalacks, phenolics, polysulfones, polyetherimides, and liquid crystal plastics. It is to be appreciated, however, that those skilled in the art will recognize that any plastic which provides acceptable electrical and physical properties can also be used.
As described above for second attaching means 602, if seal glass is to be deposited on sealing cap 604, it is applied to the bottom surface of the sealing cap, which, when fused to RF circuit substrate 106 or to glass deposited on substrate 1 06, creates a hermetic seal between substrate 1 06 and sealing cap 604. To attain the proper hermeticity and lamination of sealing cap 604 and substrate 1 06, when fusing the two surfaces together by firing the seal glass, they can be weighted. The outer dimensions of sealing cap 604 are selected so as to expose a portion of each conductive pattern 202 and 204 on the outside of package 600. The exposed portions of signal patterns 202 are used as connection points for device 1 1 6 housed inside package 600 to the next component or trace external to package 600, and the exposed portions of ground patterns 204 are used as connection points to externally connect patterns 204 to electrical ground, or to the ground conductors of CPW transmission lines on the next external component. For example, if package 600 is to be bonded to a circuit board, ground patterns 204 on package 600 can be connected in the same way that signal patterns 202 are connected. As shown in FIG. 1 2, sealing cap 604 is formed with a chamber 606 having a larger diameter than cavity 1 20 formed in RF circuit substrate 1 06. This allows the placement of sealing cap 604 directly against the upper surface of substrate 1 06 while still allowing a portion of each conductive pattern 202 and 204 to be exposed inside chamber 606. The process for assembling a microelectronic package in accordance with the sixth embodiment includes the steps of: screen printing conductive patterns 202 and 204 on RF circuit substrate 1 06; screen printing first attaching means 1 04 on the top surface of base 1 02; and attaching the top surface of base 1 02 to the bottom surface of substrate 1 06. Before beginning the assembly process for the sixth embodiment, the material for RF circuit substrate 1 06 is selected. If substrate 1 06 is made of a ceramic material, it could be the same fully fired ceramic which may be selected for the other components. Any of the ceramic substrates may be alumina (AI2O3) of various purities (e.g., 96%, 99.6%), berrylia (BeO), barium titanate (BaTi03), fused silica (Si02), or aluminum nitride (AIN), the material being selected to meet the specialized requirements of the product to be assembled, which will be within the level of skill in the art. For example, aluminum nitride and berrylia are desirable for high power, heat dissipative applications. In addition to ceramic, RF circuit substrate 1 06 may be made from a number of dielectrics including teflon, glass, low cost electronic grade ceramic, and several plastics, depending on the electrical requirements. These materials include soda lime (float or lamp bulb), alumina silicate, borosilicate, and filled or unfilled plastics including nylon, resins, novalacks, phenolics, polysulfones, polyetherimides, and liquid crystal plastics.
RF circuit substrate 106 is cleaned ultrasonically using a detergent suitable for electronic applications and rinsed with deionized water, then fired to burn out any residues from the detergent. Preferably, an Alconox detergent is used, although other detergents can be used.
Next, conductive patterns or traces 202 and 204 are formed on the top surface of RF circuit substrate 1 06. Such patterns may be formed using a variety of methods. One method of defining the patterns is to screen print preliminary conductive patterns using thick film screen printing techniques. The patterns would have significantly larger dimensions than the desired final dimensions of patterns 202 and 204. Depending on the application and the type of conductor used, it may be desirable to repeat this printing sequence at least once to attain greater thickness and more uniform density of the printed material, each printing step being followed by drying and firing steps.
When preliminary conductive patterns with dimensions larger than the desired final dimensions are on RF circuit substrate 1 06, a photolithographic process is used to more precisely define the dimensions of the patterns after which an etch is performed to remove excess conductive material. This patterning step follows the process as is known in thin film technology in which a photoresist (PR) layer is spun or otherwise coated onto the surface of the preliminary conductive patterns; the PR is exposed to ultraviolet light modulated by a mask bearing the desired patterns; and the unexposed PR is rinsed away using a developer, leaving the areas to be etched exposed. The RF circuit substrate is then immersed in an etch solution for etching. This etch solution, typically used for gold conductors, is a mixture of potassium- iodine and iodine. After etching, the PR is stripped, and a clean/fire step is performed to burn away any chemical or organic residues remaining after the etching step. This technique defines the ultimate dimensions of conductive patterns 202 and 204 to assure that all dimensions, including thickness, are uniform and within the tolerances desired for reliable operation.
Another possible method of defining conductive patterns 202 and 204 is to screen print the conductive paste using a screen that provides the actual final dimensions of the conductive patterns. This method does not require the use of an etching process. After the conductive paste is printed over the substrate, it is dried. RF circuit substrate 1 06 is then fired according to the specifications provided by the manufacturer of the paste.
Yet another possible method of defining the conductive patterns when ceramic is selected for RF circuit substrate 1 06 involves the application of metal foil directly on the surface of the ceramic. For example, copper foil may be directly bonded to alumina and other ceramics through a process known as direct bond copper. After bonding the copper foil to the ceramic, the copper foil may be etched using the photolithography/etch sequence as described below to define the final dimensions of the conductive patterns. Another method of defining the conductive patterns, particularly useful for low-cost packages, involves the implementation of the printed wiring board industry's method of printing a polymer thick film on a substrate. Using this approach, it is possible to incorporate a filled polymer substrate material, instead of alumina ceramic. This allows a large number of RF substrates 1 06 to be simultaneously formed from a single sheet of polymer. Substrates 106 may then be printed and/or etched with conductive patterns 202 and 204 for subsequent separation into single substrates. To establish a sufficient conductor thickness, the thick film printed on the polymer substrate may be repeatedly plated using electroplate or electrodeless plate techniques. For example, a high volume approach is to print a silver polymer thick film on a polymer substrate, followed by plated nickel, and plated gold.
Next, second attaching means 602 is screen printed on the top surface of RF circuit substrate 1 06. Second attaching means 1 08 in the sixth embodiment consists of a non-conductive polymer adhesive, such as epoxy. The epoxy may be deposited on either or both of sealing cap 604 and substrate 1 06. If epoxy is to be deposited on the top surface of substrate 106, it will substantially match the dimensions of sealing cap 604. Multiple printings of epoxy may be done to obtain the desired total thickness. Separate from the fabrication of RF circuit substrate 1 06, sealing cap 604 is fabricated. As discussed above, the sealing cap may be made from a number of dielectric materials including teflon, glass, low cost electronic grade ceramic, and several plastics, depending on the electrical requirements. The glass dielectric materials include soda lime (float or lamp bulb), alumina silicate, borosilicate (low loss electrical) 99.5% silica for high temperatures. Further, the plastic dielectric materials may be filled or unfilled. The filler could be in the form of a glass matt (for example, G 1 0 printed circuit board material) . Also, the ceramics listed above could be used in powdered form as an amorphous filler in the plastic. The plastics could include any of those commonly used in electrical applications, such as epoxy molding compounds and thermoset molding compounds. Specific choices for such plastics include Nylon, resins, novalacks, phenolics, polysulfones, polyetherimides, and liquid crystal plastics. It is to be appreciated, however, that those skilled in the art will recognize that any plastic which provides acceptable electrical and physical properties can also be used.
After completing RF circuit substrate 1 06, the final assembly of package 600 is performed. First, an appropriate base 1 02 is selected from the materials listed above. In the sixth embodiment, base 1 02 is preferably made of Alloy 52. A hermeticity check may be performed on the subassembly before final assembly; and the subassembly may be cleaned and fired as necessary. Before attaching base 1 02 to the bottom surface of substrate 1 06, the bottom surface of the substrate may be smoothed to facilitate the attachment. Preparation techniques may vary, depending on the type of base material used.
Next, base 102 and RF circuit substrate 1 06 are fitted together with attaching means 1 04 therebetween. Namely, attaching means 1 04 for the sixth embodiment is an organic adhesive. Such adhesive is, perhaps, a more simple method of attaching substrate 1 06 to base 1 02. However, any of the adhesives discussed above will retain substrate 1 06 and base 1 02 together.
After fitting base 102 and RF circuit substrate 1 06 together, the device 1 1 6 to be packaged therein is attached to substrate 1 06 using die attach techniques as are known in the art. Sealing cap 604 is then sealed to the upper surface of substrate 106 by a non-conductive polymer adhesive 602, such as epoxy. The process for using a non-conductive polymer adhesive 602 comprises screen printing the adhesive onto the bottom surface of sealing cap 604, then pre-baking the sealing cap to partially cure the adhesive. Once device 1 1 6 is mounted inside package 600, sealing cap 604 is aligned with substrate 106. Sealing cap 604 is then clamped in place on the surface of substrate 1 06, after which a final cure is performed at a temperature low enough to avoid damage to microelectronic device 1 1 6.
The above-described process provides a significant advantage over prior art process sequences in that the number of steps is reduced by more than 30% . In addition, the components used can be formed of less expensive materials, making the package more attractive for both its processing, and the material required.
As will be apparent to a person of skill in the art, the features described above in relation to each embodiment may be combined with the features of the other embodiments. For example, the flanking ground planes described in relation to the second embodiment may be electrically connected to the base of the package by conductive via openings as in the third embodiment, or by bonding wires passing through ears as in the fourth embodiment, and may form a portion of suspended CPW transmission lines as in the fifth embodiment. Also, the flanking ground traces of the first embodiment or the flanking ground planes of the second embodiment may be electrically connected to ground by external connections, by conductive via openings to the package base as in the third embodiment, by bonding wires passing through ears as in the fourth embodiment, or by a combination of such external connections, via openings and bonding wires.
It will be evident that there are additional embodiments and applications which are not disclosed in the detailed description but which clearly fall within the scope and spirit of the present invention. The specification is, therefore, not intended to be limiting, and the scope of the invention is to be limited only by the following claims.
WE CLAIM:

Claims

1 . A ceramic microelectronic package suitable for housing a high- frequency electronic device, comprising: a base having a top surface and a bottom surface; a ceramic circuit substrate attached to the top surface of the base, the ceramic circuit substrate having a surface and a cavity for receiving the high- frequency electronic device; and a plurality of conductive patterns deposited on the surface of the ceramic circuit substrate, the conductive patterns including at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a co-planar waveguide (CPW) transmission line.
2. The ceramic microelectronic package of claim 1 , wherein the conductive signal pattern includes a signal trace, and the conductive ground patterns include ground traces flanking the signal trace.
3. The ceramic microelectronic package of claim 2, wherein the conductive patterns include a plurality of signal traces and a plurality of ground traces, each signal trace being flanked by a pair of the ground traces.
4. The ceramic microelectronics package of claim 1 , wherein the conductive signal pattern includes a signal trace, and the conductive ground patterns include ground planes flanking the signal trace.
5. The ceramic microelectronics package of claim 4, wherein the conductive patterns include a plurality of signal traces and a plurality of ground planes, each signal trace being flanked by a pair of the ground planes.
6. The ceramic microelectronics package of claim 5, wherein each ground plane is adjacent to a pair of the signal traces to form a common ground plane between the pair of signal traces.
7. The ceramic microelectronics package of claim 1 , wherein each conductive ground pattern has a portion exposed outside the package for external connection to electrical ground.
8. The ceramic microelectronics package of claim 1 , wherein at least a portion of at least one of the top surface and the bottom surface of the base is conductive, and the base acts as an electrical ground plane.
9. The ceramic microelectronics package of claim 8, wherein each conductive ground pattern is electrically coupled to the base by a conductive via opening.
1 0. The ceramic microelectronics package of claim 8, wherein the ceramic circuit substrate has an ear proximate to each conductive ground pattern to allow wire bonding of each conductive ground pattern to the base.
1 1 . The ceramic microelectronics package of claim 1 0, wherein the ceramic circuit substrate has an outer perimeter, and each ear is located at the outer perimeter.
1 2. The ceramic microelectronics package of claim 1 0, wherein the ceramic circuit substrate has an inner perimeter surrounding the cavity, and each ear is located at the inner perimeter.
1 3. The ceramic microelectronics package of claim 1 , wherein the base is non-conductive, whereby the CPW transmission line is a suspended CPW transmission line.
1 4. A ceramic microelectronic package suitable for housing a high- frequency electronic device, comprising: a base having a top surface and a bottom surface; a ceramic circuit substrate attached to the top surface of the base, the ceramic circuit substrate having a surface and a first cavity for receiving the high-frequency electronic device; a plurality of conductive patterns deposited on the surface of the ceramic circuit substrate, the conductive patterns including at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a CPW transmission line; a ceramic seal ring substrate attached to the ceramic circuit substrate and having a second cavity larger than the first cavity; and a ceramic lid attached to the ceramic seal ring substrate, wherein a middle portion of the CPW transmission line passes beneath the ceramic seal ring substrate, whereby the CPW transmission line forms a CPW, embedded CPW, and CPW transmission line.
1 5. A microelectronic package suitable for housing a high-frequency electronic device, comprising: a base having a top surface and a bottom surface; an RF circuit substrate attached to the top surface of the base, the RF circuit substrate having a surface and a cavity for receiving the high- frequency electronic device; a plurality of conductive patterns deposited on the surface of the RF circuit substrate, the conductive patterns including at least one conductive signal pattern and at least two conductive ground patterns, wherein the conductive ground patterns flank the conductive signal pattern to form at least a portion of a CPW transmission line; and a dielectric sealing cap attached to the RF circuit substrate and having a chamber larger than the cavity of the RF circuit substrate, wherein a middle portion of the CPW transmission line passes beneath the sealing cap, whereby the CPW transmission line forms a CPW, embedded CPW, and CPW transmission line.
1 6. A process for assembling a ceramic microelectronic package for retaining a high-frequency integrated circuit, the package having a base and a ceramic circuit substrate, the base and the ceramic circuit substrate each having top and bottom surfaces, the process comprising the steps of: depositing a plurality of conductive patterns on the top surface of the ceramic circuit substrate, the conductive patterns including a plurality of conductive signal patterns and a plurality of conductive ground patterns, each of the conductive signal patterns being flanked by a pair of the conductive ground patterns to form at least a portion of a plurality of CPW transmission lines for providing electrical connections between the high- frequency integrated circuit and an external device; cutting a cavity into the ceramic circuit substrate, the cavity having dimensions for receiving the high-frequency integrated circuit; attaching the top surface of the base to the bottom surface of the ceramic surface substrate to form an assembly; and firing the assembly.
1 7. The process of claim 1 6, wherein the step of depositing a plurality of conductive patterns includes screen printing a conductive paste onto the top surface of the ceramic circuit substrate.
1 8. The process of claim 1 7, wherein the step of depositing a plurality of conductive patterns includes screen printing a plurality of signal traces and a plurality of ground traces, each signal trace being flanked by a pair of ground traces.
1 9. The process of claim 1 7, wherein the step of depositing a plurality of conductive patterns includes screen printing a plurality of signal traces and a plurality of ground planes, each signal trace being flanked by a pair of ground planes.
20. The process of claim 1 6, wherein at least a portion of at least one of the top surface and the bottom surface of the base is conductive, further comprising the steps of forming via openings in the ceramic circuit substrate corresponding to the conductive ground patterns, and applying a conductive material to the via openings to electrically couple the conductive ground patterns to the base.
21 . The process of claim 1 6, wherein at least a portion of at least one of the top surface and the bottom surface of the base is conductive, further comprising the steps of cutting ears in the ceramic circuit substrate proximate to the conductive ground patterns to allow wire bonding of the conductive ground patterns to the base.
22. The process of claim 21 , wherein the ceramic circuit substrate has an outer perimeter, and the step of cutting ears causes the ears to be formed at the outer perimeter.
23. The process of claim 21 , wherein the ceramic circuit substrate has an inner perimeter surrounding the cavity, and the step of cutting ears causes the ears to be formed at the inner perimeter.
24. The process of claim 1 6, further comprising the steps of attaching a ceramic seal ring substrate to the ceramic circuit substrate and attaching a ceramic lid to the ceramic seal ring substrate, the ceramic seal ring substrate having a second cavity larger than the first cavity of the ceramic circuit substrate, and the step of depositing the conductive patterns causes middle portions of the CPW transmission lines to pass beneath the ceramic seal ring substrate to form CPW, embedded CPW, CPW transmission lines.
25. The process of claim 1 6, further comprising the steps of attaching a dielectric sealing cap to the ceramic circuit substrate, the sealing cap having a chamber larger than the first cavity of the ceramic circuit substrate, and the step of depositing the conductive patterns causes middle portions of the CPW transmission lines to pass beneath the sealing cap to form CPW, embedded CPW, CPW transmission lines.
PCT/US1998/026263 1997-12-15 1998-12-10 Ceramic microelectronics package with co-planar waveguide feed-through WO1999034443A1 (en)

Priority Applications (1)

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AU18149/99A AU1814999A (en) 1997-12-15 1998-12-10 Ceramic microelectronics package with co-planar waveguide feed-through

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99035497A 1997-12-15 1997-12-15
US08/990,354 1997-12-15

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WO1999034443A1 WO1999034443A1 (en) 1999-07-08
WO1999034443A9 true WO1999034443A9 (en) 2000-03-02

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PCT/US1998/026263 WO1999034443A1 (en) 1997-12-15 1998-12-10 Ceramic microelectronics package with co-planar waveguide feed-through

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AU (1) AU1814999A (en)
WO (1) WO1999034443A1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4626805A (en) * 1985-04-26 1986-12-02 Tektronix, Inc. Surface mountable microwave IC package
JPH04256203A (en) * 1991-02-07 1992-09-10 Mitsubishi Electric Corp Package for microwave band ic
JP2763445B2 (en) * 1992-04-03 1998-06-11 三菱電機株式会社 High frequency signal wiring and bonding device therefor
US5753972A (en) * 1993-10-08 1998-05-19 Stratedge Corporation Microelectronics package
US5602421A (en) * 1995-01-31 1997-02-11 Hughes Aircraft Company Microwave monolithic integrated circuit package with improved RF ports
US5986331A (en) * 1996-05-30 1999-11-16 Philips Electronics North America Corp. Microwave monolithic integrated circuit with coplaner waveguide having silicon-on-insulator composite substrate

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WO1999034443A1 (en) 1999-07-08
AU1814999A (en) 1999-07-19

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