WO1999017352A1 - Procede et compositions permettant de metalliser des traversees et des interconnexions haute densite dans des dielectriques photodefinis - Google Patents

Procede et compositions permettant de metalliser des traversees et des interconnexions haute densite dans des dielectriques photodefinis Download PDF

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Publication number
WO1999017352A1
WO1999017352A1 PCT/US1998/020495 US9820495W WO9917352A1 WO 1999017352 A1 WO1999017352 A1 WO 1999017352A1 US 9820495 W US9820495 W US 9820495W WO 9917352 A1 WO9917352 A1 WO 9917352A1
Authority
WO
WIPO (PCT)
Prior art keywords
pattern
metal
additional
dielectric
dielectric layer
Prior art date
Application number
PCT/US1998/020495
Other languages
English (en)
Inventor
Paul H. Kydd
Original Assignee
Partnerships Limited, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Partnerships Limited, Inc. filed Critical Partnerships Limited, Inc.
Priority to AU95932/98A priority Critical patent/AU9593298A/en
Publication of WO1999017352A1 publication Critical patent/WO1999017352A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

La présente concerne un procédé permettant de métalliser des micro-traversées et des interconnexion haute densité dans des diélectriques photodéfinis à l'aide de nouveaux composés organo-métalliques à durcissement rapide, à basse température. Les matières sont appliquées sur la photoimage développée par un procédé d'impression quelconque adapté et sont durcies thermiquement en conducteurs de métal pur bien consolidés au même moment et dans les mêmes conditions que le durcissage et la réticulation des diélectriques en résines infusibles, insolubles.
PCT/US1998/020495 1997-09-30 1998-09-30 Procede et compositions permettant de metalliser des traversees et des interconnexions haute densite dans des dielectriques photodefinis WO1999017352A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU95932/98A AU9593298A (en) 1997-09-30 1998-09-30 Method and compositions for metallizing microvias and high density interconnectsin photodefined dielectrics

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6052197P 1997-09-30 1997-09-30
US60/060,521 1997-09-30

Publications (1)

Publication Number Publication Date
WO1999017352A1 true WO1999017352A1 (fr) 1999-04-08

Family

ID=22030022

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/020495 WO1999017352A1 (fr) 1997-09-30 1998-09-30 Procede et compositions permettant de metalliser des traversees et des interconnexions haute densite dans des dielectriques photodefinis

Country Status (2)

Country Link
AU (1) AU9593298A (fr)
WO (1) WO1999017352A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001033649A1 (fr) 1999-11-02 2001-05-10 Koninklijke Philips Electronics N.V. Procede permettant de produire des interconnexions verticales entre des dispositifs micro-electroniques a film mince, et produits comprenant ces interconnexions verticales
GB2362031B (en) * 1999-11-04 2002-11-27 Nippon Electric Co Flip-chip type semiconductor device with stress-absorbing layer made of thermosetting resin, and its manufacturing method
EP1289013A1 (fr) * 2001-08-15 2003-03-05 Datamars SA Procédé pour appliquer une puce semiconductrice sur un substrat et assemblage ainsi obtneu
GB2385466A (en) * 1999-11-04 2003-08-20 Nec Corp Flip-chip device having stress absorbing layers and contacts
EP1622435A1 (fr) * 2004-07-28 2006-02-01 ATOTECH Deutschland GmbH Méthode de fabrication d'un dispositif par des techniques d'écriture directe
US7141185B2 (en) 2003-01-29 2006-11-28 Parelec, Inc. High conductivity inks with low minimum curing temperatures
US7211205B2 (en) 2003-01-29 2007-05-01 Parelec, Inc. High conductivity inks with improved adhesion

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5503698A (en) * 1990-06-14 1996-04-02 International Business Machines Corporation Bonding method employing organometallic interconnectors
US5728626A (en) * 1993-07-26 1998-03-17 At&T Global Information Solutions Company Spin-on conductor process for integrated circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5503698A (en) * 1990-06-14 1996-04-02 International Business Machines Corporation Bonding method employing organometallic interconnectors
US5728626A (en) * 1993-07-26 1998-03-17 At&T Global Information Solutions Company Spin-on conductor process for integrated circuits

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001033649A1 (fr) 1999-11-02 2001-05-10 Koninklijke Philips Electronics N.V. Procede permettant de produire des interconnexions verticales entre des dispositifs micro-electroniques a film mince, et produits comprenant ces interconnexions verticales
US6635406B1 (en) 1999-11-02 2003-10-21 Koninklijke Philips Electronics N.V. Method of producing vertical interconnects between thin film microelectronic devices and products comprising such vertical interconnects
GB2362031B (en) * 1999-11-04 2002-11-27 Nippon Electric Co Flip-chip type semiconductor device with stress-absorbing layer made of thermosetting resin, and its manufacturing method
GB2385466A (en) * 1999-11-04 2003-08-20 Nec Corp Flip-chip device having stress absorbing layers and contacts
US6696317B1 (en) 1999-11-04 2004-02-24 Nec Electronics Corporation Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin
US6767761B2 (en) 1999-11-04 2004-07-27 Nec Electronics Corporation Method of manufacturing a flip-chip semiconductor device with a stress-absorbing layer made of thermosetting resin
EP1289013A1 (fr) * 2001-08-15 2003-03-05 Datamars SA Procédé pour appliquer une puce semiconductrice sur un substrat et assemblage ainsi obtneu
US7141185B2 (en) 2003-01-29 2006-11-28 Parelec, Inc. High conductivity inks with low minimum curing temperatures
US7211205B2 (en) 2003-01-29 2007-05-01 Parelec, Inc. High conductivity inks with improved adhesion
EP1622435A1 (fr) * 2004-07-28 2006-02-01 ATOTECH Deutschland GmbH Méthode de fabrication d'un dispositif par des techniques d'écriture directe
WO2006010639A2 (fr) * 2004-07-28 2006-02-02 Atotech Deutschland Gmbh Procede de fabrication d'un ensemble circuit electronique
WO2006010639A3 (fr) * 2004-07-28 2006-10-26 Atotech Deutschland Gmbh Procede de fabrication d'un ensemble circuit electronique

Also Published As

Publication number Publication date
AU9593298A (en) 1999-04-23

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