WO1999012263A1

WO1999012263A1 - Semiconductor integrated circuit device

Info

Publication number: WO1999012263A1
Application number: PCT/JP1998/002961
Authority: WO
Inventors: Masayuki Miyazaki; Koichiro Ishibashi; Hiroyuki Mizuno
Original assignee: Hitachi, Ltd.
Priority date: 1996-03-27
Filing date: 1998-07-01
Publication date: 1999-03-11

Abstract

A semiconductor integrated circuit device provided with a logic circuit (LOG001) which performs prescribed processing, a D/A conversion circuit (DACONV001) which generates a substrate bias for controlling the threshold of a MIS transistor constituting the logic circuit (LOG001), a voltage control circuit (VCNT001) which outputs a control signal in accordance with a delay signal, and a delay detecting circuit (MON001) which can operate at a variable speed. The circuit device is characterized in that the delay detecting circuit outputs the delay signal upon receiving a clock signal (clk001) from the outside, that the voltage control circuit inputs the delay signal from the delay detecting circuit and outputs the control signal corresponding to the delay time, that the D/A conversion circuit generates the voltage corresponding to the control signal received from the voltage control circuit, and that the operating speeds of the logic circuit and the delay detecting circuit are controlled by the voltage supplied from the D/A conversion circuit.

Description

Specification

Semiconductor integrated circuit device

Technical field

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit device suitable for high-speed operation.

This application is a continuation-in-part of United States Patent Application No. 08 / 622,389 (March 27, 1996). The disclosure forms part of the present application.

Background art

The characteristics of integrated circuits using CMOS transistors fluctuate due to variations in the transistor dimensions caused by the manufacturing process and environmental changes such as temperature and power supply voltage during operation. Exists.

1 9 9 4 Symposium on buoy 'L' S 's technology technologi digest to techno techno, 、 (June, 1991) Page 13 As described on page 14 of Kyocchi et al., As the M〇S transistor becomes finer, the basic parameters such as threshold values caused by process variation as the size of the MS transistor becomes smaller. Evening fluctuations become large.

FIG. 12 schematically shows the delay time of the CMOS circuit and the variation width thereof with respect to the dimensions of the MOS transistor. In the design of the CM〇S integrated circuit, the delay time corresponding to the worst in Fig. 12 must be taken into account. Due to the increase in the fluctuation range, the delay time of the paste is limited even if the miniaturization is performed. Here, if the characteristic fluctuation can be suppressed and the delay time of the CMOS circuit can be adjusted to the typical or best, the circuit can be accelerated.

As a method of suppressing characteristic fluctuations in a circuit, Nikkei Electronix 7-28 (19997), pages 11-13 On the page, the leak current of the monitor circuit is measured, and the substrate bias is changed so that this current becomes a constant value. In addition, a technique is described in which the delay time of a replica circuit is measured to detect a change in the delay time and the power supply voltage is changed to suppress the characteristic fluctuation.

Nikkei Electronics 7 — 28- (1997) The technology described on pages 113 to 126 is used when the gate voltage is 0 V. The substrate bias is controlled so that the leakage current of the MOS transistor of the transistor becomes a constant value. Since the leakage current of the M〇S transistor rises as the temperature rises, the threshold value must be raised by applying board bias. In this case, the drawback is that the on-current of the MOS transistor drops significantly due to a decrease in mobility due to a rise in temperature and a rise in the threshold value, resulting in a decrease in circuit speed. is there . In addition, in order to generate a power supply voltage for delay time control, a filter including an inductor and a capacitor is formed outside the chip. Since it takes several seconds for the output voltage of the filter to stabilize, the control signal has a long stabilization time and tends to be unstable. As a result, control accuracy cannot be increased. If the capacitance inductance used for the filter is to be formed on the same chip as the controlled circuit, there is a problem that the area becomes large.

Also, in Japanese Patent Application Laid-Open No. 4-274653, a delay time detecting circuit is provided to suppress the variation of the delay time of the gate circuit, and the gate circuit is controlled based on the detection result. The concept of controlling the substrate bias is shown.

Further, in Japanese Patent Application Laid-Open No. 5-152935, a substrate bias is controlled using a capacitive filter or a charge pump to suppress the variation of the element and to reduce the number of steps. Concept to improve retention is shown Has been done.

Also, Japanese Patent Application Laid-Open No. 8-2746420 discloses that a circuit delay is detected using a reference clock signal, and a circuit bias of the circuit is controlled based on the detection result. The concept is shown.

Disclosure of the invention

An object of the present invention is to solve the above-mentioned problems of the prior art.

In other words, the inventors of the present invention have studied in detail the problem that would be a problem of applying the above-described conventional technology arbitration to an actual semiconductor integrated circuit device, and proposed the present invention. is there . SUMMARY OF THE INVENTION The present invention provides a semiconductor integrated circuit composed of MOS (MlS) h transistors, which suppresses the characteristic fluctuation of the CM 回路 S circuit with a short stable time and a small area. An object of the present invention is to provide a semiconductor integrated circuit capable of improving control accuracy and improving the operation speed of a main circuit.

In order to solve the above-mentioned problems, a semiconductor integrated circuit device according to a typical embodiment of the present invention includes a logic circuit for performing a predetermined process and a substrate via a MIS transistor constituting the logic circuit. And a board bias control circuit for supplying the power. The logic circuit is formed from the MIS transistor, and the substrate bias control circuit supplies a suitable substrate bias to the MIS transistor according to the characteristic variation of the logic circuit. Μ The threshold value of the IS transistor is changed by changing the substrate bias, the characteristic fluctuation of the logic circuit is suppressed, and the characteristic of the processing circuit is detected as a delay time. The change in delay time is converted into an amount of digital. In this case, the board bias control circuit can be constituted by a digital relay circuit, so that the control voltage stabilization time is short and the circuit scale is small. As a typical configuration example of the present invention, a logic circuit for performing predetermined processing and a substrate bias for controlling a threshold value of an i \ US transistor constituting a δ-booklet circuit are provided. It has a digital-to-analog conversion circuit that generates a signal, a voltage control circuit that outputs a control signal in response to the delay signal, and a delay detection circuit that can make the operation speed variable. -A clock signal is supplied from the controller to output a delay signal, and the voltage control circuit receives the delay signal of the delay detection circuit, outputs a control signal corresponding to the delay time, and outputs a digital signal. The analog conversion circuit is supplied with a control signal from the voltage control circuit and generates a voltage corresponding to the control signal, and the logic circuit and the delay detection circuit are supplied from the "serial-to-analog conversion circuit". The operating speed is controlled by voltage And it features.

In this example, since the main part of the control circuit is configured to handle digital signals, the circuit configuration is simple. It is also possible to divide the control circuit part into a chip different from the controlled circuit.

As a typical example of each circuit, the delay detection circuit is composed of a clock duty conversion circuit and a delay monitor circuit, the voltage control circuit is composed of a delay comparison circuit, and a digital analog circuit. The log conversion circuit is composed of a board bias generation circuit, and the clock duty conversion circuit receives a clock signal from the outside and receives a clock signal with an arbitrary duty ratio. It is output.

Further, as another example, the delay monitor circuit outputs the output signal of the clock duty conversion circuit with a fixed delay time, and the delay comparison circuit outputs the clock duty ratio. The delay time difference between the output signal from the conversion circuit and the delay module circuit is compared, and a signal corresponding to the difference is output.The substrate bias generation circuit outputs a signal corresponding to the substrate bias according to the output signal from the delay comparison circuit. And a logic circuit and The delay time of the delay monitor circuit is controlled by the substrate bias generated by the substrate bias generation circuit.

As another typical example, a delay detection circuit is composed of a frequency divider circuit and an oscillation circuit, a voltage control circuit is composed of a phase frequency detection circuit and a phase frequency control circuit, and a digital / analog conversion circuit is used. The external clock is supplied to a frequency divider, and the frequency is arbitrarily divided.The phase frequency detector detects the divided signal of the frequency divider and the output of the oscillator. The phase and frequency of the signals are compared to output an output signal corresponding to the difference, the phase frequency control circuit outputs a control signal according to the output signal of the phase frequency detection circuit, and the voltage generation circuit outputs a phase signal. A substrate bias is generated according to the control signal of the frequency control circuit, and the operation speed of the logic circuit and the oscillation circuit is controlled by the substrate bias generated by the voltage generation circuit.

Further, as a preferable example, there is an example in which the pMOS circuit and the nMOS circuit are separately controlled.

In other words, the delay detection circuit detects the change in the threshold value of the pMOS transistor and the PMOS delay detection circuit, and the nMOS delay detection circuit detects the change in the threshold value of the nMOS transistor. The voltage control circuit and the digital 'analog conversion circuit are respectively composed of two circuits for the pMOS transistor and nMOS transistor, and the pMOS transistor The operation speed of the PMOS delay detection circuit is controlled by the substrate bias for the pMOS transistor generated by the digital-to-analog conversion circuit for the transistor, and the nM〇S transistor The operating speed of the nM0S delay circuit is controlled by the nMOS transistor substrate bias generated by the digital to analog converter for the transistor.

In the present invention, the base of a transistor constituting a circuit is described. By controlling the plate bias, the threshold value of the transistor is controlled, thereby controlling the operation speed of the circuit. In this case, when the threshold value of the transistor decreases, the so-called threshold leakage current (gate-source leakage current) increases. To As a result of the increase in the leak current, the temperature of the circuit rises and the delay time of the circuit increases.

Therefore, when the delay time of the circuit is detected and the delay time is increased, when the control to reduce the threshold value of the transistor constituting the circuit and reduce the delay time is performed, If such a limit is not provided, the substrate bias will continue to be applied in the direction in which the threshold value decreases, and there is a risk that the circuit will eventually undergo thermal runaway.

Therefore, the present invention has a controlled circuit including at least one transistor and a control circuit for controlling a substrate bias of the transistor of the controlled circuit. In a semiconductor integrated circuit device that changes a threshold value of a transistor, a control circuit is configured by a limiter for controlling a substrate bias within a predetermined range. Suggest to do.

As an example, the limiter has a leak current detection circuit that detects the leak current of the transistor, and when the leak current increases beyond a certain value, the limiter of the control circuit is activated. The feature is to stop the substrate bias control.

When using a digital-to-analog conversion circuit that generates a board bias to control the threshold value of the MIS transistor that constitutes the logic circuit, the leakage current is constant. By configuring so that the output voltage of the digital-to-analog conversion circuit is fixed when the value exceeds the value, it is possible to limit the increase in the leak current.

Further, in the present invention, the substrate bias is controlled. Suggest a detailed sequence at the time.

That is, in the present invention, a circuit device having a controlled circuit including a transistor and a control circuit for dynamically controlling a substrate bias of the transistor is provided. It operates in the following order.

(1) Set the transistor bias of the transistor to a predetermined value. (2) Supply the power supply voltage to the transistor.

(3) Dynamic control of transistor bias in the transistor. At this time, the control circuit includes a monitor circuit that monitors the delay time of the controlled circuit, and a board bias generator that controls the board bias of the transistor based on a signal from the monitor circuit. You can have.

As a more specific example, a logic circuit that performs a predetermined process,

It has two voltage stabilization circuits, a control voltage stabilization detection circuit, a reset release circuit, and an operation / non-operation switching circuit.After the device is started, a substrate bias is supplied, and the first voltage stabilization is performed. The circuit supplies the power supply voltage after the substrate bias is stabilized, the second voltage stabilization circuit supplies a control signal to the semiconductor integrated circuit after the power supply voltage is stabilized, and the control voltage stability detection circuit supplies the control signal to the semiconductor integrated circuit. The reset output circuit detects the stability of the output voltage for control of the integrated circuit, and the reset release circuit sends a reset release signal to the logic circuit when the control voltage stability detection circuit detects stability, and resets the logic circuit. The operation and non-operation switching circuits are activated and disabled according to the operation and non-operation switching signals. , Malfunction of the logic circuit at startup or during operation It is characterized by preventing

With the increasing multifunctionality of integrated circuit devices, it is necessary to divide a circuit into multiple blocks and change the operating speed and operating voltage of each block. And may be valid.

Another embodiment of the present invention includes a logic circuit having at least first and second blocks, first and second operation speed control circuits, and a clock generation circuit. A different power supply voltage is supplied to the second block, and the first and second operating speed control circuits are adapted to operate in the blocks according to the power supply voltage supplied to the respective blocks. It is characterized by controlling the operation speed of a logic circuit.

Another embodiment of the present invention in which emphasis is placed on reducing the power consumption of the circuit includes a first controlled circuit block and a second controlled circuit block, each of which has a first controlled circuit block and a second controlled circuit block. A switch is provided in the controlled circuit, the power supply to the transistor included in the controlled circuit is controlled by the switch, and a control circuit is provided in each controlled circuit, and the control circuit is provided. Thereby, the substrate noise of the transistor included in the controlled circuit is controlled.

This switch is controlled by, for example, a mode switching signal, and when the circuit is stopped, the switch is turned off to reduce the leakage current of the FET in the circuit. Can be During the operation of the circuit, the threshold value of the FET is controlled by the dynamic control of the transistor substrate bias as described above, and the operation speed and power consumption of the circuit are reduced. Set to an appropriate value. For example, the control circuit detects the delay time of the controlled circuit, and controls the transistor bias of the transistor based on the detection result.

The voltage of the power supply supplied to each of the above-described controlled circuits may be configured to be different.

As for the layout of the circuit, the operating speed control circuit consists of a delay detection circuit and a control circuit, and the delay detection circuit is located inside the block to be controlled, especially in the center of the block. Like to arrange Then, the operating speed can be accurately detected.

According to another aspect of the present invention, there are provided a logic circuit for performing a predetermined process, an input / output circuit for transmitting a signal to a printed circuit, and an operation speed control circuit for controlling an operation speed of the circuit. The signal transmission speed of the input / output circuit is controlled by the operation speed control circuit. Specifically, the operating speed control circuit controls the substrate bias of the transistor that forms the input / output circuit, changes the threshold value, and controls the operating speed.

Other examples include a logic circuit that performs a predetermined process, a clock generation circuit that supplies a clock signal to the logic circuit, and an operation speed control circuit that controls the operation speed of the circuit. The clock generation circuit changes the frequency of the clock signal by the frequency control signal while the logic circuit is operating, and the operation speed control circuit responds to the change of the clock signal. Control the operating speed of the logic circuit.

Also, at least a logic circuit having first and second blocks, first and second operation speed control circuits, and a clock generation circuit are provided, and the first and second blocks are provided. The clock signals of different frequencies are supplied to the clocks, and the first and second operating speed control circuits block the clock according to the frequency of the clock signal supplied to each block. Control the operating speed of the logic circuits in the box.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of the embodiment of the present invention.

Figure 3 shows the clock duty conversion circuit diagram.

Figure 4 shows the output waveform of the clock duty conversion circuit.

Figure 5 shows the delay monitor circuit diagram.

Figure 6 shows the delay comparison circuit. Figure 7 is a circuit diagram of the substrate bias generation circuit.

Figure 8 shows the selector circuit diagram.

Figure 9 shows the selector circuit diagram.

Figure 10 is a lock detection circuit diagram.

Figure 11 is a standby circuit diagram.

Figure 12 shows the relationship between device dimensions and gate-delay time. Figure 13 shows the relationship between substrate bias and threshold voltage. Figure 14 shows the relationship between substrate bias and threshold voltage. Figure 15 shows the relationship between substrate bias and gate delay time. FIG. 16 is a configuration diagram of another embodiment of the present invention.

FIG. 17 is a configuration diagram of another embodiment of the present invention.

FIG. 18 is a configuration diagram of another embodiment of the present invention.

Figure 19 shows a digital-to-analog converter.

Figure 20 shows the relationship between threshold and leakage current.

FIG. 21 is a configuration diagram of another embodiment of the present invention.

FIG. 22 is a configuration diagram of another embodiment of the present invention.

Figure 23 is a divider circuit diagram.

Figure 24. Threshold control oscillation circuit diagram.

Fig. 25 Threshold control oscillation circuit diagram.

Figure 26 shows the threshold control oscillator circuit.

Figure 27 is a circuit diagram of the threshold control delay line.

Figure 28 shows the threshold control delay line circuit diagram.

Figure 29 is a phase frequency detection circuit diagram.

Figure 30 is a phase frequency control circuit diagram.

Figure 31 shows an up-down circuit diagram.

Figure 32 is a circuit diagram of a half adder.

Figure 33 is the full adder circuit diagram.

Figure 34 is a decoder circuit diagram. Figure 35 shows the voltage generator circuit diagram.

FIG. 36 is a block diagram of another embodiment of the present invention.

Figure 37 shows the operational amplifier circuit diagram.

Figure 38 shows the operational amplifier circuit diagram.

FIG. 39 is a block diagram of another embodiment of the present invention.

Figure 40 is the delay detection circuit diagram

Figure 4 1 shows the delay detection circuit diagram

Figure 42 shows the delay detection circuit diagram.

Figure 43 shows the delay detection circuit diagram.

FIG. 4 is a block diagram of another embodiment of the present invention.

FIG. 45 is a block diagram of another embodiment of the present invention.

Figure 46 is a leakage current detection circuit diagram.

FIG. 47 is a diagram showing the effect of the present invention.

FIG. 48 shows the effect of the present invention.

FIG. 49 shows the effect of the present invention.

FIG. 50 is a diagram showing the relationship between substrate bias and gate delay time. FIG. 51 is a diagram showing the configuration of another embodiment of the present invention.

Figure 52 is a circuit diagram of the board bias stability detection circuit.

Figure 53 shows the power supply voltage stability detection circuit diagram.

Figure 54 shows the lock detection circuit.

Figure 55 is the reset release circuit diagram.

FIG. 56 is a diagram showing the operation procedure of the present invention.

FIG. 57 is a diagram showing the operation procedure of the present invention.

FIG. 58 is a block diagram of another embodiment of the present invention.

FIG. 59 is a block diagram of another embodiment of the present invention.

FIG. 60 is a diagram showing a relationship between an application example of the present invention and required performance. FIG. 61 is a configuration diagram of another embodiment of the present invention.

FIG. 62 is a block diagram of another embodiment of the present invention. FIG. 63 is a configuration diagram of another embodiment of the present invention.

FIG. 64 is a configuration diagram of another embodiment of the present invention.

Figure 65 shows an example of the configuration of a microprocessor.

FIG. 6 is a block diagram of another embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the basic concept of the present invention. The main circuit LOG transmits a detection signal sig corresponding to the operation speed of the circuit to the substrate bias control circuit CNT. The board bias control circuit C NT supplies the board bias v bp for the p-channel type MOS FET and the board bias V bn for the n-channel MOS FET to the main circuit L OG. The main circuit LOG is composed of a MOS transistor, and is configured to control a threshold voltage by controlling the substrate noise of the MOS transistor. Has been done.

With such a configuration, even if the characteristics of the MOS transistor change due to temperature and power supply voltage fluctuations and the variation in the process of manufacturing the MOS transistor, By controlling the threshold voltage of the M0S transistor by controlling the substrate bias, it is possible to keep the operating speed constant at all times. In addition, the threshold value of the MOS transistor should be lowered to a value determined by the desired maximum leak current, and the main component should be controlled by the substrate bias control. By controlling the operation speed of the circuit to be constant, it is possible to substantially increase the speed. In addition, with this configuration, when the main circuit is in the operation stop mode, the threshold value of the main circuit is increased to reduce the leak current and reduce the power consumption. This is also possible.

Figure 20 shows the threshold of the MOS transistor and the leakage current. Show the relationship. In a standard M〇S transistor, the threshold value should be designed at point A so that the fluctuation range due to the process etc. does not exceed the limit of the desired leak current. I have to. In the present invention, by lowering the threshold value to point B and applying a substrate bias, the leak current limit can be maintained even if the threshold value changes. . FIG. 16 is a diagram showing another embodiment of the present invention. The main circuit LOG10 receives a clock signal c1k10 from the outside, and generates a detection signal siglO according to the operating frequency of the clock. The substrate bias control circuit CNT10 receives the detection signal siglO and supplies the substrate biases vbplO and vbnlO to the main circuit L0G10. The board bias control circuit CNT10 controls the board biases vbp10 and Vbn10 so that the operation speed of the main circuit LOG10 follows the change of the clock signal c1k10. To As a result, the operation speed of the main circuit can be changed according to the external clock.

FIG. 17 is a diagram showing another embodiment of the present invention. The main circuit L OG 20 outputs a detection signal sig 20 of circuit characteristics. The substrate bias control circuit CNT20 generates substrate biases vbp20 and vbn20 in response to the detection signal sig20. The substrate bias 20 and \ 1311 20 are supplied to the main circuit LOG 21 together with the main circuit LOG 20 for which the characteristic has been detected. With such a configuration, it is possible to suppress characteristic fluctuations of the main circuit LOG 20 and the main circuit LOG 21.

FIG. 18 is a diagram showing another embodiment of the present invention. As shown in the figure, when a plurality of main circuits LOG30 to LOG32 constitute one semiconductor integrated circuit LSI30, the control circuits CNT30 to CNT32 of this embodiment are used. Is installed for each main circuit As a result, local characteristic fluctuations inside the semiconductor integrated circuit can be suppressed, and power management for each local area is also possible.

FIG. 2 is a diagram showing a detailed example of the present invention. An external clock signal c1kOl is supplied to a clock duty ratio conversion circuit VCLK01. The clock duty ratio conversion circuit VCLK 0 1 generates a clock signal c 1 k 0 2 having a different duty ratio based on the clock signal c 1 k 0 1. . The delay monitor circuit DMON 0 1 receives the clock signal c 1 k 0 2 from the clock duty ratio conversion circuit VCLK 0 1 and has a predetermined delay time. Outputs delayed output signal inv O l. The delay comparison circuit CMP01 includes a clock signal c1k02 from the clock duty conversion circuit VCLK011 and a delay output signal i from the delay monitor circuit DMON01. Detects the phase difference from η ν θ 1, that is, the difference in delay time, and outputs an up 0 1 signal when the delay time is fast compared to a predetermined design value and outputs dw O 1 when the delay time is slow . The substrate bias generation circuit SBG01 generates two types of substrate bias, Vbp01 for the p-channel MOSFET and vbn01, the substrate bias for the n-channel MOSFET. There. Each time the up 0 1 signal is received from the delay comparator CMP 0 1, the substrate bias generation circuit SBG 0 1 raises the voltage of vbp O 1 by a predetermined voltage unit and raises the voltage of V bn 0 1 Decrease by specified voltage unit. Each time the delay comparator CMP01 receives the dwO1 signal once, the substrate bias generation circuit SBGO1 lowers the voltage of vbpO1 by a predetermined voltage unit, and reduces the voltage of vbn01. Increase in specified voltage units. This substrate bias is applied to the substrate of the MOSFET of the delay monitor circuit DMON01.

The delay monitor circuit DMON 01 is formed on a semiconductor substrate. And the n-channel MOSFET and the p-channel MOSFET, and the substrate bias of the M0 SFET changes according to the substrate bias signal from the substrate bias generation circuit SBG01. It is configured as follows. As described later, the configuration is such that the delay time is changed by changing the threshold voltage by changing the substrate bias.

When the delay time difference between the clock signal clk 0 2 and the delay output signal inv 0 1 becomes equal to a predetermined design value, the delay comparison circuit CMP 0 1 outputs both the up 0 1 signal and the dw O l signal. No output. When the output signal from the delay comparison circuit CMP 01 is no longer supplied, the board bias generation circuit SBG01 determines that the board bias voltage value has been determined and is determined. The applied substrate bias is applied to the substrate of the main circuit LOGO 1. Then, the threshold voltage is controlled by controlling the substrate bias of the MOS transistor.

With such a configuration, by controlling the substrate bias to control the threshold voltage of the MS transistor, the voltage is always constant even when the operating environment changes. It is possible to make the operation speed equal to. In addition, with this configuration, when the main circuit is in the operation stop mode, the threshold value of the main circuit is increased to reduce the leak current and reduce the power consumption. It is also possible to achieve this.

FIG. 3 is a diagram showing an embodiment of a clock duty conversion circuit. By combining flip-flops and AND gates, three types of clocks c 1 ka, c 1 kb, and c 1 k, with different phases from clock input c 1 k 11 clkc can be generated. Figure 4 shows the waveform of each clock signal.

FIG. 5 is a diagram showing an embodiment of the delay monitor circuit. The delay monitor circuit is a series connection of the INNO and IG. I At the beginning of the first stage, the clock output of the clock duty conversion circuit, clkb, is acquired. The output signals invb and inva are extracted from the last stage of the evening and the two stages before. Each inverter changes the threshold value by controlling the board bias by the board bias signals vbpl 1 and vbnl 1, and delays the signals inva, invb and the input signal c-1 kb. You can control the time difference.

FIG. 6 is a diagram illustrating an embodiment of the delay comparison circuit. It is composed of flip-flops and AND gates. Input the clock outputs clka, clkb, c1kc and the delay output signals inva, invb of the delay monitor circuit, and input the up11, dwll signals. Output . If the delay time of the delay monitor circuit is equal to the design value, the output of iη va and c 1 kb generates a signal, and the output of invb and c 1 kb is generated. G Output andl 2 does not generate a signal. At this time, no signal is output with both up 11 and d w l l. If the characteristics fluctuate due to process variations or environmental changes, and the delay time of the delay monitor circuit is shortened, an up11 signal is output. When the delay time of the delay monitor has become longer, a dw11 signal is output.

FIG. 7 is a diagram showing an embodiment of a substrate bias generation circuit. It consists of an AND gate, an OR gate, a flip-flop, a selector, and a digital-to-analog converter. The flip-flops form possible down-registration windows, and only the output at the down-registration location corresponding to the desired board bias is signaled.

Initially, an output signal is output from the center register output dff 15. Up 1 1 signal from delay comparison circuit and dw 1 One signal is received, and the output position of the register is up or down in accordance with the clock signal c 1 ka of the clock duty conversion circuit. In the digital-to-analog converter DAC 11, the substrate bias vbpll for the p-channel MOSFET and the n-channel MOSFET correspond to the output positions dff10 to dff19 in the register. For -substrate bias VBN 11 to generate. Each time the up 11 signal is received, the register output shifts the register evening position by one step in the direction of dff 10 and dff 19. When the dwll signal is received, the register output shifts by one step in the direction from dff 19 to dff 10. The board bias output changes the board bias by 0.2 V every time the register output power S changes by one step according to the Up11 signal. When the power supply voltage is 1.8 V, if the power supply voltages of —1.8 V and 3.6 V are supplied to DAC 11, the V bp 11 signal will be changed from 1.8 V power to 3.6 V. The vbn 11 signal can be generated from 0.0 V to 1.1 V at 0.2 V intervals.

If the delay time of the delay monitor circuit becomes faster than the design value, the board bias generation circuit receives the up 11 signal, so the register output becomes larger by one step, and the board bias is increased. Increases the Q by 0.2 V in V bpll and decreases by 0.2 V in vbnll, and applies this to the MOSFET substrate of the delay monitor circuit to delay the monitor delay time. If the delay time of the delay monitor circuit is longer than the design value, the board bias generation circuit receives the dw11 signal, and the register output becomes smaller by one step. The ass is reduced by 0.2 V at Vbp11 and increased by 0.2 V at vbn11, and this is applied to the MOSFET substrate of the delay monitor circuit. Increase the delay time.

FIG. 8 and FIG. 9 are diagrams showing the details of the selector inside the substrate bias generation circuit. The register sunset signal of the board bias generation circuit switches between the up and down directions according to the selector's se 1 ect 1 input signal.

Figure 19 shows the details of the digital-to-analog converter. Substrate biases vbp200 and Vbn200 corresponding to the register outputs dff20 to dfi29 are generated.

FIG. 10 shows an embodiment of the lock detection circuit. The board bias output of the board bias generation circuit is always applied to the M〇SFET board of the delay monitor circuit.However, if the characteristics of the delay monitor circuit fluctuate, the circuit will be closed until the board bias voltage is determined. The bias voltage changes every time. After the board bias is determined, a lock detection circuit may be inserted to apply the board bias for control of the main circuit. The output V bp 21 and vbn 21 of the digital-to-analog converter DAC 21 directly connected to the shift register evening output dff 10 to dff 19 in the board bias generation circuit is Connect to MOSFET board of delay monitor circuit. The lock detection circuit LCK11 receives shift register evening outputs dffl0 to dffl9, clka, u11, and dw11 signals, and outputs AND gate and flip-flop signals. It detects that the board bias voltage has locked through the flip-flop and transmits a signal to the digital-to-analog converter DAC 22. The digital-to-analog converter DAC 22 outputs the substrate biases vbp22 and vbn22, and controls the substrate bias of the MOSFET substrate of the main circuit.

FIG. 11 shows an embodiment of the standby circuit. When the main circuit is in the operation stop mode, the P-channel M〇SFET By maximizing the substrate bias and minimizing the substrate bias for n-channel MOSFETs, the leakage current can be reduced and the power consumption can be reduced. The board bias outputs vbp23 and vbn23 from the digital / analog converter DAC23 of the board bias generation circuit are formed as shown in the figure. The source of the pMOS is connected to the maximum substrate bias-Vch, and the source of the nMOS is connected to the minimum substrate bias Vs1. If the power supply voltage is 1.8 V, vch is 3.6 V and V s1 is 1.8 V. The operation stop signal stb 21 and the stb 20 signal having a phase opposite to that of stb 21 are supplied to the gates of p M 〇 S and n MOS.

Figures 13 and 14 show the relationship between the substrate bias voltage of the MOS transistor and the threshold voltage. Fig. 13 shows the case of nMOS, and Fig. 14 shows the case of pMOS. The threshold value of the MOS transistor varies depending on the board noise as shown in FIGS. 13 and 14. Therefore, when an nMOS transistor and a pM0S transistor are used to form a gate like an inverter, as shown in FIG. The larger the absolute value of the bias, the longer the delay time. From this, it is possible to keep the delay time of the CMOS circuit constant by controlling the substrate bias. If a CMOS circuit with the characteristics shown in Fig. 15 (I) is given the characteristics of (II) by lowering the threshold value in advance in the process, the substrate bias will be around 1.0 V. By raising and lowering the bias voltage around the center, the operating speed can be made faster or slower than in earlier CMOS circuits.

The delay time variation of the CMOS circuit is about 45% without any compensation. In the method of controlling the leak current constant, Since it cannot respond to changes in temperature, the variation in delay time is 60%, which is rather wide. In the method in which the delay time fluctuation is suppressed by power supply voltage control, the fluctuation width is kept to 36%. In contrast, according to the present invention, the delay time can be suppressed to 32%.

FIG. 21 is a diagram showing another embodiment of the present invention. The delay detection circuit MON001 receives the clock signal c 1 kOOl and outputs a delay signal. The voltage control circuit VCNT 001 generates a control signal control 1 for the digital-to-analog conversion circuit DACONV001 based on the delay signal as a 10-bit signal, for example. The digital-to-analog conversion circuit DACONV001 generates the pMOS transistor board bias vbpOOl and the nMOS transistor board bias vbnOOl in response to the control signal, and generates the delay detection circuit MON001 and the main circuit. Supply to LOGO 01. The delay detection circuit MONO01 can change the signal transmission delay time by the substrate bias vbpOOl and vbnOOl, and the voltage control circuit VCNT001 ensures that the delay time of the output signal of the delay detection circuit MONO01 is always constant. A control signal is generated such that a digital-to-analog conversion circuit DACONV001 generates such a substrate bias signal. As a result, the operation speeds of the delay detection circuit MONO 01 and the main circuit LOGO 01 are always constant.

FIG. 22 is a diagram showing a detailed example of the present invention. The delay detection circuit MONO 11 is composed of a divider circuit DIV011 and a threshold value controlled oscillator circuit VC0011. The frequency divider circuit DI V011 divides the frequency of the clock signal input clkOll and outputs a clock signal clk012. The threshold control oscillator circuit VCO011 can change its oscillation frequency with the board bias signals vbpOll and vbnOll and generates the oscillation output signal vcosigOll. The voltage control circuit VCNT011 and the phase frequency detection circuit PFD011 It is composed of a wave number control circuit PFCNT011. The phase frequency detection circuit PFD011 receives the output signal clkO of the divider circuit DIV011 and the oscillation output vcos igOll of the threshold control oscillator circuit VC0011, and detects the frequency difference and phase difference between the two signals. An up signal upO 11 or a down signal dwO 11 is generated according to the difference. The phase frequency control circuit PFCNT011 converts the up signal upOl1 and the down signal dwOl1 into, for example, a 10-bit control signal cnt011. The voltage generation circuit VG011 generates a pMOS transistor substrate bias vbpOll and an nMOS transistor substrate bias vbntHl in response to the control signal cntOl1, and generates a threshold value control oscillator circuit. Supply to the board of VC0011 and main circuit LOGO 11. The voltage control circuit VCNT011 controls the substrate bias so that the output vcos igOl1 of the threshold control oscillation circuit VC0011 is synchronized with the output clk012 of the frequency divider DIV011 in both frequency and phase. Therefore, the threshold-controlled oscillation circuit VC0011 and the main circuit L0G011 always show the same operation speed in response to the clock signal input c1k011.

FIG. 23 is a diagram showing an embodiment of the frequency dividing circuit. The dividing circuit DIV 012 is configured by connecting a plurality of D-type flip-flops (such as DFF 011) as shown in the figure. One D-type flip-flop generates the output signal clk014 by setting the frequency of the input clock signal c! K013 to 1Z2, and reducing the frequency of the input clock signal c! K013 to 1/4.

Figures 24, 25, and 26 are diagrams showing an embodiment of the threshold-controlled oscillation circuit. The threshold-controlled oscillation circuit can make the oscillation frequency variable by the board bias signals vbpO12, vbpO13, vbpO14, vbnOl2, vbnO13, and vbn014, and the clock signals vcos ig012 and vcos Output i gO 13, vcos ig014. VCO 012 is an example of an inverter circuit, VC0013 is a NAND circuit, and VC0014 is an example of a NOR circuit. FIG. 27 and FIG. 28 are diagrams showing embodiments of the threshold delay line. The delay comparison circuit in Fig. 5 can be configured in the same way as VCL011 and VCL012, even if a NAND circuit or NOR circuit is used.

FIG. 29 is a diagram showing an embodiment of the phase frequency detection circuit. The phase frequency detection circuit PFD012 detects the phase difference and frequency difference between the clock signal clk019 and the oscillation output vcosig015, and if the clock signal c1kO19 is advanced, the phase signal is detected. The signal upO12 is generated and the down signal dwOl2 is generated when the oscillation output vcosigO15 is advanced.

FIG. 30 is a diagram showing an embodiment of the phase frequency control circuit. The phase frequency control circuit PFCNT012 consists of an up-down converter UDC011 and a decoder DEC 011. Up'down count UDC011 receives the up signal upOl3, adds 1 to the output signal cnt012 in binary, and receives the down signal, decrements 1 and outputs the result of addition and subtraction by 4. It is output as a control signal cnt 012 of about a bit. The decoder DE C 011 decodes the control signal c n t 012 and generates a control signal c IU 013 of about 8 bits.

Figure 31 shows the configuration of the up / down event. D-type flip-flop DFF015, DFF016, DFF017, DFF018, T-type flip-flop TFF011, TFF012, TFF013, TFF014, TFF015, TFF016, TFF017, TFF018, Half calorie calculator HA011, full power Π It can be composed of the FA011, FA012, FA013 and AND gate, NAND gate and OR gate. When the up signal up014 is input, the count signal is added, and when the down signal dwO14 is input, the count signal is subtracted, and the 4-bit output signals cnt014, cntOl5, Outputs cntOl6, cnt017. The output signal is internally fed-in to limit the count. With this configuration, the asynchronous Up-down counter can be configured.

As shown in Fig. 32, the half adder HA012 can be configured, and as shown in Fig. 33, the full adder FA014 can be configured by combining the half adders HA013 and HA014.

The decoder can be configured as shown in Figure 34. Here, the 4-bit input signal cnt 0-18-021 is converted to an 8-bit output signal cnt022-029.

FIG. 35 is a diagram showing an embodiment of the voltage generation circuit. In addition to the digital-to-analog converter shown in Fig. 19, the voltage generator VG013 can be configured as shown in Fig. 35. The output voltage changes according to the input control signal cnt030 to (; nt037. To reduce the output impedance, connect the operational amplifier circuits 0PAMPP011, OPAMPN011, and resistors RFP and RFN to the output section. The output of this voltage generator VG013 is the board bias signals vbp018 and vbn018.

FIG. 36 is a diagram showing another embodiment of the present invention. The delay detection circuit MO ^: 012 inputs the clock signal c 1 kO 20 and outputs a delay signal. The voltage control circuit VCNT012 generates a control signal based on the delay signal and transmits it to the digital-to-analog conversion circuit DACONV011. The digital-to-analog converter DACO V011 generates board bias signals vbp019 and vbn019 in response to the control signal, and applies them to the board of the delay detection circuit MONO12. The operational amplifier circuits OPAMPPO12 and OPAMPN012 receive the board bias signal, output the board bias signals vbp020 and vbn020 at the same voltage as vbp and vbn, and apply them to the board of the main circuit LOG012. The delay detection circuit MONO12 can change the signal transmission delay time by the substrate bias vbpOl9 and vbnOl9, and the voltage control circuit VCNT01 always has the delay time of the output signal of the delay detection circuit MONO12. Constant and A control signal is generated such that a digital-to-analog conversion circuit generates such a substrate bias signal. As a result, the operation speeds of the delay detection circuit MONO 12 and main circuit LOGO 12 are always constant. When the circuit size of the main circuit L0G012 is large, it takes time for the board bias signals V bp020 and Vbn020 to stabilize. The output impedance of the operational amplifier circuits OPAMPP012 and OPAMPN012 is low. By inserting a low circuit, the stability of the board bias signal can be sped up. This operational amplifier circuit can also be inserted into the board bias vbp (H9, vbn019) for the delay monitor!

Figures 37 and 38 show examples of the operational amplifier circuit.

FIG. 39 is a view showing another embodiment of the present invention. The PM0S transistor evening delay detection circuit PMON041 can change the delay time by the pMOS transistor board bias signal vbp041, and the nMOS transistor delay detection circuit NM0N041 The delay time can be changed by the nMOS transistor evening substrate bias signal vbn041. The delay detection circuits PM0N041 and NMON041 each receive the clock signal clk041 and transmit the delay signal to the voltage control circuits VCNT041 and VCNT042. Output . The digital-to-analog converter circuits DAC0NV04 and DAC0-V042 generate a pMOS transistor substrate bias vbp041 and an nMOS transistor substrate bias vbn041 in response to the respective control signals. , Delay detection circuit PMON041, NMON041, and main circuit L0G041. The digital 'analog conversion circuit DACONV041 eliminates the change in delay time caused by the pMOS transistor, and the DAC0NV042 eliminates the change in delay time caused by the nMOS transistor. The main circuit LOG041 and the delay detection circuit PM0N041, Keep the operating speed of NMON04 constant. By controlling the delay time change of the pMOS transistor and the delay time change of the nMOS transistor independently, highly accurate substrate bias control becomes possible.

Figures 40 and 41 show the delay detection circuits for pMOS transistors. By configuring as shown in the figure, the change in delay time can be controlled by supplying the substrate bias Vbp042 and Vbp043 for the pMOS-transistor.

Figures 42 and 43 show the delay detection circuits for nMOS transistors. Similarly, the change in delay time can be controlled by supplying the nMOS transistor substrate vias vbn042 and vbn043.

FIG. 44 is a diagram showing another embodiment of the present invention. It consists of a delay time control circuit according to the embodiment of FIG. 2 and a leak current detection circuit LMT051. The leak current detection circuit receives the board biases vbp051 and vbn051 generated by the board bias generation circuit SBG051, detects the leak current of the circuit, and when the leak current increases beyond a certain value. Stop the board bias control so that the board bias does not change. Therefore, the leak current detection circuit LMT051 limits the increase in leak current due to board bias control, and prevents malfunctions due to thermal runaway of the circuit.

FIG. 45 is a view showing another embodiment of the present invention. It consists of a delay time control circuit according to the embodiment in Fig. 22 and a leak current detection circuit LMT052. The leak current detection circuit receives the board biases vbp052 and vbn052 generated by the voltage generation circuit VG051 and detects the leak current of the circuit. When the leak current increases beyond a certain value, the board bias control is performed. Stop and keep the substrate bias unchanged. Therefore, the leak current detection circuit LMT052 limits the increase of the leak current by the board bias control, Prevent malfunction due to thermal runaway and so on.

FIG. 46 is a diagram showing an embodiment of the leak current detection circuit. Insert between the up signals up055 and up056, in which the leakage current is increased by the board bias control. The limit value of the leak current due to the substrate bias vbp 053 for the pMOS transistor is determined by the diffusion layer width wn (H of the nMOS transistor. The limit value of the leakage current due to the substrate bias V bn 053 is determined by the width wpOl of the diffusion layer of the P.M0S transistor.

FIG. 47 is a diagram showing a method of applying the present invention. A typical CMOS device has a distribution as shown in Fig. 47 (a) due to factors such as the fabrication process, operating voltage, and operating temperature. The upper threshold for this distribution is determined by the lower limit of the operating speed, and the lower limit is determined by the maximum limit of the power consumption. When the present invention is applied to these devices, the spread of the performance distribution can be narrowed as shown by the shaded area. Regarding the control by the substrate bias, when the substrate bias is applied only in the reverse bias direction, the distribution concentrates on the higher threshold value, that is, the slower operating speed. . As shown in Fig. 47 (b), when the threshold value is set low in advance, the lower limit of the distribution exceeds the limit of power consumption. However, when the present invention is applied to this device, the distribution can be gathered in the shaded area, and the distribution of the device can be reduced without exceeding the power consumption limit. It can be set in the low operating speed and high operating speed range, and the circuit speed can be increased.

FIG. 48 is a diagram showing another application method of the present invention. As shown in Fig. 50, it is possible to operate by applying a substrate bias in the forward bias direction up to about 0.5V. When the present invention is applied by performing forward bias control, as shown in FIG. The CMOS device distribution can be converged to the position of the diagonal line where the threshold is low and the operation is fast. This can speed up the circuit.

FIG. 49 is a diagram showing another application method of the present invention. If the board bias control is used in both the reverse bias direction and the forward bias direction, the device distribution can be aligned to the design-center value like the hatched distribution. Therefore, the yield of devices can be improved.

FIG. 51 is a diagram showing another embodiment of the present invention. The delay time control circuit according to the embodiment of FIGS. 44 and 45, the board bias stability detection circuit VSTS061, the power supply voltage stability detection circuit VSTD061, the lock detection circuit LDT061, the reset release circuit RCN061, and the standby It is composed of the circuit STB061. According to this embodiment, the operation procedure of the semiconductor integrated circuit according to the present invention is determined. When the power switch is turned on, the board bias is supplied, and the board bias stability detection circuit VSTS061 determines the stability of the board bias potential and generates the board bias stabilization signal vbst061. The power supply voltage stability detection circuit VSTD061 supplies the power supply voltage when it receives the board bias stabilization signal vbst061, determines the power supply voltage stability, and generates the power supply voltage stabilization signal vdst061. By this procedure, the substrate bias is always supplied before the power supply, and the latch-up of the MOS transistor can be prevented. The clock signal c1k061 starts transmitting the clock signal to the control circuit when the power supply voltage stabilization signal Vdst061 is input. The lock detection circuit LDT061 receives the clock signal c1k062 input to the control circuit, the up signal up062 and the down signal dwO61 in the control circuit, and When the control signal becomes stable, the lock signal 1 ck 061 is output. The reset release circuit RCN061 has a lock signal 1 CKO61 and a power supply voltage stabilization signal. Receives vdst 061 and outputs reset release signal rst 061. The main circuit L0G061 releases the reset state by receiving the reset release signal rst061, and starts operation. This procedure prevents the main circuit LOG061 from malfunctioning.

The operation procedure of the present invention according to this embodiment is shown in FIGS. Figure 56 shows the processing procedure from the start of the system to the start of main circuit operation. Such a procedure may be formed by a D-type RAM, or may be formed as a wired ROM.

After the start of the system shown in process fcl, the maximum voltage is supplied to the pMOS substrate bias Vbp and the minimum voltage is supplied to the nM0S substrate bias Vbn as in process fc2. In process fc3, it is determined whether the substrate bias is stable, the state is waited for until it becomes stable, and after stabilization, the process proceeds to process fc4. After the substrate bias is stabilized, supply the power supply voltage in process fc4. In process fc5, it is determined whether the power supply voltage is stable, the state is waited for until the power is stabilized, and after stabilization, the process proceeds to process fc6. In process fc6, the board bias control is started, and it is determined whether the control signal is locked. If the control signal is not locked, process fc7 determines whether the leak current monitor has exceeded the limit of the leak current, and if not, continues process fc6. If the leak current exceeds the limit in process fc7, the limiter of the leak current is activated in process fc8, and the substrate bias control signal does not change any more. Move to fc9. If the board bias control signal locks within the limit of the leak current, the process shifts from process fc6 to process fc9. In process fc9, the reset is released and the operation of the main circuit is started. With this operation procedure, it is possible to prevent a latch-up in the MOS transistor at the start of operation, or malfunction of the circuit due to thermal runaway or the like. Figure 57 is a diagram showing the procedure for preventing malfunctions due to thermal runaway and the like during operation of the main circuit. After resetting is released by processing fel l and the operation of the main circuit is started, in process fc12, it is confirmed that the board bias control signal is always locked. If it is locked, it is determined in process fc15 whether a standby signal has been generated. If not, the process returns to process fc12. When the board bias signal is unlocked in process fc12, the leak current monitor in process fcl3 determines the limit of the leak current. If the limit is not exceeded, the process returns to process fc and the limit is returned. If it exceeds the limit, the limiter is activated in process fc14 to stop the change of the substrate bias control signal, and the process shifts to process fc15. When a standby signal is generated in process fc15, the process sets the pMOS substrate bias Vbp to the maximum value and the nMOS substrate bias to the minimum value in process fc16 to set the main circuit in the standby state. In addition, power consumption due to leakage current during standby is reduced.

Processing fcl7 detects the occurrence of an active signal and maintains the standby state until it is generated. When the active signal is generated, the standby state is released, the operation of the main circuit is resumed, and the process returns to fc12.

FIG. 52 is a diagram showing an embodiment of the substrate bias stability detection circuit. When the reset switch RSTS061 is released, the board bias voltage is charged to the capacitor C061 through the resistor R061. Vbp062 is the power supply. When this charge voltage exceeds a certain value, the buffer circuits BUF061 and BUF06 operate, and the board bias stabilization signal Vbst062 is generated.

FIG. 53 is a diagram showing an embodiment of the power supply voltage stability detection circuit. When the board bias stabilization signal vbst063 is received, the n-type M0S transistor is turned off, and the capacitor C062 is connected to the capacitor C062 through the resistor R062. The source voltage is charged. When this charging voltage exceeds a certain value, the buffer circuits BUF063 and BUG064 operate and the power supply voltage stabilization signal Vdst062 is generated.

FIG. 54 is a diagram showing an embodiment of the lock detection circuit. The clock signal clk063 is frequency-divided by the frequency divider DIV061, and is input as the clock signal of the D-type flip-flop DFF061. Also, by taking the NOR of the up signal up 063 and the down signal dw063 and taking it in as the DFF061 data overnight signal, both the up signal and the down signal are not generated. When this happens, the lock signal lck062 is generated.

FIG. 55 is a diagram showing an embodiment of the reset release circuit. The reset release circuit RCN062 receives the lock signal lck063 and the power supply voltage stabilization signal Vdst063, and generates the reset release signal rst062. In the state where there is no input signal before the operation of the system and the state where only the power supply voltage stabilization signal Vdst063 is generated, the reset release signal rst062 is low to maintain the reset state. At that level, when the lock signal 1cko63 is generated after that, rst062 goes high and the reset is released. Once released, the reset release signal r st 062 is maintained at a low level until the system stops, and is not reset.

FIG. 58 is a diagram showing another embodiment of the present invention. By controlling the operating speed of the I / O circuit 10071 using the speed control board bias signal vbb071 by the operating speed control circuit DCNT071, external I / O to the I / O circuit IO071 is possible. It controls the signal transmission speed of signal sig072 and signal sig072 from input / output circuit 10071 to main circuit LOG071. The signal to the input / output circuit 10071 may have a difference in signal transmission speed due to the difference in voltage.Rise speed and fall in the signal transition of force 10071 By keeping the speed constant, the speed difference can be eliminated. Another significance of this embodiment is that the operation speed of the input / output circuit can be controlled independently of the main circuit. If the operation speed of the external circuit is slow, it does not make sense to operate earlier, so the board bias of the input / output circuit is controlled separately from the main circuit. It is possible to increase the threshold value of the transistor constituting the part and to reduce the power consumption due to leak current instead of limiting the operation speed.

FIG. 59 is a diagram showing another embodiment of the present invention. The clock generation circuit CPG081 can make the frequency of the generated clock signal clk081 variable by the control signal cnt081. The operating speed control circuit DCNT081 generates a board bias control signal vbb081 corresponding to the frequency of the clock signal c1kO81 and supplies it to the main circuit LOG081. As a result, the main circuit LOG081 can operate at an optimum speed in response to changes in the clock signal clk081 generated by the clock generation circuit CPG081. As shown in Fig. 60, the signal processing performed by the main circuit L0G081 differs in the processing speed and performance required according to the purpose of use, and the operating speed varies according to the purpose of use. By doing so, power consumption can be reduced.

FIG. 61 is a diagram showing another embodiment of the present invention. The clock signal clk091 generated by the clock generation circuit CPG091 is frequency-divided by frequency dividers DIV091, DIV092, DIV093, etc., and clock signals clk092, c of different frequencies are generated. This produces lk 093 and clk094. The operation speed control circuits DCNT091, DCNT092, and DCNT093 receive the clock signals clk092, clk093, and c1k094, respectively, so that the optimal circuit board for each clock frequency can be obtained. Generates bias signals vbb091, vbb 092, and vbb 093, and controls the operating speed of the main circuits LOG091, LOG092, and LOG093. Within a system, certain processes are organized Each block can be operated at a different processing speed.

Figure 65 shows an example of block division in the system. For example, regarding the LCD panel controller LCD block, depending on the resolution of the LCD panel, The processing speed of the trolley block can be changed. —Power consumption can be reduced by appropriately adjusting the operating state (active state) and the non-operating state (standby state) by means of blocks.

FIG. 62 shows another embodiment of the present invention. The operation speed control circuits DCNT101, DCT102, and DCNT103, which have received the clock signal clkl Ol of the clock generation circuit CPG101, switch the board according to the respective power supply voltages vddlOl, vddl02, and vddl03. The assembler signals vbblOl, vbbl02, and vbbl03 are generated, and power is applied to the main circuits LOG101, L0G102, and LOG103. Since the main circuit LOG10 and L0G102, LOG103 are supplied with different power supply voltages V dd 1 (H, vddl 02, vdd 103), they can operate by receiving a substrate bias that is optimal for each operation speed. If different power supply voltages are applied to each block having a certain processing in one system, optimal board bias control is performed for each main circuit that constitutes the block. be able to.

Figure 63 is an extension of Figure 62. As shown in Fig. 63, switches M0S, SW104, SW105, and SW106 are provided in each main circuit, and these switches are turned off at the time of standby or the like. In addition, it is possible to reduce power for each block. If the design is such that the leakage current of the switching FET is smaller than the sum of the leakage currents of the FETs in the block, the leakage current during standby, etc. The effect of reducing the peak current can be obtained. For example, a switch can be composed of a high threshold MOS FET. FIG. 64 is a diagram showing another embodiment of the present invention. In the main circuit L0G111, which is one of the blocks having a certain processing unit, the delay detection circuit M0N111, especially the operation speed control circuit DCNT111, is laid out in the center of the block. By doing this, the delay detection circuit MON111 can be designed to represent the operating characteristics of the block.

FIG. 66 is a diagram showing another embodiment of the present invention. In the main circuit L0G121, the delay detection circuit M0N121 and the voltage control circuit VCNT121 among the operation speed control circuits are formed, and the digital-to-analog conversion circuit DAC0NV121 that generates the control voltage is created on a different chip. Can be. This reduces the number of circuits that must be configured in the main circuit among the operating speed control circuits, and reduces the area and power consumption.

Industrial applicability

As described above, according to the present invention, by controlling the threshold value of the MOS transistor constituting the circuit, it is possible to suppress the characteristic fluctuation of the CMOS circuit and improve the operation speed. And By reducing the threshold value of the MOS transistor in advance in the process, the effect of speed improvement will be greater. The control circuit can be configured with a digital circuit to digitize and detect the characteristic fluctuation amount, and the stabilization time of the control signal can be shortened. Further, since the control circuit can be formed with a small circuit scale, a plurality of control circuits can be arranged in a semiconductor integrated circuit whose threshold value is to be controlled, and local characteristic fluctuation can be suppressed. In addition, power management for each local area of the semiconductor integrated circuit becomes possible.

Claims

The scope of the claims

1. A logic circuit that performs predetermined processing, a digital-to-analog conversion circuit that generates a board bias for controlling a threshold value of an MIS transistor that constitutes the logic circuit, and a delay It has a voltage control circuit that outputs a control signal in response to a signal, and a delay detection circuit that can change the operation speed, and a clock signal is supplied to the delay detection circuit from the outside. The voltage control circuit receives the delay signal of the delay detection circuit and outputs a control signal corresponding to the delay time, and the digital / analog conversion circuit outputs the voltage control signal. A control signal is supplied from the circuit to generate a voltage corresponding to the control signal, and the logic circuit and the delay detection circuit operate by the voltage supplied from the digital-to-analog conversion circuit. Speed controlled And a semiconductor integrated circuit device.

2. The delay detection circuit is composed of a clock duty conversion circuit and a delay monitor circuit, the voltage control circuit is composed of a delay comparison circuit, and the digital-to-analog conversion circuit is a circuit board. The clock duty conversion circuit receives a clock signal from the outside and outputs a clock signal having an arbitrary duty ratio. The output signal of the clock duty conversion circuit is output with a certain delay time, and the delay comparison circuit delays the output signals of the clock duty conversion circuit and the delay monitor circuit. The time difference is compared, and a signal corresponding to the difference is output. The board bias generating circuit generates a board bias according to the output signal of the delay comparing circuit, and outputs the logic circuit and the delay monitor. 2. The semiconductor integrated circuit according to claim 1, wherein the delay time of the circuit is controlled by a substrate bias generated by the substrate bias generation circuit. Road equipment.

3. The delay detection circuit is composed of a frequency dividing circuit and an oscillation circuit, the voltage control circuit is composed of a phase frequency detection circuit and a phase frequency control circuit, and the digital / analog conversion circuit is a voltage generation circuit. The external clock is supplied to the frequency dividing circuit to arbitrarily divide the frequency thereof.- The phase frequency detecting circuit outputs the divided signal of the frequency dividing circuit and the output signal of the oscillation circuit. The phase and frequency are compared to output an output signal according to the difference, the phase frequency control circuit outputs a control signal according to the output signal of the phase frequency detection circuit, and the voltage generation circuit outputs A board bias is generated in response to a control signal of a phase frequency control circuit, and the operation speed of the logic circuit and the oscillation circuit is controlled by the board bias generated by the voltage generation circuit. Features 2. The semiconductor integrated circuit device according to claim 1, wherein:

4. The above-mentioned delay detection circuit detects the threshold value change of the pM〇S transistor and the PMOS delay detection circuit and the nMOS transistor detects the threshold value change of the nMOS transistor. The voltage control circuit and the digital-to-analog conversion circuit are each composed of two circuits, one for the pMOS transistor and one for the nMOS transistor, respectively. The operation speed of the PMOS delay detection circuit is controlled by the substrate bias for the pMOS transistor generated by the digital-to-analog conversion circuit for the pM0S transistor, and The operating speed of the nM0S delay circuit is controlled by the nMOS transistor substrate bias generated by the M0S transistor digital-to-analog conversion circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein:

5. Logic circuit that performs predetermined processing and MIS that constitutes the logic circuit A digital-to-analog conversion circuit that generates a substrate bias for controlling the threshold value of the transistor, a voltage control circuit that outputs a control signal in response to a delay signal, and a variable operation speed A clock signal is supplied from the outside to the delay detection circuit, and a delay signal is output.The voltage control circuit receives the delay signal of the delay detection circuit and delays the delay signal. The digital / analog conversion circuit receives a control signal from the voltage control circuit to generate a voltage corresponding to the control signal, and outputs a voltage corresponding to the control signal. The delay detection circuit has a semiconductor integrated circuit whose operation speed is controlled by a voltage supplied from the digital / analog conversion circuit, and a leakage current detection circuit. Night The leak current is controlled by the voltage supplied from the analog-to-analog conversion circuit, and when the leakage current increases to a certain value or more, the output voltage of the digital-to-analog conversion circuit is fixed. Thus, a semiconductor integrated circuit device is characterized in that it limits the increase in leakage current.

6. It has a logic circuit that performs predetermined processing, two voltage stabilization circuits, a control voltage stability detection circuit, a reset release circuit, and an operation / non-operation switching circuit. The first voltage stabilization circuit supplies a power supply voltage after the substrate bias is stabilized, and the second voltage stabilization circuit supplies a control signal to the semiconductor integrated circuit after the power supply voltage is stabilized. The control voltage stability detection circuit detects the stability of the control output voltage of the semiconductor integrated circuit, and the reset release circuit resets the logic circuit when the control voltage stability detection circuit detects the stability. A reset release signal is sent to release the reset state of the logic circuit and start operation. The operation / non-operation switching circuit operates / non-operates. Switching the control of the semiconductor integrated circuit between valid and invalid in response to an operation switching signal, thereby preventing a malfunction of the logic circuit at startup or during operation. The semiconductor integrated circuit device according to claim 5.

7. A logic circuit for performing predetermined processing, an input / output circuit for transmitting a signal to the logic circuit, and an operation speed control circuit for controlling the operation speed of the circuit to be constant. A semiconductor integrated circuit device characterized in that a signal transmission speed is controlled by the operation speed control circuit so as to be constant.

8. A logic circuit for performing predetermined processing, a clock generation circuit for supplying a clock signal to the logic circuit, and an operation speed control circuit for controlling the operation speed of the circuit, The clock generation circuit changes the frequency of the clock signal by the frequency control signal while the logic circuit is operating, and the operation speed control circuit responds to the change of the clock signal by the operation speed control circuit. A semiconductor integrated circuit device which controls an operation speed of a logic circuit.

9. At least a logic circuit having first and second blocks, first and second operation speed control circuits, and a clock generation circuit, wherein the first and second blocks are provided. The clock signals of different frequencies are supplied to the blocks, and the first and second operation speed control circuits described above correspond to the frequencies of the clock signals supplied to the respective blocks. A semiconductor integrated circuit device characterized by controlling the operation speed of a logic circuit in a block.

10. A logic circuit having at least first and second blocks, first and second operation speed control circuits, and a clock generation circuit. Different power supply voltages are supplied to the blocks, and the first and second operation speed control circuits described above operate in accordance with the power supply voltage supplied to the respective blocks. A semiconductor integrated circuit device, characterized by controlling the operation speed of a logic circuit in a semiconductor device.

11.A logic circuit having at least first and second blocks and first and second operation speed control circuits, and the operation speed control circuit is provided by a delay detection circuit and a control circuit. A semiconductor integrated circuit device, wherein each delay detection circuit is configured so as to be arranged at the center-center in a corresponding block.

12. A controlled circuit including at least one transistor, and a control circuit for controlling a substrate bias of a transistor of the controlled circuit. In a semiconductor integrated circuit device for changing a threshold value of a transistor, the control circuit has a limiter for controlling the substrate bias within a predetermined range. Semiconductor integrated circuit device.

13 3. The limit circuit has a leak current detection circuit that detects the leak current of the transistor, and when the leak current exceeds a certain value, the control circuit 13. The semiconductor integrated circuit device according to claim 12, wherein the control of the substrate bias is stopped.

14. A circuit device having a controlled circuit including a transistor and a control circuit for dynamically controlling the substrate bias of the transistor, wherein the circuit device includes: A circuit device characterized by operating in the following order.

(3) Dynamic control of transistor bias

15. The control circuit includes a monitor circuit that monitors the delay time of the controlled circuit, and a board via that controls a board bias of the transistor based on a signal from the monitor circuit. S The circuit device according to claim 14, further comprising a generator.

16. The circuit device according to claim 14, further comprising a limiter circuit for stopping the dynamic control.

17. The circuit device according to claim 16, wherein the limiter circuit is a circuit that monitors a leak current of the transistor.

18. There is a first controlled circuit block and a second controlled circuit block,

A switch is provided in each of the controlled circuits, and the switch controls the supply of power to a transistor included in each of the controlled circuits, and

A semiconductor integrated circuit device, wherein a control circuit is provided in each of the controlled circuits, and the control circuit controls a substrate bias of a transistor included in each of the controlled circuits.

19. The semiconductor integrated circuit device according to claim 18, wherein a voltage of a power supply supplied to each of the controlled circuits is different.

20. The control circuit according to claim 18, wherein the control circuit detects a delay time of the controlled circuit, and controls a substrate bias of the transistor based on a result of the detection. 9. The semiconductor integrated circuit device according to item 9.