KR100597447B1 - Semiconductor integrated circuit device - Google Patents

Abstract

A logic circuit LOG001 that performs a predetermined process, a digital-analog converter circuit DACONV001 that generates a substrate bias for controlling the threshold of the MIS transistors constituting the logic circuit, and a voltage that outputs a control signal in accordance with a delay signal. It has a control circuit VCNT001 and a delay detection circuit MON001 that can change the operation speed. The delay detection circuit is supplied with a clock signal clk001 from the outside to output a delay signal, and the voltage control circuit detects the delay. The delay signal of the circuit is input to output a control signal according to the delay time. The digital-analog conversion circuit supplies the control signal from the voltage control circuit to generate a voltage corresponding to the control signal. The logic and delay detection circuits are digital. The operation speed is controlled by the voltage supplied from the analog converter circuit.

Description

Semiconductor integrated circuit device

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit device suitable for high speed operation.

This application is a partial application of Patent Application 08 / 622,389 (March 27, 1996) in the United States of America, the disclosure of which is part of the present application.

In an integrated circuit using a CMOS transistor, there is a variation in characteristics due to variations in the dimensions of transistors due to the manufacturing process, environmental changes such as temperature during operation and power supply voltage.

Symposium on V.L.S.Technology Digest of Technical Papers, June 1994 The fluctuation of the basic parameter is large.

Fig. 12 schematically shows the delay time of the CMOS circuit and its variation with respect to the dimensions of the MOS transistor. In the design of a CMOS integrated circuit, a delay time corresponding to the worst of FIG. 12 must be considered. By increasing the fluctuation range, the delay time of the wort is limited even by the speed reduction. Here, if the characteristic variation can be suppressed and the delay time of the CMOS circuit can be adjusted to the peak or the peak, the circuit can be accelerated.

As a method of suppressing characteristic variations in circuits, the leakage current of the monitor circuit is measured on pages 113 to 126 of Nikkei Electronics 7-28 (1997), and the current is maintained at a constant value. The substrate bias is changing. In addition, a technique of suppressing the characteristic variation by measuring the delay time of the replica circuit, detecting the change in the delay time, and changing the power supply voltage is described.

The technique described in Nikkei Electronics 7-28 (1997) on page 113 to page 126 controls the substrate bias so that the leakage current of the MOS transistor when the gate voltage is 0V is constant. Since the leakage current of the MOS transistor rises with increasing temperature, a threshold must be raised by biasing the substrate. In this case, the on-state current of the MOS transistor is remarkably lowered due to the decrease in mobility due to the temperature rise and the increase in the threshold, and as a result, the speed of the circuit decreases. In addition, in order to generate a power supply voltage for controlling the delay time, a filter having an inductance and a capacitance is formed outside the chip. Since the output voltage of the filter stabilizes for several μs, the settling time of the control signal is long and tends to be unstable. For this reason, control precision cannot be raised. If the capacitance and inductance used for the filter are to be formed on the same chip as the controlled circuit, there is a problem that the area becomes large.

In addition, Japanese Patent Application Laid-Open No. 4-247653 discloses the concept of providing a delay time detection circuit and controlling the substrate bias of the gate circuit based on the detection result in order to suppress the variation in the delay time of the gate circuit.

In addition, Japanese Patent Application Laid-Open No. Hei 5-152935 discloses a concept of controlling substrate bias by using a capacitive filter or a charge pump, suppressing variations in devices, and improving yield.

Further, Japanese Patent Application Laid-Open No. Hei 8-274620 discloses a concept of detecting a delay amount of a circuit using a reference clock signal and controlling a substrate bias of the circuit based on the detection result.

<Start of invention>

An object of the present invention is to solve the above problems of the prior art.

That is, the inventors of the present application examine in detail the problem that will be a problem when the prior art is applied to a real-world semiconductor integrated circuit device, and propose the present invention. In the semiconductor integrated circuit constituted by the MOS (MIS) transistor, the present invention suppresses the characteristic variation of the CMOS circuit with a short settling time and at the same time, increases the control precision and improves the operation speed of the main circuit. It is to provide a semiconductor integrated circuit capable of.

In order to solve the above problems, a semiconductor integrated circuit device according to a representative embodiment of the present invention comprises a logic circuit for performing a predetermined process and a substrate bias control circuit for supplying a substrate bias to a MIS transistor constituting the logic circuit. It features. The logic circuit is formed of a MIS transistor, and the substrate bias control circuit supplies a suitable substrate bias to the MIS transistor in accordance with the variation of the characteristics of the logic circuit. The threshold of the MIS transistor is changed by changing the substrate bias, and the variation of the characteristics of the logic circuit is suppressed. The characteristic of the logic circuit is detected as the delay time, and converts the amount of change in the delay time into a digital amount. As a result, the substrate bias control circuit can be constituted by a digital circuit, so that the settling time of the control voltage is short and the circuit size is also small.

As a typical structural example of this invention, the logic circuit which performs a predetermined process, the digital-analog conversion circuit which produces the board | substrate bias for controlling the threshold of the MIS transistor which comprises a logic circuit, and the voltage which outputs a control signal according to a delay signal It has a control circuit and a delay detection circuit that can vary the operation speed, the clock signal is supplied to the delay detection circuit from the outside to output the delay signal, and the voltage control circuit inputs the delay signal of the delay detection circuit to delay time. And a control signal supplied from the voltage control circuit to generate a voltage corresponding to the control signal, and the logic circuit and the delay detection circuit to the voltage supplied from the digital analog conversion circuit. It is characterized by controlling the operation speed.

In this example, since the main part of the control circuit is configured to handle digital signals, the circuit configuration is simple. It is also possible to divide the control circuit portion into chips different from the controlled circuit.

As a typical example of each circuit, the delay detection circuit consists of a clock duty conversion circuit and a delay monitor circuit, the voltage control circuit consists of a delay comparison circuit, and the digital and analog conversion circuit consists of a substrate bias generation circuit. Is a clock signal of an arbitrary duty ratio and receives a clock signal from the outside.

As another example, the delay monitor circuit outputs the output signal of the clock duty conversion circuit with a constant delay time, and the delay comparison circuit compares the delay time difference between the output signal of the clock duty conversion circuit and the delay monitor circuit and compares the signal according to the difference. The substrate bias generation circuit generates a substrate bias according to the output signal of the delay comparison circuit, and the delay time is suppressed by the substrate bias generated by the substrate bias generation circuit.

As another typical example, the delay detection circuit consists of a frequency divider circuit and an oscillation circuit, the voltage control circuit consists of a phase frequency detection circuit and a phase frequency control circuit, the digital-analog conversion circuit consists of a voltage generator circuit, and the external clock The frequency is supplied to the frequency divider circuit, and the frequency is arbitrarily divided. The phase frequency detection circuit compares the phase and frequency of the frequency divider signal of the frequency divider circuit and the output signal of the oscillator circuit, and outputs the output signal according to the difference. The control signal is output in accordance with the output signal of the frequency detection circuit, the voltage generation circuit generates a substrate bias in accordance with the control signal of the phase frequency control circuit, and the logic and oscillation circuits operate by the substrate bias generated by the voltage generation circuit. To control the speed.

In addition, as a preferable example, there is an example in which the pMOS circuit and the nMOS circuit are respectively controlled.

That is, the delay detection circuit is composed of a pMOS delay detection circuit that detects a threshold change of a pMOS transistor and an nMOS delay detection circuit that detects a threshold change of an nMOS transistor, and a voltage control circuit and a digital-analog conversion circuit are used for a pMOS transistor and an nMOS, respectively. An nMOS transistor composed of two circuits for transistors, a pMOS transistor substrate bias in which a digital-to-analog conversion circuit for a pMOS transistor is generated, the operation speed of the pMOS delay detection circuit is controlled, and a digital-to-analog conversion circuit for an nMOS transistor is generated. The operating speed of the nMOS delay circuit is controlled by the substrate bias.

In the present invention, the threshold of the transistor is controlled by controlling the substrate bias of the transistor constituting the circuit, thereby controlling the operating speed of the circuit. When the threshold of the transistor is lowered here, the so-called sub-threshold leakage current (leak current between gate sources) increases. As a result of the increase in the leakage current, the temperature of the circuit rises and the delay time of the circuit increases.

Therefore, when the delay time of the circuit is detected and the control is performed to reduce the delay time by lowering the threshold value of the transistor that envisions the circuit when the delay time is increased, the threshold value is lowered if no limiter is provided. There is a risk that the substrate bias will continue to be applied and the circuit will eventually reach thermal runaway.

Thus, in the present invention, in a semiconductor integrated circuit device having a controlled circuit including at least one transistor and a control circuit for controlling the substrate bias of the transistor of the controlled circuit, the control circuit is a substrate. It is proposed to configure the device by a limiter for controlling the bias within a predetermined range.

As an example, the limiter has a leak current detection circuit for detecting a leak current of the transistor, and the substrate bias control of the control circuit is stopped when the leak current increases above a certain value.

When using a digital-analog conversion circuit that generates a substrate bias for controlling the threshold of the MIS transistor constituting the logic circuit, the output voltage of the digital-analog conversion circuit is fixed when the leakage current increases above a certain value. This can limit the increase in the leakage current.

In addition, the present invention proposes a detailed sequence when controlling the substrate bias.

That is, in the present invention, in a circuit device having a controlled circuit including a transistor and a control circuit for dynamically controlling the substrate bias of the transistor, the circuit device operates in the following order.

(1) The substrate bias of the transistor is set to a predetermined value.

(2) Supply a power supply voltage to the transistor.

(3) The substrate bias of the transistor is dynamically controlled.

At this time, the control circuit may have a monitor circuit for monitoring the delay time of the controlled circuit and a substrate bias generator for controlling the substrate bias of the transistor based on a signal from the monitor circuit.

As a more specific example, it has a logic circuit which performs a predetermined process, two voltage stabilization circuits, a control voltage stability detection circuit, a reset release circuit, and an operation / non-operation switching circuit, and a substrate bias is supplied after the device is started. The voltage stabilization circuit of the circuit supplies the power supply voltage after the substrate bias is stabilized, and the second voltage stabilization circuit supplies the control signal to the semiconductor integrated circuit after the power supply voltage is stabilized, and the control voltage stability detection circuit is the output for controlling the semiconductor integrated circuit. When voltage stability is detected, the reset release circuit sends a reset release signal to the logic circuit when the control voltage stability detection circuit detects stability, releases the reset state of the logic circuit, and starts operation. The operation / non-operation switching circuit operates. • By switching the effective invalidation of the control of the semiconductor integrated circuit in accordance with the non-operational switching signal, It is characterized by preventing a malfunction.

As the integrated circuit device becomes more versatile, there are cases where it is effective to divide the circuit into a plurality of blocks and to change the operation speed and the operating voltage of each block.

Another aspect of the present invention has a logic circuit having at least first and second blocks, first and second operating speed control circuits, and a clock generation circuit, wherein different power supply voltages are supplied to the first and second blocks. The first and second operating speed control circuits control the operating speeds of the logic circuits in the blocks according to the power supply voltages supplied to the respective blocks.

In addition, another aspect of the present invention focused on reducing power consumption of a circuit includes a first controlled circuit block and a second controlled circuit block, and a switch is provided in each controlled circuit, and controlled by the switch. It is characterized in that the supply of power to the transistors included in the circuit is controlled, the control circuit is provided in each controlled circuit, and the substrate bias of the transistor included in the controlled circuit is controlled by the control circuit.

This switch is controlled by, for example, a mode switching signal, and the switch is turned off when the circuit is stopped, thereby reducing the leakage current of the FET in the circuit. In the operation of the circuit, the threshold of the FET is controlled by the dynamic control of the substrate bias of the transistor as described above, and the operating speed and power consumption of the circuit are set to appropriate values. For example, the control circuit detects the delay time of the controlled circuit and controls the substrate bias of the transistor based on the detection result.

The power supply voltages supplied to the respective controlled circuits may be configured to be different.

As the layout of the circuit, the operation speed control circuit is composed of a delay detection circuit and a control circuit, and the delay detection circuit can be accurately detected within the block to be controlled, particularly as far as possible.

Another aspect of the present invention includes a logic circuit for performing a predetermined process, an input / output circuit for performing signal transmission to the logic circuit, and an operation speed control circuit for controlling the operation speed of the circuit, wherein the input / output circuit is operated by an operation speed control circuit. Signal transmission speed is controlled. Specifically, the operation speed control circuit controls the substrate bias of the transistors constituting the input / output circuit, changes its threshold, and controls the operation speed.

Another embodiment includes a logic circuit for performing a predetermined process, a clock signal generation circuit for supplying a clock signal to the logic circuit, and an operation speed control circuit for controlling the operation speed of the circuit. The frequency of the clock signal is changed by the frequency control signal, and the operation speed control circuit controls the operation speed of the logic circuit in response to the change of the clock signal.

It also has a logic circuit having at least first and second blocks, a first and second operating speed control circuit and a clock generation circuit, the first and second blocks being supplied with clock signals of different frequencies, The first and second operating speed control circuits control the operating speed of the logic circuit in the block according to the frequency of the clock signal supplied to each block.

1 is a block diagram of an embodiment of the present invention,

2 is a detailed configuration diagram of an embodiment of the present invention;

3 is a clock duty conversion circuit diagram;

4 is an output waveform diagram of a clock duty conversion circuit;

5 is a delay monitor circuit diagram;

6 is a delay comparison circuit diagram;

7 is a substrate bias generation circuit diagram;

8 is a selector circuit diagram;

9 is a selector circuit diagram;

10 is a lock detection circuit diagram;

11 is a standby circuit diagram;

12 is a relationship diagram between device dimensions and gate delay time;

13 is a relation diagram of a substrate bias and a threshold voltage;

14 is a relation diagram of a substrate bias and a threshold voltage;

15 is a diagram illustrating a relationship between a substrate bias and a gate delay time;

16 is a configuration diagram of another embodiment of the present invention;

17 is a configuration diagram of another embodiment of the present invention;

18 is a configuration diagram of another embodiment of the present invention;

19 shows a digital-analog converter;

20 is a relation diagram of a threshold value and a leakage current;

21 is a block diagram of another embodiment of the present invention;

22 is a configuration diagram of another embodiment of the present invention;

23 is a dividing circuit diagram;

24 is a threshold control oscillation circuit diagram;

25 is a threshold control oscillation circuit diagram;

26 is a threshold control oscillation circuit diagram;

27 is a circuit diagram illustrating a threshold control delay line;

28 is a threshold control delay line circuit diagram;

29 is a phase frequency detection circuit diagram;

30 is a phase frequency control circuit diagram;

31 is an up / down counter circuit diagram;

32 is a half adder circuit diagram;

33 is a full adder circuit diagram;

34 is a decoder circuit diagram;

35 is a voltage generation circuit diagram;

36 is a block diagram of another embodiment of the present invention;

37 is an operational amplifier circuit diagram;

38 is an operational amplifier circuit diagram;

39 is a block diagram of another embodiment of the present invention;

40 is a delay detection circuit diagram;

41 is a delay detection circuit diagram;

42 is a delay detection circuit diagram;

43 is a delay detection circuit diagram;

44 is a block diagram of another embodiment of the present invention;

45 is a block diagram of another embodiment of the present invention;

46 is a leakage current detection circuit diagram;

47 is a view showing the effect of the present invention;

48 is a view showing the effect of the present invention,

49 is a view showing the effect of the present invention,

50 is a diagram illustrating a relationship between a substrate bias and a gate delay time;

51 is a block diagram of another embodiment of the present invention;

52 is a substrate bias stability detection circuit diagram;

53 is a power supply voltage stable detection circuit diagram;

54 is a lock detection circuit diagram;

55 is a reset cancel circuit diagram;

56 is a view showing the operation procedure of the present invention;

57 is a view showing the operation procedure of the present invention;

58 is a block diagram of another embodiment of the present invention;

59 is a configuration diagram of another embodiment of the present invention;

60 is a view showing a relationship between an application example of the present invention and required performance;

61 is a block diagram of another embodiment of the present invention;

62 is a block diagram of another embodiment of the present invention;

63 is a block diagram of another embodiment of the present invention;

64 is a block diagram of another embodiment of the present invention;

65 is a diagram showing an example of the configuration of a microprocessor;

66 is a block diagram of another embodiment of the present invention.

Preferred Mode for Carrying Out the Invention

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 is a view showing the basic concept of the present invention. The main circuit LOG transfers a detection signal sig according to the operation speed of the circuit to the substrate bias control circuit CNT. The substrate bias control circuit CNT supplies the substrate bias vbp for the p-channel MOSFET and the substrate bias vbn for the n-channel MOSFET to the main circuit LOG. The main circuit LOG is composed of a MOS transistor, and is configured to control the threshold voltage by controlling the substrate bias of the MOS transistor.                 

With such a configuration, even if the characteristics of the MOS transistors fluctuate due to fluctuations in temperature, power supply voltage, or variations in the MOS transistor fabrication process, the substrate bias is controlled to control the threshold voltage of the MOS transistor at a constant operating speed. It is possible to fit. In addition, it is possible to substantially increase the speed by controlling the MOS transistor to be lower than the limit value determined as the desired maximum leakage current and controlling the operation speed of the main circuit to be constant by substrate bias control. In this way, when the main circuit is in the operation stop mode, it is possible to raise the threshold of the main circuit to reduce the leakage current and to reduce the power consumption.

20 shows the relationship between the threshold of the MOS transistor and the leakage current. In a standard MOS transistor, the threshold must be designed at point A, and the variation range due to the process must exceed the desired leakage current limit. In the present invention, by lowering the threshold to the point B and applying the substrate bias, even if the threshold is changed, it ends without exceeding the leakage current limit.

16 is a view showing another embodiment of the present invention. The main circuit LOG10 receives the clock signal clk10 from the outside and generates the detection signal sig10 according to the clock operating frequency. The substrate bias control circuit CNT10 receives the detection signal sig10 and supplies the substrate biases vvp10 and vbn10 to the main circuit LOG10. The substrate bias control circuit CNT10 controls the substrate biases vbp10 and vbn10 so that the operation speed of the main circuit LOG10 is changed according to the change of the clock signal clk10. As a result, the operating speed of the main circuit can be changed to match the external clock.

17 is a view showing another embodiment of the present invention. The main circuit LOG20 outputs a detection signal sig20 of circuit characteristics. The substrate bias control circuit CNT20 generates substrate biases vvp20 and vbn20 in response to the detection signal sig20. The substrate biases vbp20 and vbn20 are also supplied to the main circuit LOG21 together with the main circuit LOG20 on which the characteristic detection is performed. This configuration can suppress variations in the characteristics of the main circuit LOG20 and the main circuit LOG21.

18 is a view showing another embodiment of the present invention. As shown in the figure, when the plurality of main circuits LOG30 to LOG32 constitute one semiconductor integrated circuit LSI30, the control circuits CNT30 to CNT32 of the present embodiment are provided for each main circuit. Local characteristic variations within the integrated circuit can be suppressed, and local power management is also possible.

2 is a view showing a detailed embodiment of the present invention. The clock signal clk01 from the outside is supplied to the clock duty ratio conversion circuit VCLK01. The clock duty ratio conversion circuit VCLK01 generates a clock signal clk02 having a different duty ratio based on the clock signal clk01. The delay monitor circuit DMON01 receives the clock signal clk02 from the clock duty ratio conversion circuit VCLK01 and outputs a delayed output signal inv01 having a predetermined delay time. The delay comparison circuit CMP01 detects a phase difference, that is, a delay time difference, between the clock signal clk02 from the clock duty conversion circuit VCLK01 and the delay output signal inv01 from the delay monitor circuit DMON01 to detect a predetermined time. Compared with the design value of, a time signal (up01) with a short delay time is output, and a time (dw01) with a low delay time is output. The substrate bias generation circuit SBG01 generates two kinds of substrate biases vvb01 for p-channel MOSFETs and substrate bias vvn01 for n-channel MOSFETs. Each time the up01 signal is received from the delay comparator CMP01, the substrate bias generation circuit SBG01 raises the voltage of vbp01 by a predetermined voltage unit and decreases the voltage of vbn01 by a predetermined voltage unit. Each time the dw01 signal is hit from the delay comparator CMP01, the substrate bias generation circuit SBG01 lowers the voltage of vbp01 in predetermined voltage units and increases the voltage of vbn01 in predetermined voltage units. This substrate bias is applied to the substrate of the MOSFET of the delay monitor circuit DMON01.

The delay monitor circuit DMON01 is composed of an n-channel MOSFET and a p-channel MOSFET formed on a semiconductor substrate, and is configured such that the substrate bias of the MOSFET is changed by the substrate bias signal from the substrate bias generation circuit SBG01. . As described later, the delay time is changed by changing the threshold voltage according to the change of the substrate bias.

In the delay comparison circuit CMP01, when the delay time difference between the clock signal clk02 and the delay output signal inv01 becomes equal to a predetermined design value, neither the up01 signal nor the dw01 signal is interrupted. In the substrate bias generation circuit SBG01, when the output signal from the delay comparison circuit CMP01 is not supplied, it is determined that the substrate bias voltage value is determined, and the determined substrate bias is applied to the substrate of the main circuit LOG01. The threshold voltage is controlled by controlling the substrate bias of the MOS transistor.

By controlling the substrate bias by such a configuration, the threshold voltage of the MOS transistor is controlled, so that even if the operating environment and the like change, it is possible to always achieve a constant operating speed. In this configuration, when the main circuit is in the operation stop mode, the threshold of the main circuit can be raised to reduce the leakage current and to reduce the power consumption.

3 is a diagram illustrating an embodiment of a clock duty conversion circuit. By combining the flip-flop and the AND gate, three kinds of clocks (clka, clkb, clkc) having different phases can be generated from the clock input clk11. The waveform of each clock signal is shown in FIG.

5 is a diagram illustrating an embodiment of a delay monitor circuit. The delay monitor circuit is a series connection of inverters. The clock output (clkb) of the clock duty conversion circuit is received at the first stage of the inverter. Output signals invb and inva are taken out from the last stage and two stages of the inverter. Each inverter can change the threshold by controlling the substrate bias by the substrate bias signals vbp11 and vbn11, and can suppress the difference between the delay time between the signals inva and invb and the input signal clkb.

6 is a diagram illustrating an embodiment of a delay comparison circuit. It consists of flip-flop and end gate. The clock outputs (clka, clkb, clkc) from the clock duty converter circuit and the delay output signals (inva, invb) of the delay monitor circuit are input, and the up11 and dw11 signals are output. When the delay time of the delay monitor circuit is equal to the design value, the AND gate output and11 between inva and clkb generates a signal, and the AND gate output and12 between invb and clkb does not generate a signal. At this time, neither up11 nor dw11 outputs a signal. When the characteristic fluctuates due to a process variation or an environment change, and the delay time of the delay monitor circuit is increased, an up11 signal is output. If the delay time of the delay monitor becomes slow, the dw11 signal is output.

7 is a diagram illustrating an embodiment of a substrate bias generation circuit. It consists of an AND gate, an OR gate, a flip-flop, a selector, and a digital-analog converter. Flip-flops form a register that can be up and down, and only the output of the register position corresponding to the desired substrate bias signals.

Initially, the output signal comes from dff15, the center register output. The up11 signal and the dw11 signal from the delay comparison circuit are received, and the output position of the register is up or down in accordance with the clock signal clka of the clock duty conversion circuit. In the digital-analog converter DAC11, the substrate bias vvb11 for the p-channel MOSFET and the substrate bias vnb11 for the n-channel MOSFET are generated corresponding to the output positions dff10 to dff19 of the register. Each time the up11 signal is received, the register output shifts the register position by one step in the direction of dff10 to dff19. Upon receiving the dw11 signal, the register output shifts the register position by one step in the direction of dff19 to dff10. The substrate bias output changes the substrate bias by 0.2V each time the register output changes by one stage due to the signal of up11. If the power supply voltage is 1.8V, supplying the DAC11 with -1.8V and 3.6V power supply, the vbp11 signal is generated from 1.8V to 3.6V while the vbn11 signal is generated from 0.2V to -1.8V at 0.2V intervals. Can be.

When the delay time of the delay monitor circuit is faster than the designed value, the substrate bias generation circuit receives the up11 signal, so that the register output is increased by one stage, the substrate bias is increased by 0.2V by vbp11, and decreased by 0.2V by vbn11. This is applied to the MOSFET substrate of the delay monitor circuit to slow down the monitor delay time. When the delay time of the delay monitor circuit is later than the design value, since the substrate bias generation circuit receives the dw11 signal, the register output decreases by one stage, the substrate bias decreases by 0.2V by vbp11, and increases by 0.2V by vbn11. Applying this to the MOSFET substrate of the delay monitor circuit speeds up the monitor delay time.

8 and 9 show details of the selector inside the substrate bias generation circuit. The register signal of the substrate bias generation circuit switches the up and down directions by the select1 input signal of the selector.

19 is a diagram showing details of a digital-analog converter. Substrate biases vbp200 and vbn200 corresponding to the register outputs dff20 to dff29 are generated.

10 shows an embodiment of the lock detection circuit. The substrate bias output of the substrate bias generation circuit is always applied to the MOSFET substrate of the delay monitor circuit. However, when the characteristics of the delay monitor circuit vary, the bias voltage changes every clock until the substrate bias voltage is determined. In order to apply the control substrate bias of the main circuit after the substrate bias is determined, a lock detection circuit may be inserted. The outputs vpp21 and vbn21 of the digital-analog converter DAC21, which are directly connected to the shift register outputs dff10 to dff19 in the substrate bias generation circuit, are connected to the MOSFET substrate of the delay monitor circuit. The lock detection circuit LCK11 receives the shift register outputs dff10 to dff19, clka, up11, and dw11 signals, detects that the substrate bias voltage value is locked through the AND gate, and flip-flop, and supplies the digital-to-analog converter DAC22. Pass the signal. The digital-analog converter DAC22 outputs the substrate biases vbp22 and vbn22, and controls the substrate bias of the MOSFET substrate of the main circuit.

11 shows an embodiment of a standby circuit. When the main circuit is in the operation stop mode, the substrate bias is maximized in the p-channel MOSFET and the substrate bias is minimized in the n-channel MOSFET, so that the leakage current can be reduced and power consumption can be reduced. Substrate bias outputs vbp23 and vbn23 from the digital-analog converter DAC23 of the substrate bias generation circuit are formed as shown in the figure. The source of pMOS is connected to the maximum substrate bias vch and the source of nMOS to the minimum substrate bias vsl. When the power supply voltage is 1.8V, vch is 3.6V and vsl is -1.8V. The operation stop signal stb21 and the stb20 signal in phase with stb21 are supplied to the gates of the pMOS and nMOS.

13 and 14 show the relationship between the substrate bias voltage and the threshold voltage of the MOS transistor. 13 is an nMOS, and FIG. 14 is a pMOS. The threshold of the MOS transistor is changed by the substrate bias as shown in FIGS. 13 and 14. For this reason, in the case where a gate like an inverter is formed by using an nMOS transistor and a pMOS transistor, as shown in Fig. 15, the larger the absolute value of the substrate bias, the larger the delay time. Therefore, by controlling the substrate bias, the delay time of the CMOS circuit can be kept constant at all times. In the case where the CMOS circuit having the characteristic of FIG. 15 (I) is processed in advance and has the characteristic of (II), the bias voltage is increased down around 1.0V of the substrate bias, compared with the initial CMOS circuit. It is also possible to speed up or slow down the operating speed.

The delay time variation of the CMOS circuit is about 45% if none of the compensation is performed. In the method of controlling the leakage current constantly, it is impossible to cope with the change in temperature, so the variation in the delay time is rather widened to 60%. In the method of suppressing the delay time variation by the power supply voltage control, the variation range is suppressed to 36%. In contrast, in the present invention, the delay time can be reduced to 32%.

21 is a view showing another embodiment of the present invention. The delay detection circuit MON001 receives the clock signal clk001 and outputs a delay signal. The power supply control circuit VCNT001 generates a control signal cont001 to the digital-analog converting circuit DACONV001 as a 10-bit signal, for example, based on the delay signal. The digital-analog conversion circuit DACONV001 generates a pMOS transistor substrate bias vbp001 and an nMOS transistor substrate bias vvn001 in accordance with a control signal, and supplies it to the delay detection circuit MON001 and the main circuit LOG001. The delay detection circuit MON001 can change the signal transmission delay time by the substrate biases vvp001 and vbn001, and the voltage control circuit VCNT001 has a constant delay time of the output signal of the delay detection circuit MON001. The control signal is generated as the digital-analog conversion circuit DACONV001 generates the substrate bias signal. As a result, the operation speeds of the delay detection circuit MON001 and the main circuit LOG001 are always constant.

22 is a diagram showing a detailed embodiment of the present invention. The delay detection circuit MON001 is composed of a frequency divider circuit DIV001 and a threshold control oscillator circuit VC0011. The division circuit DIV011 divides the frequency of the clock signal input clk011 and outputs the clock signal clk012. The threshold control oscillation circuit VC0011 can change its oscillation frequency by the substrate bias signals vvp011 and vbn011, and generates an oscillation output signal vcosig011. The voltage control circuit VCNT011 is composed of a phase frequency detection circuit PFD011 and a phase frequency control circuit PFCNT011. The phase frequency detection circuit PFD011 receives the output clock signal clk012 of the frequency division circuit DIV011 and the oscillation output vcosig011 of the threshold control oscillation circuit VC0011, and detects the frequency difference and the phase difference of the two signals according to the difference. The up signal up011 or the down signal dw011 is generated. The phase frequency control circuit PFCNT011 converts the up signal up011 or the down signal dw011 into a control signal cnt011 of 10 bits, for example. The voltage generating circuit VG011 generates the pMOS transistor substrate bias vbp011 and the nMOS transistor substrate bias vnb011 in response to the control signal cnt011, and generates the threshold control oscillation circuit VC0011 and the main circuit LOG011. Supply to the substrate. The voltage control circuit VCNT011 controls the substrate bias so that the output vcosig011 of the threshold control oscillation circuit VC0011 is synchronized with both the frequency cl and the output clk012 of the frequency divider circuit DIV011. Therefore, the threshold control oscillation circuit VC0011 and the main circuit LOG011 always exhibit the same operation speed in response to the clock signal input clk011.

23 is a diagram showing an embodiment of a frequency divider circuit. The division circuit DIV012 is constituted by connecting a plurality of D-type flip-flops (DFF011 and the like) as shown in the figure. One D-type flip-flop generates an output signal clk014 by setting the frequency of the input clock signal clk013 to 1/2 and two to 1/4.                 

24, 25 and 26 show an embodiment of a threshold control oscillator circuit. The threshold control oscillator circuit can vary its oscillation frequency by the substrate bias signals bvp012, vbp013, vbp014, vbn012, vbn013, and vbn014, and output the clock signals vcosig012, vcosig013, vcosig014. VCO013 is an example of a NAND circuit and VCO014 is an NOR circuit.

27 and 28 illustrate an embodiment of a threshold control delay line. The delay comparison circuit of FIG. 5 can be configured similarly to the VCL011 or VCL012 even using a NAND circuit or a NOR circuit.

29 is a diagram showing an embodiment of a phase frequency detection circuit. The phase frequency detection circuit PFD012 detects a phase difference and a frequency difference between the clock signal clk019 and the oscillation output vcosig015, and outputs an up signal up012 when the clock signal clk019 is in progress. In this case, the down signal dw012 is generated.

30 is a diagram showing an embodiment of a phase frequency control circuit. The phase frequency control circuit PFCNT012 is composed of an up / down counter UDC011 and a decoder DEC011. The up / down counter (UDC011) adds one output signal (cnt012) to a binary number when an up signal (up013) is received, and one subtracts it when a down signal is received, and adds and subtracts the result of a 4-bit control signal (cnt012). Output as. The decoder DEC011 decodes the control signal cnt012 to generate a control signal cnt013 of about 8 bits.

Fig. 31 shows the configuration of the up / down counter. D-type flip-flops (DFF015, DFF016, DFF017, DFF018), T-type flip-flops (TFF011, TFF012, TFF013, TFF014, TFF015, TFF016, TFF017, TFF018), Half adder (HA011), Full adder It can comprise a (FA011, FA012, FA013) and an AND gate, a NAND gate, and an OR gate. The counter is added when the up signal up014 is input, and the counter is subtracted when the down signal dw014 is input, and outputs 4-bit output signals cnt014, cnt015, cnt106, and cnt017. The output signal is fed back internally to limit the counter. This configuration makes it possible to configure an asynchronous up / down counter.

As shown in FIG. 32, the half adder HA012 can be comprised, and the full adder FA014 can be comprised by combining the half adders HA013 and HA014 as shown in FIG.

The decoder can be configured as shown in FIG. Here, the 4-bit input signal cnt0-18-021 is converted into an 8-bit output signal cnt022-029.

35 is a diagram showing an embodiment of a voltage generating circuit. In addition to the digital-analog converter shown in FIG. 19, a voltage generation circuit VG013 can be configured as shown in FIG. The output voltage is changed by the control signals cnt030 to cnt037 for input. It is also possible to connect operational amplifier circuits OPAMPP011 and OPAMPN011 and resistors RFP and RFN to the output portion to reduce the output impedance. The output of this voltage generator circuit VG013 becomes the substrate bias signals vbp018 and vbn018.

36 shows another embodiment of the present invention. The delay detection circuit MON012 inputs a clock signal clk020 and outputs a delay signal. The voltage control circuit VCNT012 generates a control signal based on the delay signal, and transfers it to the digital-analog conversion circuit DACONV011. The digital-analog conversion circuit DACONV011 generates the substrate bias signals vvp019 and vbn019 in accordance with the control signal, and applies them to the substrate of the delay detection circuit MON012. The operational amplifier circuits OPAMPPO12 and OPAMPN012 receive the substrate bias signals, output the substrate bias signals vbp020 and vbn020 at the same voltage as vbp and vbn, and apply them to the substrate of the main circuit LOG012. The delay detection circuit MON012 can change the signal transfer delay time by the substrate biases vvp019 and vbn019, and the voltage control circuit VCNT012 has a constant delay time of the output signal of the delay detection circuit MON012. The control signal is generated so that the digital-analog conversion circuit generates the substrate bias signal. As a result, the operation speeds of the delay detection circuit MON012 and the main circuit LOGO12 are always constant. When the circuit size of the main circuit LOGO12 is large, it takes time for the substrate bias signals vbp020 and vbn020 to stabilize, but by inserting a circuit having a low output impedance, such as an operational amplifier circuit (OPAMPP012 or OPAMPN012), It is possible to speed up the stabilization of the bias signal. This operational amplifier circuit may be inserted into the substrate biases vvp019 and vbn019 for the delay monitor MON012.

37 and 38 show an embodiment of the operational amplifier circuit.

39 shows another embodiment of the present invention. The pMOS transistor delay detection circuit PMONO41 can change the delay time by the pMOS transistor substrate bias signal vbn041, and the nMOS transistor delay detection circuit NMON041 uses the nMOS transistor substrate bias signal vbn041. You can change the delay time. Delay detection circuits PMONO41 and NMONO41 input clock signals clk041, respectively, and voltage control circuits VCNT041 and VCNT042, which transfer delay signals to voltage control circuits VCNT041 and VCNT042, respectively, transmit control signals according to the respective delay signals. Output The digital-to-analog conversion circuits DACONV041 and DACONV042 generate the pMOS transistor substrate bias signal vbp041 and the nMOS transistor substrate bias signal vvn041 according to the respective control signals, and the delay detection circuits PMONO41 and NMON041 and the main circuit. Supply to (LOG041). The digital-to-analog conversion circuit DACONV041 eliminates the change in the delay time caused by the pMOS transistor, and the DACONV042 eliminates the change in the delay time caused by the nMOS transistor. The operation of the main circuit LOG041 and the delay detection circuits PMON041 and NMONO41 Keep constant at speed. By controlling the change in delay time of the pMOS transistor and the change in delay time of the nMOS transistor independently, highly accurate substrate bias control is possible.

40 and 41 show a delay detection circuit for a pMOS transistor. As shown in the figure, it is possible to control the change of the delay time by supplying the substrate biases (vbp042, vbp043) for the pMOS transistor.

42 and 43 show a delay detection circuit for an nMOS transistor. Similarly, the variation of the delay time can be controlled by supplying the substrate biases (vbn042, vbn043) for the nMOS transistor.

44 is a view showing another embodiment of the present invention. It consists of a delay time control circuit and a leakage current detection circuit LMT051 according to the embodiment of FIG. The leakage current detection circuit receives the substrate biases (vbp051 and vbn051) generated by the substrate bias generation circuit (SBG051) and detects the leakage current of the circuit. When the leakage current increases above a certain value, the substrate bias control is stopped. Do not change the bias. Therefore, the leak current detection circuit LMT051 limits the increase of the leak current by the substrate bias control and prevents malfunction due to thermal runaway of the circuit.

45 is a view showing another embodiment of the present invention. It consists of a delay time control circuit and the leakage current detection circuit LMT052 according to the embodiment of FIG. The leakage current detection circuit receives the substrate biases (vbp052 and vbn052) generated by the voltage generation circuit VG051 to detect the leakage current of the circuit. When the leakage current increases above a certain value, the substrate bias control is stopped, and the substrate bias is reduced. Do not change. Therefore, the leak current detection circuit LMT052 imposes a limit on the increase in the leakage current by the substrate bias control, and prevents malfunction due to thermal runaway of the circuit.

46 is a diagram showing an embodiment of the leak current detection circuit. It inserts between the up signal up055 and up056 which become the direction in which the leakage current increases by board | substrate bias control. The limit of the leakage current by the pMOS transistor substrate bias (vbp053) is determined by the diffusion layer width (wn01) of the nMOS transistor, and the limit of the leakage current by the nMOS transistor substrate bias (vbn053) is defined by the diffusion layer width (wp01) of the pMOS transistor. Is determined.

47 is a view showing an application method of the present invention. A typical CMOS device has performance distribution as shown in Fig. 47 (a) due to factors such as creation process, operating voltage, operating temperature, and the like. The threshold upper limit of this distribution is determined by the allowable limit of the slowest operation speed, and the lower limit is determined by the maximum allowable limit of power consumption. When the present invention is applied to these devices, the width of the performance distribution can be narrowed like the oblique portions. With respect to the control by the substrate bias, when the substrate bias is applied only in the reverse bias direction, the distribution is driven to the side where the threshold is higher, that is, the operation speed becomes slower. When the threshold is made low as shown in Fig. 47 (b), the lower limit of the distribution exceeds the limit of power consumption. However, if the present invention is applied to this device, the distribution of devices that can be distributed in diagonal lines and not exceeding the limit of power consumption can be matched to a region having a low threshold and a high operating speed, and the circuit can be made faster. .

48 is a view showing another application method of the present invention. As shown in FIG. 50, it is also possible to operate | move by applying a board | substrate bias to about 0.5V in a forward bias direction. When the present invention is applied by performing forward bias control, as shown in Fig. 48, the normal CMOS device distribution can be converged to the position of the oblique line where the threshold is low and the operation becomes high. This makes it possible to speed up the circuit.

49 is a view showing another application method of the present invention. When the substrate bias control is used in both the reverse bias direction and the forward bias direction in both directions, it is possible to match the device distribution to the design center value as the diagonal distribution. Therefore, the yield of a device can be improved.

51 is a view showing another embodiment of the present invention. 44, 45, the delay time control circuit, the substrate bias stability detection circuit VSTS061, the power supply voltage stability detection circuit VSTD061, the lock detection circuit LDT061, the reset release circuit RNC061, and the standby circuit. It consists of STB061. By this embodiment, the operation procedure of the semiconductor integrated circuit according to the present invention is determined. When the power switch is input, the substrate bias is supplied, and the substrate bias stability detection circuit VSTS061 determines the stability of the substrate bias potential and generates the substrate bias stability signal vbst061. When the power supply voltage stable detection circuit VSTD061 receives the substrate bias stability signal vbst061, the power supply voltage stability detection circuit VSTD061 supplies the power supply voltage, determines the stability of the power supply voltage, and generates the power supply voltage stability signal vvdst061. By this procedure, the substrate bias can always be supplied before the power supply, thereby preventing the latch-up of the MOS transistors. The clock signal clk061 starts to transfer the clock signal into the control circuit when the power supply voltage stabilizer signal vstst061 is input. The lock detection circuit LDT061 receives a clock signal clk062 input into the control circuit, an up signal up062 and a down signal dw061 in the control circuit, and when the control signal in the control circuit is stabilized, the lock signal lck061. Outputs The reset cancel circuit RCN061 receives the lock signal lck061 and the power supply voltage stabilization signal vstst061 and outputs a reset cancel signal rst061. The main circuit LOG061 receives the reset release signal rst061 to cancel the reset state and starts operation. By this procedure, malfunction of the main circuit LOG061 is prevented.

56 and 57 show the operation procedure of the present invention according to the present embodiment.

Fig. 56 shows the processing procedure from the start of the system to the start of operation of the main circuit. Such a procedure may be created by a program or may be formed as a wild ROM.

After the start of the system shown in the processing fc1, the maximum voltage is supplied to the pMOS substrate bias Vbp and the minimum voltage is supplied to the nMOS substrate bias Vbn as in the processing fc2. In the process fc3, it is judged whether or not the substrate bias is stable, and the state is waited until it is stabilized, and then the process is shifted to the process fc4. After the substrate bias is stabilized, the power supply voltage is supplied in the process fc4. In the process fc5, it is determined whether the voltage voltage is stable, and the state is waited until it is stabilized, and then the process shifts to the process fc6 after the stability. In process fc6, substrate bias control is started to determine whether the control signal is locked. If the control signal is not locked, it is determined in step fc7 whether the leak current monitor has exceeded the limit of the leak current, and if not, the process fc6 is continued. If the leak current exceeds the limit in the process fc7, the limiter of the leak current is activated in the process fc8, and the substrate bias control signal does not change any more, and the process proceeds to the process fc9. If the substrate bias control signal is locked within the limit of the leakage current, the process shifts from the processing fc6 to the processing fc9. In the process fc9, the reset is canceled to start the operation of the main circuit. This operation procedure can prevent malfunction of the circuit due to latch-up of the MOS transistor, thermal runaway, or the like at the start of operation.

Fig. 57 is a view showing a procedure for preventing malfunction due to thermal runaway during the operation of the main circuit. After the reset is canceled in the process fc11 to start the operation of the main circuit, it is confirmed in the process fc12 that the substrate bias control signal is always locked. In the case of locking, it is judged whether or not a standby signal is generated in the process fc15, and returns to the process fc12 if it is not generated. When the lock of the substrate bias signal is released in the process fc12, the leak current monitor of the process fc13 determines the limit of the leakage current, and returns to the process fc12 if the limit is not exceeded. The limiter is operated in fc14 to stop the change of the substrate bias control signal, and the process proceeds to fc15. When the standby signal is generated in the process fc15, the pMOS substrate bias Vbp is the maximum value and the nMOS substrate bias is the minimum value in the process fc16 in order to bring the main circuit into the standby state. Reduce power consumption

In the process fc17, the generation of the active signal is detected, and the standby state is maintained until it occurs. When the active signal is generated, the standby state is canceled, the operation of the main circuit is resumed, and the process returns to the processing fc12.

52 is a diagram showing an embodiment of the substrate bias stability detection circuit. When the reset switch RSTS061 is released, the substrate bias voltage is charged to the capacitor C061 through the resistor R061. Vbp062 is the power source. When this charging voltage exceeds a certain value, the buffer circuits BUF061 and BUF062 operate to generate the substrate bias stabilization signal vbst062.

Fig. 53 is a diagram showing an embodiment of the power supply voltage stable detection circuit. Upon receiving the substrate bias stabilization signal vbst063, the n-type MOS transistor is turned off and the power supply voltage is charged to the capacitor C062 through the resistor R062. When this charging voltage exceeds a certain value, the buffer circuits BUF063 and BUG064 operate to generate the power supply voltage stabilization signal vstst062.

54 is a diagram showing an embodiment of the lock detection circuit. The clock signal clk063 is divided by the division circuit DIV061 and input as a clock signal of the D flip-flop DFF061. Further, by taking the NOR of the up signal up063 and the down signal dw063 and accepting it as the data signal of DFF061, the lock signal lck062 is generated when neither the up signal nor the down signal is generated.

55 is a diagram showing an embodiment of a reset cancel circuit. The reset cancel circuit RCN062 receives the lock signal lck063 and the power supply voltage stabilization signal vstst063 and generates a reset cancel signal rst062. In a state in which there is no input signal before starting the operation of the system and only the power supply voltage stabilization signal vstst063 is generated, the reset release signal rst062 is at a low level in order to maintain the reset state, but then the lock signal lck063 is applied. If this occurs, rst062 goes high and the reset is canceled. Once released, the reset release signal rst062 remains high level and does not reset until the system is stopped.

58 is a view showing another embodiment of the present invention. By controlling the operation speed of the input / output circuit IO071 using the speed control substrate bias signal vbb071 by the operation speed control circuit DCNT071, the input / output signal sig071 and the input / output signal from the outside to the input / output circuit IO071 are input and output. The signal transfer speed of the signal sig072 from the circuit IO071 to the main circuit LOG071 is controlled. Although the signal to the input / output circuit IO071 may cause a difference in signal transmission speed due to different voltages, the speed difference can be eliminated by making the rising and falling speed constant during the signal transition of the IO071.

Another significance of this embodiment is that the operating speed of the input / output circuit can be controlled independently of the main circuit. If the input / output circuit is slower than the operation speed of the external circuit, it is meaningless. Therefore, the substrate bias of the input / output circuit is controlled separately from the main circuit, and the threshold value of the transistor constituting this part is increased. Instead of limiting the operating speed, it is possible to reduce the power consumption by the leakage current.

59 is a view showing another embodiment of the present invention. The clock generation circuit CPG081 can vary the frequency of the generation clock signal clk081 by the control signal cnt081. The operation speed control circuit DCNT081 generates the substrate bias control signal vbb081 according to the frequency of the clock signal clk081 and supplies it to the main circuit LOG081. As a result, the main circuit LOG081 can operate at an optimum speed against the change of the clock signal clk081 generated by the clock generation circuit CPG081. As shown in FIG. 60, the signal processing performed by the main circuit LOG081 varies in processing speed and performance required according to the purpose of use, and thus, power consumption can be reduced by changing the operating speed in accordance with the intended use.

61 is a view showing another embodiment of the present invention. The clock signal clk091 generated by the clock generation circuit CPG091 is divided by the division circuits DIV091, DIV092, DIV093 and the like to generate clock signals clk092, clk093, and clk094 of different frequencies. The operation speed control circuits DCNT091, DCNT092, and DCNT093 receive clock signals clk092, clk093, and clk094, respectively, and generate optimum substrate bias signals vbb091, vbb092, and vbb093 according to each clock frequency, and generate the main circuit. Controls the operation speed of (LOG091, LOG092, LOG093). It is possible to operate at different processing speeds for each block that has the sum of certain processing in one system.

Although FIG. 65 shows an embodiment of block division in a system, for example, a block of a liquid crystal panel controller LCD may change the processing speed of the controller block according to the resolution of the liquid crystal panel. In addition, the power consumption can be reduced by appropriately adjusting the operation state (active state) and non-operation state (standby state) by the block.

62 is a view showing another embodiment of the present invention. The operation speed control circuits DCNT101, DCNT102, and DNCT103 that receive the clock signal clk101 of the clock generation circuit CPG101 have the substrate bias signals vbb101, vbb102, and vbb103 according to the respective power supply voltages vdd101, vdd102, and vdd103. Is generated and applied to the main circuits (LOG101, LOG102, LOG103). Since the main circuits LOG101, LOG102, LOG103 are supplied with different power supply voltages vvd101, vdd102, vdd103, the main circuits LOG101, LOG102, LOG103 can be operated under a substrate bias that is optimal for the respective operating speeds. When different power supply voltages are applied to each block having a total of a certain process in one system, optimal substrate bias control can be performed for each main circuit constituting the block.

FIG. 63 is a development example of FIG. 62. As shown in Fig. 63, the switches MOS, SW104, SW105, and SW106 are provided in each main circuit, and this switch is turned off at the time of standby or the like, and further power reduction per block is possible. If the leakage current of the FET to be the switch is designed to be smaller than the sum of the leakage currents of the FETs in the block, it is possible to obtain the effect of reducing the leakage current during standby or the like. For example, the switch may be composed of a MOSFET having a high threshold.

64 is a view showing another embodiment of the present invention. In the main circuit LOG111, which is one of the blocks having a total of a certain processing, the layout arrangement of the delay detection circuit MON111 among the operation speed control circuit DCNT111 is arranged at the center of the block to represent the operation characteristics of the block. The delay detection circuit MON111 can be designed.

66 is a view showing another embodiment of the present invention. In the main circuit LOG121, the delay detection circuit MON121 and the voltage control circuit VCNT121 among the operation speed control circuits are formed, and the digital-analog conversion circuit DACONV121 for generating the control voltage can be created on another chip. As a result, a circuit that must be configured in the main circuit among the operation speed control circuits can be reduced, and the area and power consumption can be reduced.

As described above, according to the present invention, by controlling the threshold value of the MOS transistors constituting the circuit, the characteristic variation of the CMOS circuit can be suppressed and the operation speed can be improved. By lowering the threshold of the MOS transistors in advance, the effect of speed improvement is greatly increased. In order to digitally detect the characteristic variation, the control circuit can be configured as a digital circuit, and the settling time of the control signal can be shortened. In addition, since the control circuit can be formed in a small circuit size, a plurality of control circuits can be arranged in the semiconductor integrated circuit to control the threshold, and local characteristic variations can be suppressed. In addition, power management for each part of the semiconductor integrated circuit is also possible.

Claims (22)

A logic circuit composed of a MOS transistor, a digital-analog conversion circuit for generating a substrate bias voltage for controlling the threshold of the MOS transistor constituting the logic circuit, a voltage control circuit for outputting a control signal in accordance with a delay signal, It has a delay detection circuit for supplying a clock signal from the outside to output the delay signal, The voltage control circuit inputs the delay signal of the delay detection circuit, and outputs a control signal corresponding to the delay time indicated by the delay signal, The digital-analog conversion circuit receives the control signal from the voltage control circuit to generate a voltage corresponding to the control signal, and the operation speeds of the logic circuit and the delay detection circuit are supplied from the digital-analog conversion circuit. Semiconductor integrated circuit device, characterized in that controlled by the voltage. The method of claim 1, The delay detection circuit is composed of a clock duty conversion circuit and a delay monitor circuit, The voltage control circuit is composed of a delay comparison circuit, The digital-analog conversion circuit is constituted by a substrate bias generation circuit, The clock duty conversion circuit receives the clock signal from the outside and outputs a clock signal having an arbitrary duty ratio, The delay monitor circuit outputs the output signal of the clock duty conversion circuit with a constant delay time, The delay comparison circuit compares the delay time difference between the output signal of the clock duty conversion circuit and the delay monitor circuit, and outputs a signal according to the difference. The substrate bias generation circuit generates a substrate bias voltage according to the output signal of the delay comparison circuit, And said logic circuit and said delay monitor circuit control a delay time by a substrate bias voltage generated by said substrate bias generation circuit. The method of claim 1, The delay detection circuit is composed of a frequency divider circuit and an oscillation circuit, The voltage control circuit is composed of a phase frequency detection circuit and a phase frequency control circuit, The digital-analog conversion circuit is constituted by a voltage generating circuit, The clock signal supplied from the outside is supplied to the frequency division circuit to arbitrarily divide the frequency. The phase frequency detection circuit compares the phase and frequency of the divided signal of the frequency divider circuit and the output signal of the oscillator circuit and outputs an output signal according to a difference. The phase frequency control circuit outputs a control signal in accordance with the output signal of the phase frequency detection circuit, The voltage generation circuit generates a substrate bias voltage in accordance with a control signal of the phase frequency control circuit. And an operation speed of the logic circuit and the oscillation circuit is controlled by a substrate bias voltage generated by the voltage generation circuit. The method of claim 1, The delay detection circuit is composed of a pMOS delay detection circuit that detects a threshold change of a pMOS transistor and an nMOS delay detection circuit that detects a change in a threshold of an nMOS transistor, The voltage control circuit and the digital-analog conversion circuit are each composed of two circuits for a pMOS transistor and an nMOS transistor, respectively. An operating speed of the pMOS delay detection circuit is controlled by a pMOS transistor substrate bias voltage generated by the pMOS transistor digital-analog conversion circuit. And an operating speed of the nMOS delay circuit is controlled by an nMOS transistor substrate bias generated by the nMOS transistor digital-analog conversion circuit. A logic circuit composed of MOS transistors, a digital-analog conversion circuit for generating a substrate bias voltage for controlling the threshold of the MOS transistors constituting the logic circuit, a voltage control circuit for outputting a control signal in accordance with a delay signal, It has a delay detection circuit and a leakage current detection circuit for supplying a clock signal from the outside to output the delay signal, The voltage control circuit inputs the delay signal of the delay detection circuit to output a control signal corresponding to the delay time indicated by the delay signal, The digital-analog conversion circuit receives the control signal from the voltage control circuit, generates a voltage corresponding to the control signal, and the operation speeds of the logic circuit and the delay detection circuit are supplied from the digital-analog conversion circuit. Controlled by the voltage being The leakage current detection circuit controls the leakage current by the voltage supplied from the digital analog conversion circuit, and fixes the leakage voltage of the digital analog conversion circuit when the leakage current increases above a certain value. Semiconductor integrated circuit device characterized in that the limit to increase. The method of claim 5, Having first and second voltage stabilization circuits, control voltage stabilization detection circuits, reset release circuits, and operation / non-operation switching circuits, The first voltage stabilization circuit supplies a power supply voltage after the substrate bias voltage at which supply is started after the semiconductor integrated circuit device is started is stabilized, The second voltage stabilization circuit starts supplying a clock signal from the outside to the delay detection circuit after the power supply voltage is stabilized; The control voltage stable detection circuit detects the stability of the control output voltage, The reset canceling circuit sends a reset cancel signal to the logic circuit when the control voltage stability detecting circuit detects stability to release the reset state of the logic circuit to start operation. The operation / inoperation switching circuit switches the validity and invalidation of the control of the semiconductor integrated circuit in accordance with the operation / inaction switching signal, thereby preventing the malfunction of the logic circuit during startup or operation. Device. delete delete delete delete delete delete A semiconductor integrated circuit device having a controlled circuit including at least one transistor and a control circuit for controlling a substrate bias voltage of the transistor of the controlled circuit, wherein the threshold of the transistor is changed. The control circuit has a limiter for controlling the substrate bias voltage within a predetermined range, And the limiter has a leak current detecting circuit for detecting a leak current of the transistor, and stops substrate bias control of the control circuit if the leak current increases above a certain value. delete A circuit device comprising a controlled circuit comprising a transistor and a control circuit for controlling a substrate bias of the transistor, wherein the circuit device is provided with: (1) Set the substrate bias of the transistor to a predetermined value, (2) Supply the power voltage to the transistor, (3) operates in the order of dynamically controlling the substrate bias of the transistor, And the control circuit includes a monitor circuit for monitoring a delay time of the controlled circuit, and a substrate bias generator for controlling a substrate bias of the transistor based on a signal from the monitor circuit. The method of claim 15, And a limiter circuit for stopping the dynamic control. The method of claim 16, And the limiter circuit is a circuit for monitoring the leakage current of the transistor. Having a first controlled circuit block and a second controlled circuit block, A switch is provided in each of the controlled circuits, and the switch controls supply of power to transistors included in each controlled circuit, And a control circuit is provided in each of the controlled circuits, and the substrate circuit controls the substrate bias voltage of the transistors included in each of the controlled circuits. The method of claim 18, And a voltage of power supplied to each of the controlled circuits is different. The method of claim 18 or 19, And the control circuit detects a delay time of the controlled circuit and controls the substrate bias voltage of the transistor based on the detection result. A logic circuit including a first MOS transistor, A delay monitor circuit including a second MOS transistor and outputting an oscillation signal; A delay comparison circuit for comparing a reference clock signal with the oscillation signal from the delay monitor circuit and outputting a control signal; A substrate bias generation circuit for applying a substrate bias voltage to the first MOS transistor and the second MOS transistor, And the substrate bias generation circuit raises or lowers the substrate bias voltage in predetermined voltage units according to a control signal from the delay comparison circuit. The method of claim 21, And the delay monitor circuit is a delay circuit to which the reference clock signal is input and formed by the second MOS transistor.

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