WO1998058324A1 - Device for exchanging asynchronous data between two microprocessors - Google Patents

Device for exchanging asynchronous data between two microprocessors Download PDF

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Publication number
WO1998058324A1
WO1998058324A1 PCT/FR1998/001255 FR9801255W WO9858324A1 WO 1998058324 A1 WO1998058324 A1 WO 1998058324A1 FR 9801255 W FR9801255 W FR 9801255W WO 9858324 A1 WO9858324 A1 WO 9858324A1
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Prior art keywords
microprocessor
master
slave
microprocessors
memory
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PCT/FR1998/001255
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French (fr)
Inventor
Alain Rhelimi
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Schlumberger Systemes
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Publication date
Application filed by Schlumberger Systemes filed Critical Schlumberger Systemes
Priority to CA002294245A priority Critical patent/CA2294245A1/en
Priority to EP98930854A priority patent/EP0990208A1/en
Publication of WO1998058324A1 publication Critical patent/WO1998058324A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Definitions

  • the present invention relates to a device for exchanging asynchronous data between two microprocessors via an interface constituted by a random access memory.
  • the invention finds a particularly advantageous application whenever it is desired to exchange asynchronous data between two microprocessors without one of said microprocessors being slowed down or disturbed in the execution of its instruction cycles by the exchange of data.
  • a known solution to satisfy this requirement consists in sharing the data bus, then called "multi-bus", between the two microprocessors.
  • each microprocessor releases the bus at the request of a bus controller, which orchestrates the sharing of the bus between the two microprocessors.
  • the microprocessors cannot guarantee a precise processing time because access to the bus is not deterministic.
  • RAM dual access random access memory
  • the technical problem to be solved by the object of the present invention is to propose a device for exchanging asynchronous data between two microprocessors by means of an interface constituted by a random access memory, a device which would allow obtain deterministic access to said memory, to ensure simple management of arbitration, while avoiding disturbing the operation of one of the microprocessors.
  • each instruction executed by said master microprocessor comprises execution cycles followed by at least two cycles of data exchange in read / write with the second microprocessor, said microprocessor-slave, at an address of the random access memory defined by said microprocessor-slave,
  • the master microprocessor is able to extend the access time of the slave microprocessor to the random access memory until the end of the last data exchange cycle.
  • the management of access to the random access memory with single access is fully taken care of by the master microprocessor, the operation of which is therefore insensitive to the exchange of data. , at least two cycles of the master microprocessor being reserved for access to the RAM memory by the microprocessor-slave. This characteristic is very important if the execution time of the master microprocessor must be a time reference, in particular when it is desired to simulate a UART by software.
  • Figure 1 is a general block diagram of the asynchronous data exchange device according to the invention.
  • FIG. 2 is a breakdown into clock cycles of an instruction executed by the master microprocessor of the device of the invention.
  • Figure 3 is a timing diagram between a microprocessor-master and microprocessor-slave.
  • FIG. 1 is shown schematically an asynchronous data exchange device between a first microprocessor 10, which will be called microprocessor-master in the following, and a second microprocessor 20, called microprocessor-slave.
  • a first microprocessor 10 which will be called microprocessor-master in the following
  • a second microprocessor 20 called microprocessor-slave.
  • the exchange of asynchronous data between the two microprocessors takes place via an interface constituted by a random access memory (RAM) 30 of the single access type.
  • RAM random access memory
  • Access to the RAM memory 30 is permanently under the control of the master microprocessor 10 in the sense that when the slave microprocessor 20 requests read / write access to a given address of the memory 30 (time tQ of the timing diagram of FIG. 3), this request RD / WR is recorded by the microprocessor-master 10 at the instant ti, according to the instant tg of a clock cycle of the microprocessor-master 10 for example. If, at this instant ti, access to the RAM memory 30 is not available because the microprocessor-master 10 is precisely in a situation of exchange with said memory 30, during one of the cycles of execution 1 to N-2 of the instruction represented in FIG. 2, the microprocessor-master 10 delivers to the microprocessor-slave 20 a signal S ⁇ of elongation access time to the RAM memory 30, the effect of the signal S ⁇ being to suspend the read / write cycle of the microprocessor-slave 20.
  • an instruction executed by the master microprocessor 10 comprises, in addition to the execution cycles 1 to N- 2 with or without access to the memory RAM 30, an initial acquisition cycle O "FETCH" of an operating code and two final cycles, N-1 and N, of access to the memory 30 in write AM or in read AM-R by the microprocessor-slave 20.
  • These cycles AM and AM-R therefore have the effect allow the exchange of asynchronous data between the two microprocessors 10, 20 at the address of the RAM memory 30 defined by the microprocessor-slave 20 and recorded by the microprocessor 10 at time ti.
  • the AM and AM-R cycles of exchange with the slave microprocessor 20 being an integral part of the instructions executed by the master microprocessor 10 the latter is in no way disturbed or slowed down by the exchange of data.
  • the cycle AM takes place between the instants t2 and during this interval the microprocessor-master 10 writes data which are read by the microprocessor-slave 20, while between the instants t_ and t_.
  • the microprocessor-master 10 reads the data written by the microprocessor-slave 20.
  • the signal S ⁇ is switched at time t5 thus marking the end of the RD / WR cycle of the microprocessor-slave 20.

Abstract

The invention concerns a device for exchanging asynchronous data between two microprocessors (10, 20) through an interface consisting of a random access memory (30). The invention is characterised in that said random access memory has a single access controlled by one of said microprocessors, called master microprocessor (10). Each instruction executed by said master microprocessor comprises execution cycles followed by at least two read-write data exchange cycles with the second microprocessor, called slave microprocessor (20) and the master microprocessor (10) is capable of prolonging the slave microprocessor (20) access time to the random access memory until the end of the last data exchange cycle (AM-R).

Description

DISPOSITIF D'ECHANGE DE DONNEES ASYNCHRONES ASYNCHRONOUS DATA EXCHANGE DEVICE
ENTRE DEUX MICROPROCESSEURSBETWEEN TWO MICROPROCESSORS
La présente invention concerne un dispositif d'échange de données asynchrones entre deux microprocesseurs par l'intermédiaire d'une interface constituée par une mémoire à accès aléatoire.The present invention relates to a device for exchanging asynchronous data between two microprocessors via an interface constituted by a random access memory.
L'invention trouve une application particulièrement avantageuse à chaque fois que l'on souhaite échanger des données asynchrones entre deux microprocesseurs sans que l'un desdits microprocesseurs ne soit ralenti ou perturbé dans l'exécution de ses cycles d'instruction par l'échange de données.The invention finds a particularly advantageous application whenever it is desired to exchange asynchronous data between two microprocessors without one of said microprocessors being slowed down or disturbed in the execution of its instruction cycles by the exchange of data.
Une solution connue pour satisfaire cette exigence consiste à partager le bus de données, appelé alors "multi-bus", entre les deux microprocesseurs. Dans ce cas particulier, chaque microprocesseur libère le bus à la demande d'un contrôleur de bus, lequel orchestre le partage du bus entre les deux microprocesseurs. Selon ce mode de fonctionnement^ les microprocesseurs ne peuvent garantir un temps de traitement précis car l'accès au bus n'est pas déterministe.A known solution to satisfy this requirement consists in sharing the data bus, then called "multi-bus", between the two microprocessors. In this particular case, each microprocessor releases the bus at the request of a bus controller, which orchestrates the sharing of the bus between the two microprocessors. According to this operating mode, the microprocessors cannot guarantee a precise processing time because access to the bus is not deterministic.
Une autre solution fréquemment mise en oeuvre est l'utilisation comme interface d'une mémoire à l'accès aléatoire (RAM) à double accès. Toutefois, ce type de mémoire nécessite une gestion électronique lourde impliquant un nombre plus important de portes liées à l'arbitrage que pour des mémoires à accès aléatoire à simple accès. De plus, là encore, si le temps d'exécution doit être constant ou précis, alors le partage de la mémoire RAM à double accès n'est pas déterministe.Another frequently used solution is the use of a dual access random access memory (RAM) as an interface. However, this type of memory requires cumbersome electronic management involving a greater number of doors related to arbitration than for random access memories with single access. In addition, here again, if the execution time must be constant or precise, then the sharing of the dual-access RAM memory is not deterministic.
Aussi, le problème technique à résoudre par l'objet de la présente invention est de proposer un dispositif d'échange de données asynchrones entre deux microprocesseurs par l'intermédiaire d'une interface constituée par une mémoire à accès aléatoire, dispositif qui permettrait d'obtenir un accès déterministe à ladite mémoire, d'assurer une gestion simple de l'arbitrage, tout en évitant de perturber le fonctionnement d'un des microprocesseurs.Also, the technical problem to be solved by the object of the present invention is to propose a device for exchanging asynchronous data between two microprocessors by means of an interface constituted by a random access memory, a device which would allow obtain deterministic access to said memory, to ensure simple management of arbitration, while avoiding disturbing the operation of one of the microprocessors.
La solution au problème technique posé consiste, selon la présente invention, en ce que : - ladite mémoire à accès aléatoire est du type à simple accès, lequel est contrôlé par l'un desdits microprocesseurs, dit microprocesseur-maître,The solution to the technical problem posed consists, according to the present invention, in that: - said random access memory is of the single access type, which is controlled by one of said microprocessors, called microprocessor-master,
- chaque instruction exécutée par ledit microprocesseur-maître comporte des cycles d'exécution suivis d'au moins deux cycles d'échange de données en lecture /écriture avec le deuxième microprocesseur, dit microprocesseur-esclave, à une adresse de la mémoire à accès aléatoire définie par ledit microprocesseur-esclave,each instruction executed by said master microprocessor comprises execution cycles followed by at least two cycles of data exchange in read / write with the second microprocessor, said microprocessor-slave, at an address of the random access memory defined by said microprocessor-slave,
- le microprocesseur-maître est apte à allonger le temps d'accès du microprocesseur-esclave à la mémoire à accès aléatoire jusqu'à la fin du dernier cycle d'échange de données.- The master microprocessor is able to extend the access time of the slave microprocessor to the random access memory until the end of the last data exchange cycle.
Ainsi, comme on le verra en détail plus loin, la gestion de l'accès à la mémoire à accès aléatoire à simple accès est totalement prise en charge par le microprocesseur-maître dont le fonctionnement est de ce fait insensible à l'échange de données, au moins deux cycles du microprocesseur-maître étant réservés à l'accès à la mémoire RAM par le microprocesseur-esclave. Cette caractéristique est très importante si le temps d'exécution du microprocesseur-maître doit être une référence temporelle, notamment lorsque l'on veut simuler une UART par logiciel.Thus, as will be seen in detail below, the management of access to the random access memory with single access is fully taken care of by the master microprocessor, the operation of which is therefore insensitive to the exchange of data. , at least two cycles of the master microprocessor being reserved for access to the RAM memory by the microprocessor-slave. This characteristic is very important if the execution time of the master microprocessor must be a time reference, in particular when it is desired to simulate a UART by software.
D'autre part, on peut observer que l'accès à la mémoire RAM est déterministe et que l'arbitrage peut être géré très facilement.On the other hand, we can observe that access to RAM memory is deterministic and that arbitration can be managed very easily.
Enfin, l'utilisation d'une mémoire RAM à simple accès présente l'avantage d'une intégration très simple au sein d'un ASIC (3000 portes pour 2048 bits). La description qui va suivre en regard des dessins annexés, donnés à titre d'exemples non limitatifs, fera bien comprendre en quoi consiste l'invention et comment elle peut être réalisée.Finally, the use of a single-access RAM memory has the advantage of very simple integration within an ASIC (3000 doors for 2048 bits). The description which follows with reference to the appended drawings, given by way of nonlimiting examples, will make it clear what the invention consists of and how it can be implemented.
La figure 1 est un schéma synoptique général du dispositif d'échange de données asynchrones conforme à l'invention.Figure 1 is a general block diagram of the asynchronous data exchange device according to the invention.
La figure 2 est une décomposition en cycles d'horloge d'une instruction exécutée par le microprocesseur-maître du dispositif de l'invention.FIG. 2 is a breakdown into clock cycles of an instruction executed by the master microprocessor of the device of the invention.
La figure 3 est un chronogramme de synchronisation entre un microprocesseur-maître et microprocesseur-esclave.Figure 3 is a timing diagram between a microprocessor-master and microprocessor-slave.
Sur la figure 1 est représenté schématiquement un dispositif d'échange de données asynchrones entre un premier microprocesseur 10, qui sera appelé microprocesseur-maître dans la suite, et un deuxième microprocesseur 20, dit microprocesseur-esclave. Comme on peut le voir sur la figure 1 , l'échange de données asynchrones entre les deux microprocesseurs s'effectue par l'intermédiaire d'une interface constituée par une mémoire à accès aléatoire (RAM) 30 du type à simple accès.In Figure 1 is shown schematically an asynchronous data exchange device between a first microprocessor 10, which will be called microprocessor-master in the following, and a second microprocessor 20, called microprocessor-slave. As can be seen in FIG. 1, the exchange of asynchronous data between the two microprocessors takes place via an interface constituted by a random access memory (RAM) 30 of the single access type.
L'accès à la mémoire RAM 30 est en permanence sous le contrôle du microprocesseur-maître 10 en ce sens que lorsque le microprocesseur-esclave 20 demande d'accéder en lecture /écriture à une adresse donnée de la mémoire 30 (temps tQ du chronogramme de la figure 3), cette demande RD/WR est enregistrée par le microprocesseur- maître 10 à l'instant ti , suivant l'instant tg d'un cycle d'horloge du microprocesseur-maître 10 par exemple. Si, à cet instant ti , l'accès à la mémoire RAM 30 n'est pas disponible du fait que le microprocesseur- maître 10 se trouve précisément en situation d'échange avec ladite mémoire 30, au cours d'un des cycles d'exécution 1 à N-2 de l'instruction représentée sur la figure 2, le microprocesseur-maître 10 délivre au microprocesseur-esclave 20 un signal S^ d'allongement de temps d'accès à la mémoire RAM 30, l'effet du signal S^ étant de suspendre le cycle de lecture /écriture du microprocesseur-esclave 20.Access to the RAM memory 30 is permanently under the control of the master microprocessor 10 in the sense that when the slave microprocessor 20 requests read / write access to a given address of the memory 30 (time tQ of the timing diagram of FIG. 3), this request RD / WR is recorded by the microprocessor-master 10 at the instant ti, according to the instant tg of a clock cycle of the microprocessor-master 10 for example. If, at this instant ti, access to the RAM memory 30 is not available because the microprocessor-master 10 is precisely in a situation of exchange with said memory 30, during one of the cycles of execution 1 to N-2 of the instruction represented in FIG. 2, the microprocessor-master 10 delivers to the microprocessor-slave 20 a signal S ^ of elongation access time to the RAM memory 30, the effect of the signal S ^ being to suspend the read / write cycle of the microprocessor-slave 20.
A titre indicatif, le signal S d'allongement d'accès à la mémoireAs an indication, the signal S for extending memory access
30 est connu sous le terme "READY" pour certains microprocesseurs de la société INTEL ou "DTACK" pour ceux de la société MOTOROLA. Pour les microprocesseurs qui ne disposent pas de signaux St d'allongement d'accès, tels que le 8031 d'INTEL, il est prévu dans ce cas que le microprocesseur-maître 10 soit apte à suspendre le fonctionnement du microprocesseur-esclave 20 en stoppant l'horloge de cadencement dudit microprocesseur-esclave.30 is known under the term "READY" for certain microprocessors from the company INTEL or "DTACK" for those from the company MOTOROLA. For microprocessors which do not have access extension St signals, such as the INTEL 8031, provision is made in this case for the microprocessor-master 10 to be able to suspend the operation of the microprocessor-slave 20 by stopping the clock clock of said microprocessor-slave.
Ainsi que le montre la figure 2, une instruction exécutée par le microprocesseur-maître 10 comporte, outre les cycles d'exécution 1 à N- 2 avec ou sans accès à la mémoire RAM 30, un cycle initial O "FETCH" d'acquisition d'un code opératoire et deux cycles finaux, N- l et N, d'accès à la mémoire 30 en écriture AM ou en lecture AM-R par le microprocesseur-esclave 20. Ces cycles AM et AM-R ont donc pour effet de permettre l'échange de données asynchrones entre les deux microprocesseurs 10, 20 à l'adresse de la mémoire RAM 30 définie par le microprocesseur-esclave 20 et enregistrée par le microprocesseur 10 à l'instant ti . On comprendra que les cycles AM et AM-R d'échange avec le microprocesseur-esclave 20 faisant partie intégrante des instructions exécutées par le microprocesseur-maître 10, celui-ci n'est en rien perturbé ni ralenti par l'échange de données.As shown in FIG. 2, an instruction executed by the master microprocessor 10 comprises, in addition to the execution cycles 1 to N- 2 with or without access to the memory RAM 30, an initial acquisition cycle O "FETCH" of an operating code and two final cycles, N-1 and N, of access to the memory 30 in write AM or in read AM-R by the microprocessor-slave 20. These cycles AM and AM-R therefore have the effect allow the exchange of asynchronous data between the two microprocessors 10, 20 at the address of the RAM memory 30 defined by the microprocessor-slave 20 and recorded by the microprocessor 10 at time ti. It will be understood that the AM and AM-R cycles of exchange with the slave microprocessor 20 being an integral part of the instructions executed by the master microprocessor 10, the latter is in no way disturbed or slowed down by the exchange of data.
Sur 1-e chronogramme de la figure 3, le cycle AM a lieu entre les' instants t2 et pendant cet intervalle le microprocesseur-maître 10 écrit des données qui sont lues par le microprocesseur-esclave 20, tandis qu'entre les instants t_ et t_. définissant le cycle AM-R, le microprocesseur-maître 10 lit les données écrites par le microprocesseur-esclave 20. Enfin, après détection du cycle AM-R, le signal S^ est basculé à l'instant t5 marquant ainsi la fin du cycle RD/WR du microprocesseur- esclave 20.In the timing diagram of FIG. 3, the cycle AM takes place between the instants t2 and during this interval the microprocessor-master 10 writes data which are read by the microprocessor-slave 20, while between the instants t_ and t_. defining the AM-R cycle, the microprocessor-master 10 reads the data written by the microprocessor-slave 20. Finally, after detection of the AM-R cycle, the signal S ^ is switched at time t5 thus marking the end of the RD / WR cycle of the microprocessor-slave 20.
Bien entendu, si le dernier cycle d'exécution d'une instruction exécutée par le microprocesseur-maître 10 ne nécessite pas d'accès à la mémoire 30, ce cycle pourra être confondu avec le premier cycle AM d'échange avec le microprocesseur-esclave 20. Of course, if the last cycle of execution of an instruction executed by the master microprocessor 10 does not require access to the memory 30, this cycle could be confused with the first cycle AM of exchange with the microprocessor-slave 20.

Claims

REVENDICATIONS
1 - Dispositif d'échange de données asynchrones entre deux microprocesseurs ( 10, 20) par l'intermédiaire d'une interface constituée par une mémoire (30) à accès aléatoire, caractérisé en ce que : - ladite mémoire (30) à accès aléatoire est du type à simple accès, lequel est contrôlé par l'un desdits microprocesseurs, dit microprocesseur-maître ( 10),1 - Device for exchanging asynchronous data between two microprocessors (10, 20) via an interface constituted by a memory (30) with random access, characterized in that: - said memory (30) with random access is of the single access type, which is controlled by one of said microprocessors, called microprocessor-master (10),
- chaque instruction exécutée par ledit microprocesseur-maître comporte des cycles d'exécution suivis d'au moins deux cycles (AM, AM- R) d'échange de données en lecture / écriture avec le deuxième microprocesseur, dit microprocesseur-esclave (20),each instruction executed by said master microprocessor comprises execution cycles followed by at least two cycles (AM, AM-R) of data exchange in read / write with the second microprocessor, called microprocessor-slave (20) ,
- le microprocesseur-maître ( 10) est apte à allonger le temps d'accès du microprocesseur-esclave (20) à la mémoire (30) à accès aléatoire jusqu'à la fin du dernier cycle (AM-R) d'échange de données. 2 - Dispositif d'échange de données selon la revendication 1 , caractérisé en ce que ledit microprocesseur-maître ( 10) est apte à délivrer au microprocesseur-esclave (20) un signal S d'allongement de temps d'accès à la mémoire (30) à accès aléatoire.- the microprocessor-master (10) is able to extend the access time of the microprocessor-slave (20) to the memory (30) with random access until the end of the last cycle (AM-R) of exchange of data. 2 - Data exchange device according to claim 1, characterized in that said microprocessor-master (10) is capable of delivering to the microprocessor-slave (20) a signal S for extending the access time to the memory ( 30) random access.
3 - Dispositif d'échange de données selon la revendication 1 , caractérisé en ce que le microprocesseur- maître ( 10) est apte à suspendre le microprocesseur-esclave (20) en stoppant l'horloge de cadencement dudit microprocesseur-esclave.3 - Data exchange device according to claim 1, characterized in that the microprocessor-master (10) is able to suspend the microprocessor-slave (20) by stopping the clock for clocking said microprocessor-slave.
4 - Dispositif d'échange de données selon l'une quelconque des revendications 1 à 3, caractérisé en ce qu'au moins un desdits cycles d'échange de données est constitué par un cycle d'exécution sans accès à la mémoire (30) à accès aléatoire. 4 - Data exchange device according to any one of claims 1 to 3, characterized in that at least one of said data exchange cycles is constituted by an execution cycle without access to the memory (30) random access.
PCT/FR1998/001255 1997-06-18 1998-06-15 Device for exchanging asynchronous data between two microprocessors WO1998058324A1 (en)

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CA002294245A CA2294245A1 (en) 1997-06-18 1998-06-15 Device for exchanging asynchronous data between two microprocessors
EP98930854A EP0990208A1 (en) 1997-06-18 1998-06-15 Device for exchanging asynchronous data between two microprocessors

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FR97/07584 1997-06-18
FR9707584A FR2765006B1 (en) 1997-06-18 1997-06-18 DEVICE FOR EXCHANGING ASYNCHRONOUS DATA BETWEEN TWO MICROPROCESSORS

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0230664A2 (en) * 1985-12-25 1987-08-05 Nec Corporation Master slave microprocessor system with virtual memory
US4698753A (en) * 1982-11-09 1987-10-06 Texas Instruments Incorporated Multiprocessor interface device
EP0314069A2 (en) * 1987-10-26 1989-05-03 Matsushita Electric Works, Ltd. Multi-CPU system using common memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698753A (en) * 1982-11-09 1987-10-06 Texas Instruments Incorporated Multiprocessor interface device
EP0230664A2 (en) * 1985-12-25 1987-08-05 Nec Corporation Master slave microprocessor system with virtual memory
EP0314069A2 (en) * 1987-10-26 1989-05-03 Matsushita Electric Works, Ltd. Multi-CPU system using common memory

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FR2765006A1 (en) 1998-12-24
FR2765006B1 (en) 1999-07-16
EP0990208A1 (en) 2000-04-05

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