WO1998056039A1 - Utilisation de caracteristiques inherentes de redressement d'un substrat dans des dispositifs a semi-conducteurs - Google Patents

Utilisation de caracteristiques inherentes de redressement d'un substrat dans des dispositifs a semi-conducteurs Download PDF

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Publication number
WO1998056039A1
WO1998056039A1 PCT/US1998/011523 US9811523W WO9856039A1 WO 1998056039 A1 WO1998056039 A1 WO 1998056039A1 US 9811523 W US9811523 W US 9811523W WO 9856039 A1 WO9856039 A1 WO 9856039A1
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WO
WIPO (PCT)
Prior art keywords
substrate
rectifying characteristics
source
semiconductor device
inherent
Prior art date
Application number
PCT/US1998/011523
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English (en)
Inventor
Laurence P. Sadwick
J. C. Koniak
R. Jennifer Hwu
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University Of Utah Research Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University Of Utah Research Foundation filed Critical University Of Utah Research Foundation
Publication of WO1998056039A1 publication Critical patent/WO1998056039A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors

Definitions

  • This invention relates generally to semiconductor devices and, more specifically, to devices and methods that utilize a previously unknown inherent rectifying characteristic of select semiconductor substrates, such as Gallium Arsenide (GaAs) substrates, to reduce leakage currents and provide rectifying behavior in high temperature and other semiconductor devices.
  • select semiconductor substrates such as Gallium Arsenide (GaAs) substrates
  • a positive drain-to-source voltage V DS applied between drain and source terminals 10 and 12 of a conventional depletion-type MEtal-Semiconductor Field-Effect Transistor (MESFET) 14 causes electrons e " to flow from ground, into the source terminal 12, through an n + source region 16, an n-type channel 18, and an n + drain region 20, and out the drain terminal 10.
  • MESFET MEtal-Semiconductor Field-Effect Transistor
  • a negative gate-to-source voltage V GS applied at a gate terminal 22 controls a depletion region 24 within the channel 18 that "pinches" the flow of electrons e ' in the channel 18 and thereby controls the drain current I D , as is desirable.
  • a Gallium Arsenide (GaAs) substrate 26 of the MESFET 14 is designed to behave as a semi-insulator by restricting electron flow e " between the source and drain regions 16 and 20 primarily to the channel 18.
  • GaAs Gallium Arsenide
  • I SUB _ LEA K * S a leakage portion of the drain current I D observed as a result of the flow of electrons e " through the GaAs substrate 26
  • I GAT E_ LEAK * S a leakage portion of the drain current I D observed as a result of the flow of electrons e * from the gate terminal 22.
  • leakage mechanisms other than I SUB _ LEAK and I GATE LEAK may also be present in the MESFET 14, but their discussion is not necessary to an understanding of the present invention.
  • leakage currents I SUB LEAK and I GATE LEAK are not pinched within the channel 18 by the depletion region 24, these currents operate beyond the control of the depletion region 24 and the gate-to-source voltage V GS , and thus add an undesirable uncontrolled component to the drain current I D .
  • the effect of this uncontrolled component is relatively minor at the ambient temperature under discussion because the leakage currents I SUB LEAK and I GATE LEAK are relatively minor portions of the drain current I D at this temperature, the reduction is significant enough to have encouraged efforts to reduce the undesirable effects of the leakage currents
  • a substrate terminal 28 is attached to the GaAs substrate 26 of the conventional MESFET 14, and a positive substrate voltage V SUB greater than the drain-to-source voltage V DS is applied to the terminal 28.
  • V SUB positive substrate voltage
  • the Inoue et al. method shown in Figure 2 can be problematic, because the substrate current I SUB drawn by the substrate terminal 28 can be substantial.
  • the substrate current I SUB drawn by the substrate terminal 28 can be substantial.
  • at elevated ambient temperatures of about 100°C to 200 °C and above enough thermally generated carriers appear within the GaAs substrate 26 to support a substantial flow of electrons e " from the source region 16 into the GaAs substrate 26, thus dramatically increasing the substrate current I SUB drawn by the substrate terminal 28.
  • this substantial substrate current I SUB can be a significant problem.
  • the Inoue et al. method is of limited usefulness in high-temperature environments, where a great need presently exists for a solution to excess leakage currents in semiconductor devices.
  • Such a device and method would preferably draw minimal current, in contrast to the Inoue et al. method described above, and would be capable of doing so even in high temperature environments including, for example, in automotive electronics, in well bores, in high-temperature portions of airplanes (e.g. , the wings), in the presence of high-temperature chemical reactions, in high radiation environments, and in high-power radar electronics.
  • Gallium- Arsenide (GaAs) wafers some wafers exhibit inherent resistive behavior when a differential voltage is applied to them, as would be expected, while other wafers exhibit previously unknown inherent rectifying characteristics.
  • inherent rectifying characteristics it is meant that the wafers exhibit diode-like behavior in a raw, pre-fabrication state.
  • the inventors expect that inherent rectifying characteristics will also be exhibited by other III-V type semiconductor wafers, and by semiconductor wafers having III-V-like behavior. The inventors exploit these inherent rectifying characteristics in semiconductor devices to reduce leakage currents, as will be described below.
  • One embodiment of the present invention is a method for sorting through a group of semiconductor wafers for those wafers on which semiconductor devices may be fabricated that will operate with reduced leakage currents.
  • each of the wafers in the group is tested for inherent rectifying characteristics, and those wafers that have inherent rectifying characteristics are then selected for fabrication.
  • the testing may be accomplished by applying a varying voltage differential to each of the wafers and then measuring current flow through the wafers as a function of the varying voltage differential.
  • Another embodiment of the present invention is a method for making a semiconductor device, such as a MEtal-Semiconductor Field-Effect Transistor (MESFET) or other transistor.
  • a semiconductor device such as a MEtal-Semiconductor Field-Effect Transistor (MESFET) or other transistor.
  • MESFET MEtal-Semiconductor Field-Effect Transistor
  • a substrate is provided that has inherent rectifying characteristics, such as a selected GaAs or other III-V type substrate, and the semiconductor device is then fabricated on the substrate.
  • a further embodiment of the present invention is a method for reducing leakage currents in a semiconductor device.
  • the semiconductor device is fabricated on a substrate having inherent rectifying characteristics. This may be accomplished by fabricating a depletion or enhancement-type MESFET transistor on a selected GaAs substrate having inherent rectifying characteristics by implanting n + source and drain regions in the GaAs substrate, forming an n-type channel in the GaAs substrate between the n + source and drain regions, and attaching a metal gate to the GaAs substrate proximate the n-type channel to form a Schottky barrier between the gate and the channel.
  • the substrate is reverse biased by, for example, a voltage differential applied to the substrate, in order to reduce leakage currents in the device. Because the substrate is reverse biased, it draws minimal current, in contrast to the Inoue et al. method described above.
  • a semiconductor device such as a diode or a transistor, includes a substrate having inherent rectifying characteristics, such as a selected GaAs substrate.
  • a pair of terminals are coupled to the substrate so a voltage differential applied between the terminals may cause the substrate to exhibit its rectifying characteristics.
  • the terminals may comprise, for example, a substrate terminal and a source or drain terminal, or anode and cathode diode terminals.
  • a system for use in a high-temperature environment includes a structure for use in the environment that attains a high temperature in the environment.
  • the structure may be, for example, an engine or other part in a motorized vehicle, a housing that is inserted into a well bore, an airplane part, such as a wing, a chemical or other substance that undergoes a reaction in the environment, a part of a nuclear reactor or a satellite, or a part of a radar apparatus.
  • the system also includes a semiconductor device as described above adjacent the structure.
  • the present invention thus provides an improved device and method for reducing leakage currents in semiconductor devices.
  • the device and method draw minimal current, in contrast to the Inoue et al. method described above that was designed to minimize noise at room temperature, and are capable of doing so even in high temperature environments.
  • Figure 1 is a cross-sectional side view and schematic of channel and leakage currents in a conventional MEtal-Semiconductor Field-Effect Transistor (MESFET);
  • Figure 2 is a cross-sectional side view and schematic of a conventional method for reducing the negative effects of the leakage currents in the MESFET of Figure 1 ;
  • Figure 3 is a sectional isometric view and schematic of a method for testing a substrate for inherent rectifying characteristics in accordance with the present invention;
  • Figures 4A and 4B are respective graphs of current flowing through the substrate of Figure 3 as a function of a voltage applied across the substrate when the substrate has inherent rectifying characteristics and when it does not;
  • Figure 5 is a cross-sectional side view and schematic of a MESFET incorporating a substrate having inherent rectifying characteristics in accordance with the present invention in order to reduce leakage currents through the substrate;
  • FIG. 6 is a schematic of a diode incorporating a substrate having inherent rectifying characteristics in accordance with the present invention.
  • FIGS 7A, 7B, 7C, 7D, 7E, 7F, and 7G are illustrations of the MESFET of Figure 5 respectively incorporated into an engine of a vehicle, a housing in a well bore, a part of an airplane, a probe in a beaker, a nuclear reactor, a satellite, and a radar apparatus.
  • Best Mode for Carrying Out the Invention As shown in Figure 3, a Gallium- Arsenide (GaAs) wafer 30 is tested for previously unknown inherent rectifying characteristics by applying a varying differential voltage V TEST to the wafer 30 and measuring current flow I TEST through the wafer 30 as a function of the differential voltage V TEST using a current meter 32.
  • GaAs Gallium- Arsenide
  • Type III-V semiconductor wafers other than GaAs wafers, and semiconductor wafers having type ⁇ l-V-like behavior may also exhibit inherent rectifying characteristics and, thus, may also work for purposes of the present invention.
  • Such wafers include Indium-Phosphide (InP) wafers, Gallium-Phosphide (GaP) wafers, and Gallium-Nitride (GaN) wafers.
  • InP Indium-Phosphide
  • GaP Gallium-Phosphide
  • GaN Gallium-Nitride
  • the wafer 30 may exhibit inherent rectifying characteristics when tested using the method shown in Figure 3. Specifically, the wafer 30 may allow current I TEST to pass in one direction in increasing amounts when the differential voltage V TEST is positive, and may not allow current I TEST to pass in the other direction in any appreciable amount when the differential voltage V TEST is negative.
  • the wafer 30 may instead exhibit inherent resistive behavior, as would conventionally be expected, when tested using the method shown in Figure 3. Such a wafer 30 exhibiting resistive behavior generally would not work for purposes of the present invention.
  • an inventive depletion-type MEtal-Semiconductor Field-Effect Transistor (MESFET) 50 is fabricated on a GaAs substrate 52 that exhibits inherent rectifying characteristics such as those shown in Figure 4A.
  • MESFET MEtal-Semiconductor Field-Effect Transistor
  • the present invention is not limited to depletion-type MESFET' s, but instead includes within its scope any semiconductor device, including diodes, enhancement-type MESFET 's, and high electron mobility transistors (HEMT's).
  • a positive drain-to-source voltage V DS applied between drain and source terminals 54 and 56 of the MESFET 50 causes electrons e " to flow from ground, into the source terminal 56, through an implanted n + source region 58, n-type channel 60, and n + drain region 62, and out the drain terminal 54. Externally, this flow of electrons e " is observed as part of a positive drain current I D flowing into the drain terminal 54.
  • a negative gate-to-source voltage V GS applied at a gate terminal 64 controls a depletion region 66 within the channel 60 that "pinches” the flow of electrons e " in the channel 60 and thereby controls the drain current I D .
  • a slightly positive gate-to-source voltage V GS may also be used.
  • the thermally generated carriers e " described immediately above would support an undesirable flow of electrons e " between the source and drain regions 58 and 62 through the GaAs substrate 52 (see prior art Figure 1).
  • a positive substrate voltage V SUB greater than the drain-to-source voltage V DS by about one volt applied to a substrate terminal 68 reverse biases the inherent rectifying characteristics (represented in Figure 5 by diode symbols) of the GaAs substrate 52, thus substantially reducing or preventing the flow of electrons e " through the substrate 52.
  • the MESFET 50 operates in a more controlled manner, even at higher temperatures.
  • the substrate voltage V SUB only needs to be of sufficient magnitude and polarity to reverse bias the GaAs substrate 52, and thus does not necessarily need to be about one volt greater than the drain-to-source voltage V DS to fall within the scope of the present invention. Also, it should be understood that other methods for reverse biasing the GaAs substrate 52 also fall within the scope of the present invention.
  • a GaAs substrate (not shown) that exhibits inherent rectifying characteristics such as those shown in Figure 4 A may be incorporated into a diode 70 having anode and cathode terminals 72 and 74.
  • the MESFET 50 of Figure 5 is particularly useful attached or adjacent to structures in high-temperature environments (e.g., those of about 100°C and higher), such as, respectively: an engine 80 or other part of a motorized vehicle (not shown); a housing 82 in a well bore 84; a wing 86 or other part of an airplane 88; a probe 90 or other structure in the presence of a substance undergoing a high-temperature chemical reaction in, for example, a beaker 92; a part (not shown) subject to radiation in a nuclear reactor 94; a satellite 96 subject to radiation in space; and a part (not shown) of a radar apparatus 98.
  • high-temperature environments e.g., those of about 100°C and higher
  • adjacent includes “in,” “touching,” and “very close to, so as to be subject to the heat of, but not touching. " Also, it should be understood that the present invention is useful in any high-temperature environment, and is not limited to those enumerated above.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention concerne un nouveau transistor à effet de champ métal-semiconducteur (MESFET) (50) fabriqué sur un substrat d'arséniure de gallium (AsGa) (52) auquel on attribue des caractéristiques inhérentes de redressement jusque là ignorées, les courants de fuite du substrat étant réduits ou éliminés pendant le fonctionnement du MESFET (50) par application d'une polarisation inverse au substrat (52) avec une tension de polarisation mesurant un volt de plus que les tensions appliquées à la source (56) ou au drain (54) du MESFET (50). Le MESFET est tout particulièrement adapté à des environnements à hautes températures compte tenu des problèmes classiques qu'ils soulèvent, notamment ceux liés aux courants de fuite des substrats. Ainsi, les caractéristiques inhérentes de redressement attribuées au substrat de AsGa (52) autorisent son utilisation dans la fabrication d'une diode.
PCT/US1998/011523 1997-06-03 1998-05-29 Utilisation de caracteristiques inherentes de redressement d'un substrat dans des dispositifs a semi-conducteurs WO1998056039A1 (fr)

Applications Claiming Priority (2)

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US86830097A 1997-06-03 1997-06-03
US08/868,300 1997-06-03

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3150021A (en) * 1961-07-25 1964-09-22 Nippon Electric Co Method of manufacturing semiconductor devices
US3886580A (en) * 1973-10-09 1975-05-27 Cutler Hammer Inc Tantalum-gallium arsenide schottky barrier semiconductor device
US3924154A (en) * 1973-11-21 1975-12-02 Floyd M Minks Voltage regulator for alternating current lighting system
US4601096A (en) * 1983-02-15 1986-07-22 Eaton Corporation Method for fabricating buried channel field effect transistor for microwave and millimeter frequencies utilizing molecular beam epitaxy
US4803526A (en) * 1984-11-02 1989-02-07 Kabushiki Kaisha Toshiba Schottky gate field effect transistor and manufacturing method
US4972237A (en) * 1988-06-13 1990-11-20 Fujitsu Limited Metal-semiconductor field effect transistor device
US4974664A (en) * 1990-02-14 1990-12-04 Eaton Corporation Compensating for water pump speed variations in a tempered air system for vehicle passenger compartments
US5014108A (en) * 1990-05-15 1991-05-07 Harris Corporation MESFET for dielectrically isolated integrated circuits
US5639343A (en) * 1995-12-13 1997-06-17 Watkins-Johnson Company Method of characterizing group III-V epitaxial semiconductor wafers incorporating an etch stop layer

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3150021A (en) * 1961-07-25 1964-09-22 Nippon Electric Co Method of manufacturing semiconductor devices
US3886580A (en) * 1973-10-09 1975-05-27 Cutler Hammer Inc Tantalum-gallium arsenide schottky barrier semiconductor device
US3924154A (en) * 1973-11-21 1975-12-02 Floyd M Minks Voltage regulator for alternating current lighting system
US4601096A (en) * 1983-02-15 1986-07-22 Eaton Corporation Method for fabricating buried channel field effect transistor for microwave and millimeter frequencies utilizing molecular beam epitaxy
US4803526A (en) * 1984-11-02 1989-02-07 Kabushiki Kaisha Toshiba Schottky gate field effect transistor and manufacturing method
US4972237A (en) * 1988-06-13 1990-11-20 Fujitsu Limited Metal-semiconductor field effect transistor device
US4974664A (en) * 1990-02-14 1990-12-04 Eaton Corporation Compensating for water pump speed variations in a tempered air system for vehicle passenger compartments
US5014108A (en) * 1990-05-15 1991-05-07 Harris Corporation MESFET for dielectrically isolated integrated circuits
US5639343A (en) * 1995-12-13 1997-06-17 Watkins-Johnson Company Method of characterizing group III-V epitaxial semiconductor wafers incorporating an etch stop layer

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