WO1998044405A1 - Transition automatique entre les modes acpi3 et c2 - Google Patents

Transition automatique entre les modes acpi3 et c2 Download PDF

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Publication number
WO1998044405A1
WO1998044405A1 PCT/US1998/001907 US9801907W WO9844405A1 WO 1998044405 A1 WO1998044405 A1 WO 1998044405A1 US 9801907 W US9801907 W US 9801907W WO 9844405 A1 WO9844405 A1 WO 9844405A1
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WO
WIPO (PCT)
Prior art keywords
power
state
electronic device
processing unit
power state
Prior art date
Application number
PCT/US1998/001907
Other languages
English (en)
Inventor
David Poisner
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to AU61400/98A priority Critical patent/AU6140098A/en
Priority to DE19882269T priority patent/DE19882269T1/de
Priority to GB9922090A priority patent/GB2338806A/en
Publication of WO1998044405A1 publication Critical patent/WO1998044405A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Definitions

  • the present invention relates generally to reducing average power consumption by electronic devices. More particularly, the present invention relates to keeping the electronic devices in as low a power state as possible by turning off the electronic devices when various system caches do not need to be snooped.
  • Portable computers enable workers and students to have computing power on demand at a variety of locations and not be limited by the power supply of a desktop machine.
  • portable computing devices are frequently limited by the amount of time that they can run on battery power without reconnection to an AC power supply.
  • engineers are continuously trying to find ways of reducing the power consumption of various components of portable computers, including the central processing unit.
  • Keeping electronic devices such as a central processing unit, a memory controller or a memory in their lowest possible power state provides a number of benefits. For example, it allows battery operated machines to operate for longer periods of time between recharging. A reduction in power consumption also reduces thermal dissipation by the central processing unit. Reduced thermal dissipation allows the central processing unit to run at full speed for longer periods of time, while remaining within its thermal dissipation specifications. Reduced thermal dissipation also reduces the need for fans and other components used to prevent heat build-up in a computer. Finally, keeping the electronic device in a lower power state than could otherwise be achieved and reducing the number of transitions between power states improves system performance by reducing latencies caused by switching between designated power states.
  • ACPI advanced configuration and power interface
  • OSPM operating system directed power management
  • the goal of ACPI is to enhance power management functionality and robustness, as well as facilitating industry wide implementation of common power management features.
  • the ACPI specification is a publicly available document and can be obtained from the Internet at www//http.teleport.com/ ⁇ ACPI.
  • the ACPI defines a number of processor power states which are processor power consumption and thermal management states within a global working state. These processor states include a (i) C0 power state, (ii) Cl power state, (iii) C2 power state, and (iv) C3 power state.
  • the processor executes instructions and is at full power.
  • the processor is in a non-executing power state.
  • the C2 power state uses less power than the Cl state.
  • the processor still allows the bus to snoop the processor cache memory and thereby maintain cache coherency.
  • the C3 power state offers improved power savings over the Cl and C2 power states.
  • the processor cache ignores any snoops.
  • the operating software is responsible for ensuring that the processor caches maintain coherency.
  • the C0, Cl, C2 and C3 power states of the ACPI map into various power states of commercial microprocessors.
  • the C0 power state maps into a normal state in which all clocks are running
  • the C2 power state maps into a STOP GRANT state
  • the C3 power state maps into a STOP CLOCK state.
  • PCI Peripheral Component Interconnect
  • FIG. 1 A flow chart of a conventional implementation of a bus access is given in Figure 1.
  • the central processing unit CPU
  • the CPU disables an arbiter in step 104.
  • the CPU transitions to a C3 power state.
  • the power management logic recognizes a bus master request, the power management logic causes the CPU to transition from a C3 power state back to a high powered C0 power state and generates an interrupt in step 108.
  • Examples of conventional interrupts used in an INTEL® PENTIUM® processor include an Interrupt request (“INTR”) or an active-low system management interrupt (SMI#).
  • INTR Interrupt request
  • SI# active-low system management interrupt
  • the CPU which is now in a full power state re- enables the arbiter allowing the bus master to access the CPU's cache memory in step 112.
  • the CPU also determines whether it can wait for the bus master to complete its transfers in step 116. If the CPU can wait for the bus master to complete its transfers, the CPU waits for completion of the transfers in step 120 and returns to step 104 to disable the arbiter. Disabling the arbiter returns the CPU to the C3 power state in step 106. Otherwise, if the CPU cannot wait for the bus master to complete its transfers, the CPU can be placed in a C2 power state in step 124.
  • the invention relates to a method and apparatus of minimizing power consumption in an electronic system which has a processor with at least three power states including a full power state, a first power conserving state, and a second power conserving state.
  • the method comprises the steps of 1) placing the processor in a first conserving state, wherein the first power conserving state does not allow snooping of a cache memory; 2) detecting a bus master request to use a bus; 3) transitioning the processor directly into a second power conserving state, wherein the second power conserving state allows snooping of the cache; and 4) detecting when snooping of the cache is completed and returning the processor directly to the first power conserving state from the second power conserving state.
  • FIG. 1 is a flow diagram of the prior art method of handling CPU cache requests
  • FIG. 2 illustrates the transitions between processor power states in the ACPI specification as modified by the current invention
  • Figure 3 is a flow diagram of one method of handling CPU cache requests involving transitions from the C3 or deep sleep power state to the C2 power state without powering the CPU to the C0 power state;
  • Figure 4 is one embodiment of a chip implementation for performing the method shown in flow diagram 3;
  • Figure 5 is a second embodiment of a hardware system capable of performing the flow diagram shown in Figure 3.
  • Figure 2 illustrates a modified ACPI processor power state diagram.
  • the diagram includes both traditional transitions between power states and new transitions added by the present invention. All states, the C0 state 204, the Cl state 208, the C2 state 212 and the C3 state 216 are encompassed within a G0 working state 220.
  • a G0 working state is defined by the ACPI specification as a computer state where the system dispatches user mode (application) threads. In the G0 working state, these threads are executed. In this state, devices (peripherals) are dynamically having their power states changed.
  • a processor transitions between various processor power states including the C0 state 204, the Cl state 208, the C2 state 212, and the C3 state 216.
  • the processor is at full power.
  • the Cl state 208 defines a state in which the processor power state has the lowest latency. Aside from putting the processor in a non-executing power state, the Cl state 208 has no other software visible effects.
  • the C2 state is a second non-executing power state which offers improved power savings over the Cl state 208.
  • the C3 power state 216 offers improved savings over both the Cl state 208, and the C2 state 212. While in the C3 state 216, the processor's caches maintain the respective cache states but ignore any snoops. Thus the operating system is responsible for ensuring that the caches maintain coherency.
  • transitions between states occur from the C0 state 204 along path 222 to the Cl state 208 and back to the C0 state along return path 224. Transitions also occur from the C0 state 204 to the C2 state 212 along path 226 and return to the C0 state 204 along path 228. Finally, transitions occur from the C0 state 204 along path 230 to the C3 state 216 and return to the C0 state along path 232. Stopping a clock is one method of generating a transition from the C0 state to the C2 state along path 226. An interrupt will result in a transition of the system from the C2 state 212 along a path 228 to the C0 state 204.
  • a transition from the C0 state 204 along path 230 to the C3 state 216 may be achieved by: 1) asserting a stop clock signal, 2) asserting a sleep signal, and 3) stopping the clocks. An interrupt or request for access will cause the processor to transition from the C3 state 216 along path 232 to the C0 state 204.
  • Applicant's invention adds two more paths along which a processor can transition directly between a C3 state 216 and a C2 state 212.
  • a transition from the C3 state 216 to the C2 state 212 along path 234 can be accomplished by restarting a clock and/or deasserting an optional SLP# signal. It should be noted that it is unnecessary to deassert a stop clock signal (STPCLK#) for this transition. Stopping a clock transitions the processor from a C2 state 212 to a C3 state 216 along path 232. In some processors, an optional sleep signal may also be asserted. In the preferred embodiment of the invention, the STPCLK# on the Intel® PENTIUM® processor does not change while the processor is transitioning directly between the C3 state and the C2 state 212.
  • the C3 power state described in the specification will be equivalent to the lowest power state of a processor and should be considered to be a power state in which a CPU cannot maintain cache coherency. In this lowest power state, bus masters are prevented from accessing memory (because the CPU cannot snoop the cycles).
  • the ACPI C3 power state is equivalent to a stop clock state.
  • the C3 power state is called a sleep or a deep sleep state.
  • the C3 power state is simply defined as a low power state in which cache coherency cannot be maintained, and thus, snooping of the cache memory is not permitted.
  • the ACPI C2 power state is defined generally to be an intermediate power state between full power and the C3 power state.
  • the C2 power state is equivalent to the STOP GRANT state.
  • the C2 power state allows snooping memory accesses and maintaining cache coherency.
  • the C0 power state is defined for purposes of this invention as a full power state in which the CPU carries on its normal functions.
  • Figure 3 illustrates a method by which the bus master and power logic can access the cache of the CPU without raising the CPU to a full power state.
  • the CPU disables the arbiter in step 304 before transitioning into a lowest power or deep sleep C3 power state in step 308.
  • the CPU remains in the C3 power state until a bus master request or interrupt is received in step 309. If an interrupt is received, the processor transitions to a C0 power state in step 310. If instead, a valid bus master request is recognized in step 312, the power management logic (typically a chipset) causes the CPU to transition from the C3 power state to a C2 power state in step 316.
  • the power management logic typically a chipset
  • This transition is usually accomplished by either restarting the CPU clock and/or deasserting the optional SLP# signal to an INTEL® PENTIUM® processor. It should be noted that with an INTEL® PENTIUM® processor, no INTR or SMI# interrupts need to be generated and transmitted to the CPU. Unlike prior systems, the CPU transitions directly from the C3 power state to the C2 power state without first going to the C0 (full power) state.
  • the power management logic chipset enables the memory arbiter in step 320.
  • the memory arbiter may be found in a variety of memory controllers, similar to the one found in the Intel 82430TX. It should be noted that the CPU is not enabling the arbiter because the CPU is in a C2 power state and not executing instructions.
  • the bus master While the CPU is in the C2 power state, the bus master is allowed to access memory. As earlier defined, while the CPU is in a C2 power state (a low power state), the CPU can properly snoop the cycles and maintain cache coherency as done in step 324. After the bus master has completed its access of memory, the power management logic (chipset) detects the end of the bus master request and automatically transitions the CPU back to the C3 or deep sleep state in step 328. Thus, the memory access request issued while the CPU was in its lowest power C3 state did not cause the CPU to transition to the C0 or full power state. By avoiding the transition to the full power C0 state, the CPU saves both power and latency time by avoiding multiple transitions between states.
  • FIG. 4 illustrates one embodiment of the present invention.
  • a CPU 404 including a memory cache 408 is coupled to a memory controller 412 which helps direct flow of information to memory 416.
  • the memory controller 412 is coupled to an ACPI or other power management system 420 via a high speed link 422.
  • the power management logic 420 may include a bus interface, such as a Peripheral Component Interconnect (PCI), which connects a peripheral device 424 via a PCI or other appropriate bus 428.
  • PCI Peripheral Component Interconnect
  • the peripheral 424 may transfer PCI requests to the ACPI power management unit 420 along bus 428.
  • the power management unit 420 respond by transferring grant signals to the peripheral 424 along bus 428.
  • the power management unit 420 also controls a clock generator 432 which clocks other chips in the system, such as the CPU, memory controller and memory.
  • a typical "wake-up" from a C3 power to a C0 power state occurs when a request such as a PCI request is transmitted to the power management unit 420, which responds by switching on the clock generator 432 turning the clocks on.
  • PLL phase lock loop
  • the CPU transitions to a C2 state appropriate for snooping of the cache memory.
  • STPCLK# stop clock
  • an optional sleep signal may also be used.
  • the power management unit 420 enables the clock generator 432 upon receipt of the PCI requests from peripheral 424.
  • the start of the clock generator 432 starts the clocks to the memory controller 412 and the CPU 404.
  • the CPU's stop clock signal (STPCLK#) is not deasserted.
  • STPCLK# stop clock signal
  • a power management unit 420 asserts a grant along PCI bus 428 to the peripheral 424, resulting in a memory cycle which can be snooped by the CPU 404.
  • the power management unit 420 deasserts the PCI grant signal and turns off the clocks to the memory controller 412 and to the CPU 404 by appropriately signaling clock generator 432.
  • Figure 5 shows an alternate system capable of implementing transitions directly from a deep sleep or C3 power state to a C2 or low powered snoop state without taking the CPU to a full power state.
  • the CPU 504 including a cache 508 is connected to a memory controller 512.
  • the memory controller includes a memory arbiter (not shown).
  • the arbiter is coupled to a memory 516.
  • a peripheral 524 such as a PCI peripheral, transmits a request to the memory controller to access memory.
  • the request is routed to the power management unit 528 which in one embodiment may be a variant of the Intel PIIX4 chip.
  • the memory access request indicates to the power management unit 528 that the CPU should exit the C3 or deep sleep state.
  • the power management unit 528 starts a clock generator 532 which starts the clock to the CPU 504.
  • an optional sleep signal may also be triggered to "wake up" the CPU.
  • the stop clock signal is not deasserted.
  • the CPU does not transition to a full power state. Instead, the CPU transitions directly to a C2 power state.
  • a PLL OK signal is transmitted to the memory controller 512 indicating a grant signal may be transmitted from the memory controller to the peripheral 524.
  • the peripheral 524 performs a memory cycle which allows snooping of the cache 508 of CPU 504. When snooping is complete, the memory request from the peripheral 524 goes inactive, the grants are deasserted and the clock to the CPU is turned back off.
  • Both embodiments of the ACPI power management unit, the power management unit 420 of Figure 4 or 528 of Figure 5 allow the CPU to transition from a deep sleep or C3 to an intermediate low power C2 power state without powering all the way back up to the fully powered C0 power state by including logic to start a clock to the CPU when a PCI request is received.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

L'invention concerne un procédé de minimisation de la consommation électrique d'un processeur et la possibilité de disposer d'au moins trois modes d'alimentation électrique dont un mode de pleine puissance, un premier mode de gestion d'énergie et un second mode de gestion d'énergie. Ledit procédé consiste à mettre le processeur dans un premier mode de gestion d'énergie (308), jusqu'à ce qu'un bus maître demande la détection d'une antémémoire (309). A la réception de la demande, le processeur passe directement au second mode de gestion d'énergie (316), lequel autorise la détection de l'antémémoire. Une fois l'antémémoire détectée, le processeur repasse directement du second mode de gestion d'énergie au premier mode de gestion d'énergie (328).
PCT/US1998/001907 1997-03-31 1998-02-02 Transition automatique entre les modes acpi3 et c2 WO1998044405A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU61400/98A AU6140098A (en) 1997-03-31 1998-02-02 Automatic transitioning between acpi c3 and c2 states
DE19882269T DE19882269T1 (de) 1997-03-31 1998-02-02 Automatisches Übergehen zwischen ACPI-C3- und -C2-Zuständen
GB9922090A GB2338806A (en) 1997-03-31 1998-02-02 Automatic transitioning between ACPI C3 and C2 states

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83147297A 1997-03-31 1997-03-31
US08/831,472 1997-03-31

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DE (1) DE19882269T1 (fr)
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US9081575B2 (en) 2004-07-27 2015-07-14 Intel Corporation Method and apparatus for a zero voltage processor sleep state
US9141180B2 (en) 2004-07-27 2015-09-22 Intel Corporation Method and apparatus for a zero voltage processor sleep state
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US9223390B2 (en) 2004-07-27 2015-12-29 Intel Corporation Method and apparatus for a zero voltage processor
WO2006025999A1 (fr) * 2004-08-31 2006-03-09 Intel Corporation Procede et appareil pour commander des transitions d'etat de gestion d'alimentation
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GB2338806A (en) 1999-12-29
AU6140098A (en) 1998-10-22
DE19882269T1 (de) 2000-05-11

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