WO1998038581A1

WO1998038581A1 - A device for digital signal processing

Info

Publication number: WO1998038581A1
Application number: PCT/BG1997/000002
Authority: WO
Inventors: Kristian Rusanov Angelov
Original assignee: Kristian Rusanov Angelov
Priority date: 1997-02-28
Filing date: 1997-02-28
Publication date: 1998-09-03
Also published as: AU1761497A

Abstract

A device for digital signal processing, applied in the sphere of radio-electronics for parallel signal processing in analogue technique and parallel data processing in digital technique. The problem, concerning creating of a device for digital signal processing which scheme provides possibility for achieving maximum processing speed. The device consists of a decoder (1), connected to registers (5). The outputs of the registers (5) are three-bit and are connected to controlling inputs (10) of two-way buffers (11). The input/outputs of the peripheral two-way buffers (11) form the input/outputs (16) of the device and an operative register matrix (6) is built up. The two-way buffers (11) are forming a logical processor (12). The two-way buffers (11) could have seven states and are cross-connected to each other in the form of a three-dimensional grid.

Description

A DEVICE FOR DIGITAL SIGNAL PROCESSING

TECHNICAL FIELD

The invention refers to a device for digital signal processing that could be applied in the whole sphere of radio-electronics, especially for holding the parallel signal processing in analogue technique and parallel data processing in digital technique.

BACKGROUND ART

A device for digital signal processing is known, using a computer, the main way for data processing and an analogue-to-digital converter for converting analogue signals into digital data. The computer is built of a digital processor, RAM and ROM, clock-pulse generator and a input- output device. All blocks are connected to each other via a data bus, an address bus and a control bus. (1 )

In the described device, the analogue input signal is converted to digital by the analogue-to-digital converter and is entering the memory and the digital processor via the input-output device, where the signal is subjected to computations with different arithmetical and logical operations according to the instructions of a predetermined program. The computing operations are functionally equivalent to the analogue operations such as amplification, reduction, modulation and detection of the signal. For example, the input signal multiplication by a special number corresponds to the operation "amplification" in the analogue technique. In the digital processor, the computing processes are held mainly by an arithmetical logical device with a multiplier and with the help of registers, multiplexers, RAM and ROM. The sequence of the operations in the computing process depends on the predetermined program, that could be changed for the different signal processing types. Each instruction of the predetermined program is addressed to control the processes in the digital processor with the help of the clock pulses. The data of the predetermined program enter the data bus via the input - output device, entering, after that, the address memory of RAM for storage. The address memory is maintained by the microprocessor via the address bus, the control bus and using the control program, kept in ROM. When the program is input, the data bus is used for the input of the input signal via the input - output device of the RAM and the microprocessor and for the output of the processed signal. The microprocessor is controlled by the clock-pulse generator, its pulses defining the sequence of processor's operations for executing the instructions or for controlling the read and write mode.(1)

The main disadvantage of the mentioned device is that the instructions and the input digital signal are input and executed consequently for it is impossible these data to be output simultaneously on the data bus or to be fulfilled simultaneously by the microprocessor. Several clock pulses, respectively certain time are necessary for processing a singe unit input signal. The principal of consequential data processing is restricting the possibilities for reaching maximum processing speed. DISCLOSURE OF INVENTION

The technical problem, solved in the present invention is to create a device for digital signal processing, the scheme of which provides good possibility for achieving maximum processing speed.

Digital technique provides devices with abilities for holding the necessary direct operations, such as parallel analogue-to-digital converters, adders, parallel multipliers, coders, decoders, digital comparators and others. These devices could be connected in a predefined way, therefor to receive a special desired effect of parallel signal processing. The main disadvantage is that in achieving different variants of parallel processing, the devices should be connected in different ways or even replaced by other devices.

In digital technique are applied logical elements possessing few basic functions : OR; NOR; AND; NAND; and EXCLUSIVE OR. Counters, registers, decoders, triggers, digital comparators, adders, etc. could be built up, applying these elements. Each function could be converted either by inverting the input or output of the logical element, or by a combination of a few logical elements' functions. Besides, few buffers with open collectors could form a function if their outputs are connected in one point with common load. The application of inverting buffers allows forming different functions. Thus, a set of mutually connected buffers could build devices for digital technique.

The technical problem is solved by building up a device for digital signal processing after the following scheme. The device comprises a decoder, the inputs of the decoder being address input of the device and its outputs being connected to controlling inputs of three-bit registers, thus building up "an operative register matrix". The inputs of the registers are connected to a common three-bit input, necessary for the instructions' input, and their outputs, connected to the controlling inputs of two-way buffers, building up a processor for the execution of logical functions, further called "logical processor". The two-way buffers could have seven states and are cross - connected to each other in the form of a grid. Thus connected, the two-way buffers are positioned in the points of intersection of the grid lines. Each input/output of the two-way buffer is connected to a common point with the input/outputs of several neighbouring two-way buffers. The outputs of neighbouring two-way buffers have common load, connected between their common point and ground, the load being either a current generator, or a resistor. Each two- way buffer itself has an open emitter on its outputs. The input/outputs of the peripheral two-way buffers of the logical processor form the input/outputs of the device. The link of the two-way buffers could be held either in the form of a flat grid, or in the form of a three-dimensional grid for the different variants of the device.

The peripheral two-way buffers could also comprise an analogue comparator, determining the threshold of signal's logical "1" and "0". The non-inverting input of the comparator is connected to the device's input/output and its output - connected to an input of a logical element of a corresponding peripheral two-way buffer. The inverting inputs of the analogue comparators are the controlling inputs of the peripheral two- way buffers, therefor providing a possibility for matching the input-output levels of the device to other devices. Besides, it is possible to build up analogue-to-digital converters of parallel type, using precise comparators and connecting a circuit of standard voltages to their inverting inputs. The address inputs of the decoder and the inputs for instructions couid be connected to the input/outputs of the peripheral two-way buffers. The two-way buffer with seven states comprises two logical elements EXCLUSIVE OR, necessary for maintaining the inverse mode and two electronic switches, necessary for controlling the direction. Three controlling inputs for determining the states and two controlled input/outputs for the line are provided. The outputs of the logical elements EXCLUSIVE OR are connected to the inputs of the electronic switches, their outputs being connected to one of the inputs of the same logical elements and these connections forming the input/output of the two-way buffer. One of the controlling inputs is connected to the remaining input of the EXCLUSIVE OR logical elements and is used for maintaining the inverse mode. The other two controlling inputs are used for controlling the electronic switches, determining the direction of the buffer.

The seven states of the two-way buffer, according to the binary value of the controlling inputs, are as follows : a High impedance state on the two input/outputs. No connection between them;

■ Repeater;

■ Inverter;

■ Repeater with opposite direction;

■ Inverter with opposite direction;

■ Low impedance state on the two input/outputs. This state is blocking the buffer;

■ Low impedance state on the two input/outputs. Brings the two input/outputs into a blocked inverse state one towards the other or leaves them in this state.

The technical problem of reaching maximum processing speed in the above described device for digital signal processing is soived by achieving parallel data processing, when the input digital signal passes through elements of the device, being not detained, nor held on. The signal "flows" with the speed of switching the elements. The advantage of the device for digital signal processing is the achievement of maximum speed of signal processing.

DESCRIPTION OF THE ENCLOSED FIGURES

One example of the device for digital signal processing, corresponding to the description is presented on figures 1 and 2. Figure 1 is a block - functional scheme of the device; Figure 2 is showing a part of the line-scheme of the device; Figure 3 is a line-scheme of a two-way buffer with seven states.

MODEL OF INVENTION

The technical problem is solved by creating a device for digital signal processing, built up after the following scheme. The device comprises a decoder 1 , its inputs forming the address input 2 of the device. The outputs 3 of the decoder 1 are connected to the controlling inputs 4 of three-bit registers 5, building up an operative register matrix 6. The inputs 7 of the registers 5 are connected to a common three-bit input 8, necessary for the input of instructions and the outputs 9 f the registers 5 are connected to the controlling inputs 10 of two-way buffers 11 , building up a logical processor 12.The two-way buffers 1 1 could have seven states and are cross - connected to each other in the form of a grid. Thus connected, the two-way buffers 11 are placed on the points of intersection 13 of grid lines 14. Each input/output 15 of a two-way buffer 11 is connected to a common point 13 with input/outputs 15 of several neighbouring two-way buffers 1 1. The outputs of neighbouring two-way buffers 1 1 have common load, connected between their common point 13 and ground, being either a current generator, or a resistor (not marked). Each two-way buffer 1 1 , itself, has an open emitter on its outputs. The input/outputs of the peripheral two-way buffers 1 1 of the logical processor 12 are the device's input/outputs 16. In the different variants of the device, the two-way buffers 11 could be connected in the form of a flat grid or in the form of a three-dimensional grid. The peripheral two-way buffers could also possess an analogue comparator for determining the threshold of signal logical "1" and "0". The non-inverting comparator's input is connected to the device input/output 16, and its output - to a logical element input of a corresponding peripheral two-way buffer 11. The inverting inputs of the analogue comparators are controlling inputs of the peripheral two-way buffers 11 , providing a possibility for matching the device input/output levels to other devices. Besides, it is possible to form analogue-to-digital converters - parallel type, using precise comparators and connecting a circuit of standard voltages to their inverting inputs. The address inputs 2 of the decoder 1 and the inputs for instructions 8 could be connected to the input/outputs 16 of the peripheral two-way buffers 11.

The two-way buffer 11 could have seven states and comprises two EXCLUSIVE OR logical elements 17 and 18, necessary for controlling the inverse mode* and two electronic switches 19 and 20, necessary for controlling the direction. The two-way buffer possesses three controlling inputs Xa, Xb, Xc for determining the states and two controlled input/outputs A and B for the line. The outputs of the

Ε. Xs CLUSIVE OR logical elements 17 and 18 are connected to the inputs of the electronic switches 19 and 20, their outputs being connected to one of the inputs of the same logical elements 17 and 18 and these links form the input/output A ana B of the two-way buffer 1 1. The controiling input Xb is connected to the free input of the EXCLUSIVE OR logical elements 17 and 18 and is used for maintaining the inverse mode. The controlling inputs Xa and Xc are connected to the controlling inputs of the electronic switches 19 and 20, determining the direction of the buffer 11.

The seven states of the two-way buffer 1 1 , according to the binary value of the controliing inputs Xa, Xb, Xc, are as follows :

0X0 - High impedance state on the two input/outputs A and B. No connection between them;

001 - Repeater with direction from A to B; A is an input, B is an output;

011 - Inverter with direction from A to B; A is an input, B is an output;

100 - Repeater with direction from B to A; B is an input, A is an output;

110 - Inverter with direction from B to A; B is an input, A is an output;

101 - Low impedance state on the two input/outputs A and B. In this state the buffer is blocking;

111 - Low impedance state on the two input outputs A and B. This state brings the two inputoutputs A and B into a blocked inverse state one towards another or leaves them in this state. APPLICATION OF INVENTION

The operation of the device for digital signal processing is as

The input signal enters the logical processor 12 through the input/outputs 16 of the device's peripheral two-way buffers 1 1 , passes through it and is processed with the speed of switching of the elements building up the logical processor 12. The logical processor 12, itself, is ccntroiied by instructions, stored in the operative register matrix 6. The instructions are programs, used for logical processing of information. The instructions are prε-intrcduced in the software for storage. The multitude of instructions is spread in the operative register matrix 6 by the decoder 1. Each instruction, stored in a register cell 5 with its binary value, is controlling the state of a corresponding two-way buffer 1 1 in the logical processor 12. A group of special states of the two-way buffers 1 1 forms a logical function of elements in the digital technique. The processed signal is output on the input/outputs 16 of the peripheral two- way buffers 11 in the logical processor 12.

Bibliography : 1. A. Angelov, P. Petrov, Microprocessors in the systems of radio engineering, Technica, Sofia, 1989.

Claims

PATENT CLAIMS

1. A device for digital signal processing, comprising a decoder, its inputs being an address input of the device and its outputs being connected to controlling inputs of registers, characterised by the fact that '.he outputs of th registers (5) are three-bit and are connected to the controlling inputs (10) of two-way buffers (11 ), where the input/outputs of the peripheral two-way buffers (11 ) are input/outputs (16) of the device, and registers (5) inputs (7) are connected to a common three-bit input (8), thus building up an operative register matrix (6).

2. A device, in accordance with claim 1 , comprising two-way buffers (11 ), building up a logical processor (12).

3. A device, in accordance with ciaims 1 and 2, comprising two- way buffers (11 ) with seven states, cross-connected to each other in the form of a grid.

4. A device, in accordance with claims 1 ,2 and 3, comprising two- way buffers (1 1 ), placed, when cross-connected, on the points of intersection (13) of the grid lines (14), each input/Output (15) of a two- way buffer (11) being connected to a common point (13) with the input/outputs (15) of several neighbouring two-way buffers (1 1 ).

5. A device, in accordance with claims 1 ,2 and 3, comprising two- way buffers (11 ), the outputs of the neighbouring two-way buffers having open emitter and common load, connected between their common point (13) and ground.

6. A device, in accordance with claims 1 and 3, comprising two- way buffers (11 ), their cross-connection could be in the form of a fiat or three-dimensional grid.

7. A device, in accordance with any ciaim from 1 to 6, comprising a two-way buffer (1 1 ), built up of two EXCLUSIVE OR logical elements (17) and (18) and two electronic switches (19) and (20), possessing three controlling inputs Xa, Xb, Xc for determining the states and two controlled input/outputs A and B for the line, the outputs of the logical elements EXCLUSIVE OR (17) and (18) being connected to the inputs of the electronic switches (19) and (20), their outputs connected to one of the inputs of the same logical elements (17) and (18), thus forming input/output A and B of the two-way buffer (1 1 ), the controlling input Xb being connected to the free input of the EXCLUSIVE OR logical elements (17) and (18) and each of the other two controlling inputs Xa and Xc being connected to the controlling inputs of the electronic switches (19) and (20).