WO1998037475A3 - System and method for designing electronic circuits - Google Patents
System and method for designing electronic circuits Download PDFInfo
- Publication number
- WO1998037475A3 WO1998037475A3 PCT/US1998/002334 US9802334W WO9837475A3 WO 1998037475 A3 WO1998037475 A3 WO 1998037475A3 US 9802334 W US9802334 W US 9802334W WO 9837475 A3 WO9837475 A3 WO 9837475A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- architecture
- selected target
- representation
- representations
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/347—Physical level, e.g. placement or routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3932097P | 1997-02-07 | 1997-02-07 | |
US60/039,320 | 1997-02-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1998037475A2 WO1998037475A2 (en) | 1998-08-27 |
WO1998037475A3 true WO1998037475A3 (en) | 1999-02-18 |
Family
ID=21904843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/002334 WO1998037475A2 (en) | 1997-02-07 | 1998-02-06 | System and method for designing electronic circuits |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO1998037475A2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6425116B1 (en) | 2000-03-30 | 2002-07-23 | Koninklijke Philips Electronics N.V. | Automated design of digital signal processing integrated circuit |
US6817005B2 (en) | 2000-05-25 | 2004-11-09 | Xilinx, Inc. | Modular design method and system for programmable logic devices |
US6983427B2 (en) * | 2001-08-29 | 2006-01-03 | Intel Corporation | Generating a logic design |
US6640329B2 (en) * | 2001-08-29 | 2003-10-28 | Intel Corporation | Real-time connection error checking method and process |
US9087164B2 (en) | 2008-01-26 | 2015-07-21 | National Semiconductor Corporation | Visualization of tradeoffs between circuit designs |
US8813019B1 (en) | 2013-04-30 | 2014-08-19 | Nvidia Corporation | Optimized design verification of an electronic circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5544067A (en) * | 1990-04-06 | 1996-08-06 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
US5557533A (en) * | 1994-04-19 | 1996-09-17 | Lsi Logic Corporation | Cell placement alteration apparatus for integrated circuit chip physical design automation system |
-
1998
- 1998-02-06 WO PCT/US1998/002334 patent/WO1998037475A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5544067A (en) * | 1990-04-06 | 1996-08-06 | Lsi Logic Corporation | Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation |
US5557533A (en) * | 1994-04-19 | 1996-09-17 | Lsi Logic Corporation | Cell placement alteration apparatus for integrated circuit chip physical design automation system |
Also Published As
Publication number | Publication date |
---|---|
WO1998037475A2 (en) | 1998-08-27 |
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