WO1998036545A1

WO1998036545A1 - Method and apparatus for processing a multi-level fsk signal

Info

Publication number: WO1998036545A1
Application number: PCT/US1998/001029
Authority: WO
Inventors: Michael J. Deluca; Susan Chang
Original assignee: Motorola Inc.
Priority date: 1997-02-14
Filing date: 1998-01-20
Publication date: 1998-08-20

Abstract

A receiver (100) is used for processing a multi-level FSK signal, comprising a converter (101) for converting the multi-level FSK signal into a sequence of state transitions, and a baud rate detector (111). The baud rate detector (111) comprises in a plurality of sampling intervals, wherein each of the plurality of sampling intervals is offset by a first predetermined time from other sampling intervals, and wherein each of the plurality of sampling intervals is further subdivided into a plurality of recording intervals, a plurality of counters (502-508) for counting the sequence of state transitions that occur during at least a minimum number of the plurality of recording intervals. The baud rate detector (111) further comprises a baud rate detection circuit (524) for detecting the desired baud rate based on counts recorded in a memory (522).

Description

METHOD AND APPARATUS FOR PROCESSING A MULTI-LEVEL FSK

SIGNAL

Field of the Invention

This invention relates in general to the processing of radio signals, and in particular to a method and apparatus for demodulating a multilevel FSK (frequency shift keyed) signal and for detecting a desired baud rate of the multi-level FSK signal.

Background of the Invention

Currently, selective call receivers (SCR's) that receive multi-level FSK signals utilize asynchronous analog demodulation circuits. These circuits employ conventional front-end mixers for mixing a high frequency FSK signal (e.g., 900 MHz) to an intermediate frequency (IF)-FSK signal (e.g., 455 KHz). Generally, the IF-FSK signal is demodulated into baseband analog signals by a discriminator circuit that converts frequency signals to multi-level baseband voltage signals. For a four-level FSK signal, for example, the output of the discriminator is a four level voltage signal, each voltage level representing a symbol of data (i.e., two data bits of information).

Thereafter, the output of the discriminator is conditioned by a conventional post-detection filter which removes high frequency noise. Finally, the conditioned signal is processed by a conventional symbol detector (or bit slicer) which converts the four-level signal into digital symbol data.

A substantial portion of these circuits is designed with analog circuit techniques. Although these circuits are generally effective in demodulating FSK signals, they characteristically have several undesirable drawbacks. The most significant drawback being that of high energy consumption, which has an adverse effect on the battery life performance of the SCR's. Another significant drawback is the difficulty in manufacturing high quality SCR's that utilize these circuits. Moreover, the nature of an asynchronous analog demodulator creates several problems in properly detecting the baud rate of a multilevel FSK signal. For instance, the post-detection filter removes not only high frequency noise from the detected signal, but also harmonics of the signal itself, thereby affecting the integrity of demodulated data provided by the demodulator circuit. Consequently, prior art baud rate detectors that operate on the demodulated data have decreased sensitivity. Yet another disadvantage is that prior art baud rate detectors are incapable of processing baud rate information other than from demodulated data. Thus, prior art baud rate detectors are subject to the sensitivity performance of prior art demodulator circuits.

Hence, what is needed is a method and apparatus that overcomes the deficiencies of prior art analog demodulators and baud rate detectors. In particular, a method and apparatus is desired that would provide significant improvements over the energy consumption of prior art analog demodulators. Further, a baud rate detector is needed that detects baud rate information from a source providing a substantially higher level sensitivity than that of demodulated data provided by a demodulator circuit.

Brief Description of the Drawings

FIG. 1 is an electrical block diagram of a frequency shift keyed (FSK) receiver according to the present invention;

FIGs. 2 through 5 are illustrations of complex domain graphs of unconditioned in-phase and quadrature signals in a noise-free environment for each deviation of a multi-level FSK signal; FIG. 6 is an illustration depicting a sequence of state transitions of conditioned in-phase and quadrature signals;

FIG. 7 is an electrical block diagram of a state transition detector according to the present invention;

FIGs. 8 and 9 are illustrations of complex domain graphs of the in- phase and quadrature signals in a noisy environment;

FIG. 10 is an electrical block diagram of a magnitude deviation detector according to the present invention;

FIG. 11 is an electrical block diagram of a polarity detector according to the present invention; FIGs. 12 through 14 are illustrations of the performance of the receiver utilizing the demodulator circuit according to the present invention; FIG. 15 is an electrical block diagram of a baud rate detector according to the present invention;

FIG. 16 is an illustration of a timing diagram depicting the operation of the baud rate detector according to the present invention; FIGs. 17 and 18 are flow charts depicting the operation of the baud rate detector according to the present invention; and

FIG. 19 is an electrical block diagram of a selective call receiver utilizing the receiver according to the present invention.

Description of the Preferred Embodiment

FIG. 1 is an electrical block diagram of an FSK (frequency shift keyed) receiver 100 according to the present invention. The FSK receiver 100 comprises preferably a converter 101, a baud rate detector 111 and a demodulator circuit 110. The converter comprises a zero-IF mixer 102, an I-Q (in-phase and quadrature) limiter circuit 104, and a state transition detector 113. The zero-IF mixer 102 is a conventional non-coherent mixer comprised of in-phase and quadrature mixers driven from a substantially accurate local oscillator (LO) for generating an in-phase signal, and a quadrature signal, respectively. The zero-IF mixer 102 receives an RF-FSK signal (radio frequency FSK signal shown as RFin in FIG. 1) from a conventional high frequency antenna (not shown).

It will be appreciated that, alternatively, a conventional front-end mixer circuit such as, for example, a super-heterodyne circuit, along with a conventional quadrature mixer can be used in place of the zero-IF mixer 102. The front-end mixer is generally used for receiving FSK signals transmitted by a remote transmitter station at high frequencies (e.g., 900 MHz). After a high frequency FSK signal has been mixed by the front-end mixer circuit, an IF-FSK signal results, e.g., 455 KHz. The IF-FSK signal is then mixed down by quadrature mixer to generate an in-phase signal, and a quadrature signal, respectively.

Returning back to the preferred embodiment, once the zero-IF mixer 102 has mixed down the RF-FSK signal to basedband, the unconditioned in-phase and quadrature signals 103, 105 are then processed by the I-Q limiter circuit 104. The conditioning of these signals is performed by two low-pass filters (LPF) and two limiter circuits connected in tandem, respectively. The LPF's remove adjacent channel interference, while the limiters generate a two-level voltage signal representative of conditioned in-phase and quadrature signals (I_CH, and Q_CH) 106, 108, respectively. To do this, the limiter circuit utilizes a one-bit conventional analog-to-digital converter. The two-level voltage output of each limiter circuit is representative of a digital output, i.e., high ("1") and low ("0") digital representations.

The two-level in-phase and quadrature signals are then processed by a state transition detector 113, which detects transitions between states of the I-Q signals 108, 106 and generates state outputs which are applied to a state transition bus 115. The design and operation of the state transition detector 113 will be discussed in detail shortly. The data provided by the state transition bus 115 is then processed by the demodulator circuit 110, and the baud rate detector 111.

The demodulator circuit 110 demodulates these signals into digital symbol data. The demodulator circuit 110 in this example illustrates the demodulation of a four-level FSK signal. For this reason, the output of the demodulator circuit 110 is a two bit output signal that is applied to a demodulation bus 112. It will be appreciated that, alternatively, the demodulator circuit 110 is designed for demodulating other multi-level FSK signals (e.g., 2-level, 8-level, 16-level, etc.). Hence, the number of levels transmitted with an FSK signal is not critical to the present invention. The discussions that follow for the demodulator circuit 110, however, will be limited to illustrations of demodulating a four-level FSK signal according to the present invention. These discussions should be viewed as being substantially similar to discussions regarding the demodulation of a higher or lower number of levels of FSK signals according to the present invention.

The baud rate detector 111 processes the data provided by the state transition bus 115 and determines therefrom whether the multi-level FSK signal intercepted by the receiver 100 has a desired baud rate. Once the baud rate detector 111 has made a determination, it generates an output signal (baud rate detected), which is also applied to the demodulation bus 112.

The demodulation bus 112, which includes both the baud rate detector 111 output and the two bit output signal generated by the demodulator circuit 110, can be utilized by a processor for decoding and operating a selective call receiver, as will be discussed below. The discussions that follow will focus on the theory, design, and operation of the state transition detector 113 shown in FIG. 1. In particular, FIGs. 2-6 are provided to introduce the reader to the important principles which are utilized in the design (shown in FIG. 7) of the state transition detector 113 according to the present invention. Both the baud rate detector 111 and the demodulator circuit 110 utilize the data provided by the state transition detector 113.

FIGs. 8 and 9 are provided to introduce the reader to important principles which are utilized in the design of the demodulator circuit 110 according to the present invention. FIGs. 10 and 11 illustrate, by way of example, a hardware implementation of the demodulator circuit 110. And FIGs. 12-14 illustrate performance results contrasting the demodulator circuit 110 and prior art systems.

Following the discussions of the demodulator circuit 110, the design and operation of the baud rate detector 111 will be discussed according to the illustrations in FIGs. 15-18.

FIGs. 2 through 5 are illustrations of complex domain graphs of the unconditioned in-phase and quadrature signals 103, 105 in a noise-free environment for each deviation, respectively, of a four-level FSK signal. These graphs are presented to illustrate characteristics of the in-phase and quadrature signals that the present invention takes advantage of in demodulating and detecting a desired baud rate of a multi-level FSK signal. The graphs illustrate deviations of ±4800 Hz, and ±1600 Hz from a frequency reference (e.g., 900 MHz carrier). In a complex domain system, the in-phase signal (I) is a real signal, while the quadrature signal (Q) is a complex signal. After plotting the magnitude and phase of these signals in continuous time, the resulting graphs shown in FIGs. 2 through 5 are generated.

Depending on whether the frequency deviation with respect to a carrier signal is positive or negative, the plotted signals have a clockwise or counter-clockwise direction. In particular, for positive deviations the rotation is counter-clockwise, and for negative deviations the rotation is clockwise. This characteristic of the in-phase and quadrature signals is utilized by the demodulator circuit 110 and the baud rate detector 111 to determine the polarity of the frequency deviation, and to detect a desired baud rate, respectively. Another characteristic of in-phase and quadrature signals when plotted in a complex system, is that depending on the frequency of these signals several rotations may result around the complex domain. Table 1 illustrates an example for a four-level FSK signal transmitted at 3200 symbols per second (or effectively 6400 bits per second).

Table 1.

As Table 1 illustrates, a ±4800 Hz frequency deviation rotates 5 to 6 times in a counter-clockwise /clockwise direction around the complex domain. A ±1600 Hz frequency deviation rotates 1 to 2 times in a counterclockwise/clockwise direction around the complex domain. This characteristic of the in-phase and quadrature signals is utilized by the state transition detector 113 to provide rotation information to the demodulator circuit 110 and the baud rate detector 111. The demodulator circuit 110 counts the number of rotations around the complex domain and compares this information to predetermined ranges to determine the magnitude of the frequency deviation. The baud rate detector 111 counts the number of rotations around the complex domain at predetermined time intervals to determine whether the multi-level FSK signal has a desired baud rate.

Knowing direction of rotation, and number of rotations, the demodulator circuit 110 demodulates frequency deviation into baseband digital data. As noted above, however, the I-Q limiter circuit 104 conditions the in-phase and quadrature signals into digitized two level signals, i.e., "0" or "1." As a result, the continuous curves shown in FIGs. 2-5 cannot be reproduced. Instead, a digitized representation of the in- phase and quadrature signals remains. These digitized points of data occur only on the I and Q axis's (shown as "x's" on these figures). For the present invention, these crossings of the I and Q axis's are defined as states. As the conditioned in-phase and quadrature signals 106, 108 are sampled by the state transition detector 113, the state transition detector 113 monitors a sequence of states, and a sequence of state transitions. A sequence of states is defined as a sequence of crossings of the I and Q axis's. A sequence of state transitions, on the other hand, is defined as a sequence of transitions between states. Note a transition from one state to the same state is not considered a state transition, and therefore is ignored by the state transition detector 113 when counting state transitions. This, as it will be shown, is a useful method for filtering noise.

FIG. 6 is an illustration depicting a sequence of state transitions of the conditioned in-phase and quadrature signals 108, 106. Note that the conditioned in-phase and quadrature signals 108, 106 (referred to herein as I-Q signals 108, 106) differ from the unconditioned in-phase and quadrature signals 103, 105 in that the former signals 108, 106 are digitized while the latter signals 103, 105 are not. This results in the square waveforms of FIG. 6 as opposed to sinusoidal waveforms representative of the unconditioned in-phase and quadrature signals 103, 105 (not shown). In determining the present state of the I-Q signals 108, 106, the state transition detector 113 monitors each edge transition (rising-edge or falling-edge) of the I-Q signals 108, 106 over a symbol period.

In the example shown in FIG. 6, the first rising-edge of the Q signal occurs while the I signal is high. This represents state 1 in the complex domain system (i.e., the positive I axis; see FIGs. 2 through 5). The next signal to switch levels is the I signal (falling-edge). During this edge transition the Q signal is HI, thereby representing state 2 (i.e., the positive Q axis). Note the transition from state 1 to state 2 represents one sequence of a state transition. The next signal to switch is the Q signal (falling-edge). During this edge transition the I signal is LO, thereby representing state 3 (i.e., the negative I axis). Finally, the I signal switches from LO to HI. During this edge transition the Q signal is LO, thereby representing state 4 (i.e., the negative Q axis). The four edge transitions that follow represent a repetition of states 1 - 4 as depicted in FIG. 6. By tracking the sequence of state transitions, the state transition detector 113 determines from the order of the sequence the direction of the I-Q signals 108, 106 around the complex domain (i.e., counter-clockwise or clockwise rotation), and the number of rotations. This information is useful to the demodulator circuit 110 for demodulating the frequency deviation into digitized two-bit data conforming with Table 1, and also useful to the baud rate detector 111 for detecting a desired baud rate. FIG. 7 is an electrical block diagram of a state transition detector 113 according to the present invention.

As shown, the state transition detector 113 comprises two D Flip- Flops 202, 210, two Exclusive OR gates 204, 212, four AND gates 206, 209, 218, 214, and two inverters 208, 216. The state transition detector 113 receives as input the conditioned I-Q signals 108, 106 (also illustrated in FIG. 6). The D Flip-Flops 202, 210, which sample the I-Q signals 108, 106, are clocked by a sampling clock (CLK) that is several times faster than the rate of the I-Q signals 108, 106 (e.g., 76.8 KHz). The combination of the D Flip-Flop 202 and the X'OR 204 serves to detect a transition of the I signal. Similarly, the combination of the D Flip Flop 210 and X'OR 212 serves to detect a transition of the Q signal. When a transition is detected, these circuits generate an I_PULSE and a Q PULSE, respectively, and the four AND gates 206, 209, 218, 214 in combination with the two inverters 216 serve as state decoders. For example, assume that the I signal 108 experiences a falling-edge transition, and during that transition the Q signal 106 is high. The falling- edge transition is detected by the combination D Flip-Flop 202, and the X'OR 204, thereby generating a positive pulse, I_PULSE (the pulse duration is approximately one to one half cycles of the sampling clock— CLK). The I_PULSE is then received by both AND gates 206 and 209.

AND gate 206 then generates an output representative of state 2 when it detects the I_PULSE and when the Q signal 106 is HI (i.e., the condition for state 2). Similarly, AND gate 209 generates an output representative of state 4 when it detects the I_PULSE and when the Q signal 106 is LO (i.e., the condition for state 4).

The signal generated by AND gate 206 has a duration approximately equal to the duration of I_PULSE. The other state decoders operate in a similar manner as just described. These state outputs (i.e., states 1-4) are applied to a state transition bus 115, which is utilized by an algorithmic state machine (of the demodulator circuit 110) for tracking transitions between states, thereby providing a means for determining the polarity and magnitude of the frequency deviation received. Although this method of demodulation is effective in low-noise environments, further circuitry is necessary in communication systems that encounter Gaussian noise and Rayleigh fading. The operation of the demodulator circuit 110 is will be discussed shortly. It is worth noting, however, that the information provided in the state transition bus 115 is also used by the baud rate detector 111 for detecting a desired baud rate. A discussion of the baud rate detector 111 will follow a discussion of the demodulator circuit 110 in a noisy environment.

FIGs. 8 and 9 are illustrations of complex domain graphs of the I-Q signals 108, 106 in noisy environments. FIG. 8 illustrates a situation where I-Q signals 108, 106 have embedded noise that results in state 4 transitioning on itself once (the crossings where the noise occurred is noted with "x's"). After the noise has subsided, the rest of the I-Q plot remains normal. This type of noise is typically a short random burst noise. To avoid this type of false state transition, the demodulator circuit 110 utilizes an algorithmic state machine coupled to the state transition bus 115 which ignores state transition pulses of the same state.

The more complex situation arises when the burst error is a lengthy random error as shown in FIG. 9 (again the crossings where the noise occurred is noted with "x's"). In this example, states 3 and 4 have transitioned on themselves, which is ignored by the method just mentioned above. However, the transition from state 4 back to state 3, and then back to state 4 again is not ignored by the same circuit. For this situation, the demodulator circuit 110 utilizes a more sophisticated algorithm.

FIG. 10 is an electrical block diagram of a magnitude deviation detector 300, which includes an algorithm for resolving the noise problems discussed for FIGs. 8 and 9, according to the present invention. The magnitude deviation detector 300 is a circuit element included in the demodulator circuit 110. The purpose of the magnitude deviation detector 300 is to determine the magnitude (unit of Hz) of the frequency deviation signal being demodulated. Once it has made this determination, it generates a least significant bit (LSB) equal to a "1" or a "0." Referring back to Table 1, it is worth noting that when the LSB is equal to a "1," this data represents a magnitude of 1600 Hz of the frequency deviation. And when the LSB is equal to "0," the magnitude of the frequency deviation is 4800 Hz. The magnitude of the frequency deviation as described above, is determined by the number of rotations monitored about the complex I-Q domain, i.e., 5 to 6 rotations for 4800 Hz, and 1 to 2 rotations for 1600 Hz. Hence when 5 to 6 rotations are detected, the magnitude deviation detector 300 generates an LSB equal to "0," and when 1 to 2 rotations are detected the magnitude deviation detector 300 generates an LSB equal to "1." These results generally apply when there is negligible noise in the communication system, i.e., the examples given in FIGs. 2 through 5. However, in a noisy communication environment the number of rotations counted may include both clockwise and counter-clockwise rotations which may in effect generate an intermediate number of rotations between the two expected ranges.

For example, in a noisy environment an intermediate number of rotations, such as 3 rotations, may result. Since 3 rotations is neither in the range of 1 to 2 rotations, or 5 to 6 rotations for 1600 Hz and 4800 Hz deviations, respectively, further decision processing is necessary. The magnitude deviation detector 300, as will be shown shortly, also makes a determination under these conditions.

The magnitude deviation detector 300 comprises a counter- clockwise state transition counter 301, a clockwise state transition counter 302, a state counter 309, a summer 303, and three decision elements 304, 306, 308. The counter-clockwise state transition counter 301, and the clockwise state transition counter 302 are preferably each conventional algorithmic state machines programmed to count upward and downward sequences of states (not including same state transitions), respectively. The upward and downward sequences of states are representative of clockwise and counter-clockwise rotations, respectively, about the I-Q complex domain.

The counter-clockwise state transition counter 301, and the clockwise state transition counter 302 receive as input signals carried by the state transition bus 115. From these signals, the counters 301, 302 determine if the sequence of state pulses is representative of a clockwise rotation or a counter-clockwise rotation about the complex I-Q domain. Note as stated earlier above, transitions between the same state are ignored. To perform this function each counter comprises, for example, a conventional algorithmic state machine to count a sequence of state transitions, ignoring transitions between the same state. After tracking a number of clockwise and counter-clockwise rotations, the result of each counter is added by the summer 303. The summation result is then processed by the first decision element 304 which determines whether the number of rotations was greater than three. If the number of rotations is greater than three, then the first decision element 304 sets the LSB to "0," representative of the magnitude of the frequency deviation being 4800 Hz. That is, it presumes that the number of rotations counted are near the predetermined range of transitions for a frequency deviation of 4800 Hz (i.e., >3 rotations). If the number of rotations is less than or equal to three rotations, then the second decision element 306 is invoked.

The second decision element 306 looks to whether the number of rotations counted is equal to three. If it is not, i.e., there are less than 3 rotations, the second decision element 306 sets the LSB to "1," representative of the magnitude of the frequency deviation being 1600 Hz. Again, the magnitude deviation detector 300 presumes that the number of rotations counted is near the predetermined range of transitions for a frequency deviation of 1600 Hz (i.e., <3 rotations).

Up to now, the number of rotations is representative of a low noise environment consistent with the example signals shown in FIGs. 2 through 5. If the communication environment was predictably a low noise environment, then no further logic circuits would be necessary, and the magnitude deviation detector 300 would comprise only the circuits discussed up to now. However, in a noisy environment where a lengthy random burst can occur, the potentially illusive situation can result where the number of rotations is three, which is substantially in the middle of the two predetermine ranges of transitions (i.e., >3 and <3 rotations). When this situation happens, the third decision element 308 is invoked. To make a final determination on the magnitude of the frequency deviation being demodulated, the third decision element 308 utilizes information provided by the state counter 309. The state counter 309 also receives as input the state transition bus 115. However, rather than tracking state transitions only, the state counter counts all states. That is, any sequence of state pulses received from the state transition bus 115 is recorded by the state counter 309. This includes a sequence of state pulses that is representative of a state transition to the same state. The state counter 309 can also be viewed as a counter which tracks the number of crossings in the I-Q complex domain on the I and Q axis's, respectively. While the clockwise and the counter-clockwise state transition counters 301, 302 only records transitions between states that are not repeated.

Referring back to the present situation, when three rotations are detected, the third decision element 308 looks to the sequence of states counted by the state counter 309. If the third decision element 308 detects that the total number of states counted is above three, then the LSB is set to "0," representative of the magnitude of the frequency deviation being 4800 Hz. If the total number of states counted is equal to three, then the LSB is set to "1," representative of the magnitude of the frequency deviation being 1600 Hz.

This algorithm is statistically based. That is, more often than not the proper magnitude will be selected by the magnitude deviation detector 300. Although there may be instances when a magnitude in error is selected, this error may be readily compensated by the data transmitted in the FSK signal utilizing conventional error correction codes.

In summary, when the sequence of state transitions counted is between a first and second predetermined range of transitions, the step of determining the frequency deviation includes assigning a first magnitude of deviation to each frequency deviation demodulated when the sequence of states counted is above a predetermined threshold, and a second magnitude of deviation to each frequency deviation when the sequence of states counted is below the predetermined threshold. In this example, the first and second predetermined ranges were <3 transitions, and >3 transitions, respectively, and the predetermined threshold is 3. These two predetermined ranges pertain to the example of demodulating a four- level FSK signal. It will be appreciated that, alternatively, when demodulating higher or lower multi-level FSK signals (e.g., 2-level, 8- level, 16-level, etc.), the predetermined ranges for adjacent frequency deviations can be different, depending on, for example, the channel bandwidth assigned to a communication system.

FIG. 11 is an electrical block diagram of a polarity detector 400 according to the present invention. The polarity detector 400 is yet another circuit element of the demodulator circuit 110 of FIG. 1. Its purpose is to determine the polarity of the frequency deviation being demodulated. Referring back to Table 1, when the MSB is equal to a "1," this data is representative of positive frequency deviations, i.e., + 1600 Hz, or + 4800 Hz. When the MSB is equal to "0," the polarity of the frequency deviation is - 1600 Hz, or - 4800 Hz.

To make this determination, the polarity detector 400 utilizes a counter-clockwise state transition counter 402, and a clockwise state transition counter 404. These counters are functionally the same as the state transition counters noted in FIG. 10. In fact, it is preferable that these counters be utilized for the polarity detector 400. However, for the purpose of illustration, these counters have been duplicated in this example. The polarity detector 400 further includes a subtractor 406, two decision elements 408, 410, a memory element 412, and an inverter 414. During operation, the subtractor 406 subtracts the output of counter 402 from counter 404 and applies the result to the first decision element 408. If the result is greater than zero rotations, i.e., a counterclockwise rotation about the I-Q complex domain, then the first decision element 408 sets the MSB to "1," representative of a positive frequency deviation. If the difference generated by the subtractor 406 is equal to or less than zero, then the second decision element 410 is invoked. If the second decision element 410 detects less than zero rotations, i.e., clockwise rotations, then the MSB is set to "0," representative of a negative frequency deviation. However, if the number of rotations is equal in each direction, i.e., a subtraction result of zero, then the MSB is set to an opposite polarity of a previously determined frequency deviation. This is accomplished by storing the polarity of a previously demodulated frequency deviation in the memory element 412 and inverting it with the inverter 414 to generate a new MSB.

The rationale for assigning a polarity to the MSB that is the opposite polarity of a previously demodulated frequency deviation is that two unlike frequency deviations demodulated in sequence with each other may have some overlap between them, thereby causing the counters 402, 404 to detect two sequences, each sequence having a substantially equal number of state transitions going in opposite directions. That is, there may be a residue signal from the previously demodulated frequency deviation that overlaps into the demodulation of the present frequency deviation, thereby causing the polarity detector 400 to detect opposing sequences. When this happens, the polarity detector 400 presumes that a transition between frequency deviations is occurring, e.g., + 1600 Hz, to a new frequency deviation, e.g., - 1600 Hz. Thus, once the magnitude deviation detector 300, and the polarity detector 400 have determined the LSB and the MSB, respectively, the frequency deviation has been demodulated to baseband digital data. The digital data included in the MSB and the LSB is representative of a symbol of data.

FIGs. 12 through 14 are illustrations of the performance of the receiver 100 according to the present invention. The dashed plots 416 are representative of the performance of a conventional analog FSK receiver, while the solid plots 418 are representative of the performance of the receiver 100 of the present invention. These plots compare the performance between the conventional analog FSK receiver, and the receiver 100. The analog FSK receiver utilized for the present comparison comprises an analog discriminator (i.e., a frequency-to-voltage converter), a post-detection filter, and a multi-level symbol detector. All of these elements are conventional elements well known to those of ordinary skill in the art.

The plots of FIGs. 12 through 14 illustrate simulations of the bit- error-rate performance of a conventional analog FSK receiver using a conventional analog demodulator circuit and the receiver 100 including the demodulator circuit 110 of the present invention. Each simulation represents three communication environments. FIG. 12 represents a communication environment where static Gaussian noise is present during RF communications. FIG. 13 represents a communication environment that experiences Rayleigh fading (with walk speed v=5mph). And FIG. 14 represents a simulcast communication system having a relative power = 0 dB, simulcast delay = 80 us (~ 1/4 symbol) and a frequency offset = 30 Hz. As can be seen, the performance of the receiver 100 is substantially similar to that of the analog FSK receiver.

However, the receiver 100 has several advantages over the prior art analog receiver. First, the demodulator circuit 110 of the receiver 100 comprises digital components only, thereby allowing these circuits to be fully integrated into an IC. Also, with the advent of high performance low power IC technology such as CMOS logic, the power consumption of the receiver 100 is substantially superior to prior art analog receivers. Yet another advantage is that the demodulator circuit 110 is immune to upgrades in IC fabrication technology, e.g., 1 micron technology upgraded to 0.5 micron technology. Since the demodulator circuit 110 utilizes digital logic, redesign of the demodulator circuit 110 after a fabrication upgrade is not necessary. In contrast, because the circuits of the prior art analog receivers are primarily analog, such circuits generally require redesign. Finally, it is well-known in the art that the parametric values of analog circuits experience large variances during manufacturing. As a result, some level of tuning is required in the manufacture of each analog receiver. Because the demodulator circuit 110 has no analog components, tuning is not required.

The reader's attention is now directed to FIG. 15, which is an electrical block diagram of the baud rate detector 111 according to the present invention. The baud rate detector comprises a plurality of counters 502-508, a symbol/phase timer 520, a memory 522 and a baud rate detection circuit 524. The plurality of counters 502-508 are used for counting the sequence of state transitions generated by the state transition detector 113 and received on the state transition bus 115.

For detecting whether a four-level FSK signal has a desired baud rate, the baud rate detector 111 preferably comprises four counters 502-508 for counting the sequence of state transitions present in the state transition bus 115. Each counter comprises a clockwise counter and a counter-clockwise counter (not shown) similar to the counters 402, 404 shown in FIGs. 10 and 11. The clockwise and counter-clockwise counter outputs are applied to a subtractor (not shown) which subtracts the result of one counter from the other, similar to the subtractor 406 of FIG. 11.

It is not critical which counter is considered the subtrahend or the minuend as long as all of the counters of the baud rate detector 111 apply consistently the same standard. For the purpose of discussions below, the output of the counter-clockwise counter will be considered the minuend and the output of the clockwise counter will be considered the subtrahend. Hence, when the counter-clockwise counter counts five counter-clockwise rotations and the clockwise counter counts two clockwise rotations, the subtrator generates a net result of +3 rotations. Each counter 502-508 provides a net result of rotations counted in the output signals 510-516, respectively. The output signals 510-516 are then applied to a memory bus 518 (shown as a thick signal line). Also shown for each counter, is an enable count input (represented by the symbol ">"). The enable count input is utilized by each counter 502- 508 to begin counting rotations detected in the state transition bus 115, and to reset the counters when a new counting cycle begins. The enable count input functions from a positive-edge triggered clock. That is, each time a low-to-high edge transition is detected at an enable count input, the previous count cycle is reset and a new count cycle begins. The plurality of clock signals 523-529 which control the enable count input of each counter, respectively, are generated by the symbol/phase timer 520. The symbol/phase timer 520 is a conventional timer operating from the sampling clock discussed above (CLK operating at 76.8 KHz). The symbol/phase timer 520 conventionally divides down the sampling clock into a plurality of clock signals 523-529 operating at the symbol rate of the four-level FSK signal. That is, for a symbol rate of 3200 sps (symbols per second), each of the plurality of clock signals 523-529 operates at a frequency of 3200 Hz. The plurality of clock signals 523-529 are then applied to a clock bus 521 (shown as a thick line signal) which distributes the clocks to the respective counters 502-508.

Additionally, each of the plurality of clock signals 523-529 is offset by a first predetermined time, which is preferably in a four-level FSK signal, a phase corresponding to one quarter of a symbol interval. Thus, for a four-level FSK signal operating at a symbol rate of 3200 sps, the first predetermined time is equal to 78.125 us (one quarter of a symbol interval, i.e., one quarter of 312.5 us). A timing illustration of the plurality of clocks 523-529 is shown in FIG. 16, which will be discussed shortly.

The memory 522 is a conventional memory utilized for recording the sequence of state transitions counted by the plurality of counters 502- 508. Each result recorded in the memory 522 is controlled by the symbol/phase timer 520. The timing for recording data in the memory 522 is also shown in FIG. 16. The order in which data is recorded in the memory 522 is not critical to the present invention. The only requirement is that a consistent order of recording is followed so that the baud rate detection circuit 524 can properly retrieve data for processing purposes.

The baud rate detection circuit 524 is implemented, for example, with a conventional algorithmic state machine comprising conventional digital components. It will be appreciated that, alternatively, the baud rate detection circuit 524 may be implemented with a conventional microprocessor operating from micro-coded software. The baud rate detection circuit 524, as mentioned earlier, detects the presence of a desired baud rate. The operation of the baud rate detection circuit 524 will be discussed in detail from the flow charts shown in FIGs. 17 and 18.

FIG. 16 is an illustration of a timing diagram 600 depicting the operation of the baud rate detector 111 according to the present invention. Diagram 600 is helpful in understanding the timing operation of the plurality of counters 502-508, the memory 522, and the baud rate detection circuit 524. Each of the plurality of counters 502-508 is made to count the sequence of state transitions presented by the state transition bus 115 for no more than a sampling interval 606. A sampling interval is preferably a predetermined time interval that provides adequate time for processing the multi-level FSK signal for determining whether a desired baud rate is present or whether the signal is noise only.

Selecting an appropriate predetermined time interval is, for example, determined from the random nature of the data transported in the multi-level FSK signal, and the accuracy desired from the baud rate detector 111. The longer the predetermined time interval is, the more accurate will be the results provided by the baud rate detector 111.

Each sampling interval 606 is further subdivided into a plurality of recording intervals 604. In the present example, a recording interval is preferably equal to a symbol interval of the multi-level FSK signal.

Furthermore, each of the plurality of sampling intervals 606 is offset by the first predetermined time 602 as previously discussed.

In brief, the four counters 523-529 count during a plurality of sampling intervals 606 each comprising a plurality of recording intervals 604, wherein each recording interval 604 has a duration equal to a symbol interval. Moreover, each of the plurality of sampling intervals 606 is offset by the first predetermined time 602 (or one quarter of a symbol interval). These characteristics should be evident from the positions of the plurality of clocks 523-529 with respect to each other and the plurality of sampling intervals shown for each of the plurality of counters 502-508. As noted above, each of the plurality of counters 502-508 is controlled by the plurality of clocks 523-529, respectively, which enable and reset the counters during the rising edges (shown as upward arrows) of the clocks. The number contained in each recording interval is representative of the net number of rotations counted by a counter, and thereafter recorded in the memory 522 under the control of the symbol/phase timer 520. Each number is either positive (for a net number of counter-clockwise rotations) or negative (for a net number of clockwise rotations). FIG. 16 further illustrates the ideal net number of rotations that would be counted by one of the counters if it were synchronized to the sequence of state transitions provided by the state transition bus 115 (see the portion of the timing designated as the state transition bus 115). With a basic understanding of the timing of the baud rate detector 111 provided by FIG. 16, FIGs. 17 and 18 may now be discussed.

FIGs. 17 and 18 are flow charts 700 depicting the operation of the baud rate detector 111 according to the present invention. The operation of the baud rate detector 111 is primarily controlled by the operational steps programmed into the baud rate detection circuit 524 for processing data recorded in the memory 522. It will be appreciated that the method used by the baud rate detection circuit 524 for extracting data from the memory 522 is conventional and well known by those of ordinary skill in the art. This method is not shown in FIGs. 17 and 18, and will not be discussed below.

The flow chart begins with step 702, where the baud rate detection circuit 524 selects a first sampling interval from the plurality of sampling intervals. In the example shown in FIG. 16, there are four sampling intervals representative of the plurality of sampling intervals, wherein each sampling interval corresponds to one of the plurality of counters 502- 508. Thus, a first sampling interval may correspond to anyone of the four sampling intervals in the present example. For illustration, the first sampling interval selected will correspond to the sampling interval of counter 502 (shown in FIG. 16).

In step 704, the baud rate detection circuit 524 selects first and second recording intervals from the plurality of recording intervals corresponding to the first sampling interval. The first and second recording intervals are preferably recording intervals that are adjacent in time to each other. Referring back to FIG. 16, it can be seen that each of the four sampling intervals corresponding to the plurality of counters 502-508 are identified by sequence numbers directly above the recording intervals. In this example there are five recording intervals, numbered 1-5, for each of the four sampling intervals. For the present example, the first and second recording intervals are preferably the first two recording intervals of counter 502. The values recorded during these intervals (+6 and -6, respectively) are set in bold and are emphasized by a large character size. Once the first and second recording intervals have been read from the memory 522, the baud rate detection circuit 524 proceeds to step 706 where it sums values recorded in the memory corresponding to the first and second recording intervals. In this example, the result of this summation is zero, i.e., (+6) + (-6) = 0. In step 708, the baud rate detection circuit 524 selects a second sampling interval from the plurality of sampling intervals, wherein the second sampling interval is offset by a third predetermined time from the first sampling interval. The third predetermined time is preferably offset by one-half a symbol interval from the first sampling interval. Since each sampling interval is offset by one- quarter of a symbol interval, the second sampling interval, in this example, is the sampling interval corresponding to counter 506 shown in FIG. 16.

Note the selection of a second sampling interval is primarily for selecting a reference sampling interval (can also be referred to as an out-of- phase sampling interval) to provide an indication of how much the first sampling interval is synchronized to the data generated by the multi-level FSK signal. Viewing the second sampling interval as a reference sampling interval is important when applying step 720 of the flow chart, which will be discussed shortly.

Proceeding to step 710, the baud rate detection circuit 524 selects a third recording interval from the plurality of recording intervals corresponding to the second sampling interval. The third recording interval is preferably a recording interval having the same sequence number as the first recording interval of the first sampling interval. Since the first recording interval has a sequence number of 1, the third recording interval is the recording interval having the same sequence number. This recording interval is shown in FIG. 16 as having a recorded value of zero (shown in bold and emphasized by a large character). In step 714, the baud rate detection circuit 524 multiplies the third recording interval stored in the memory 522 by a coefficient. The coefficient is preferably a factor of two. The multiplication result in this example, however, remains zero. In step 716, the baud rate detection circuit 524 subtracts the result of the multiplication operation in step 714 from the result of the summation operation in step 706. The baud rate detection circuit 524 then proceeds to step 718 where it repeats steps 702-716 for a different set of first and second sampling intervals selected from the plurality of sampling intervals until the operations above have been applied to each of the plurality of sampling intervals. In the first cycle described above, the first and second sampling intervals corresponded to the sampling intervals of counters 502 and 506, respectively. This selection of sampling intervals provided a result in step 716 of zero, i.e., (+6) + (-6) - (0 X 2) = 0. It will be appreciated that, preferably, the subtraction result, from step 716, is further processed as an absolute number. Hence, had this example provided a negative result (e.g., -3), the final result would have been positive instead (i.e., +3). On a subsequent cycle, the first and second sampling intervals are selected as the sampling intervals for counters 504 and 508, respectively. Applying steps 704-716 to the new set of sampling intervals provides a result of positive four in step 716, i.e., I (+2) + (-2) - (-2 X 2) I = +4. Thereafter, the first and second sampling intervals correspond to the sampling intervals for counters 506 and 502, respectively. This selection of sampling intervals provides a result in step 716 of positive 12, i.e., I (0) + (0) - (+6 X 2) I = +12. The cycle is completed in step 716 when the selection of the first and second sampling intervals corresponds to the sampling intervals for counters 508 and 504, respectively. This selection of sampling intervals provides a result in step 716 of positive four, i.e., I (-2) + (+2) - (+2 X 2) I = +4. Once steps 702-716 have been applied to the first and second sampling intervals just discussed, the baud rate detection circuit 524 proceeds to step 720. In step 720, the baud rate detection circuit 524 selects at least one sampling interval from the plurality of sampling intervals having a lowest result from the subtraction operation in step 716. Recalling the results above (0, +4, +12, +4), the first and second sampling intervals providing the lowest result in step 716 are the sampling intervals for counters 502 and 506. Since there are no other sampling intervals providing a similar result of zero, only the sampling intervals for counters 502 and 506 are considered. Since the second sampling interval is simply a reference sampling interval, as discussed above, the sampling interval for counter 502 is selected as the sampling interval for step 720. Had more than one sampling interval provided a result of zero in step 716, step 720 would result in the selection of more than one sampling interval. The baud rate detection circuit 524 now proceeds to step 722 where it records in the memory 522 an incidence for the at least one sampling interval having the lowest result. Upon initialization of the baud rate detector 111 (e.g., initial power-on cycle, or first interception of an incoming multi-level FSK signal), the memory 522 is cleared with all zero's. Hence, the recording of an incidence of the sampling interval for counter 502 results in a recording (or "hit") value of one. For future hits, this value in the memory 522 continues to be incremented by one. Further, since there are four sampling intervals each corresponding to one of the plurality of counters 502-508, four memory locations are reserved in the memory 522 for recording hits or incidences of sampling intervals having a lowest value in step 720.

Redirecting the readers attention to FIG. 18, the baud rate detection circuit 524 now proceeds to step 726 where it selects at least one synchronized sampling interval from the plurality of sampling intervals, wherein the at least one synchronized sampling interval is substantially synchronized to the multi-level FSK signal, and wherein the at least one synchronized sampling interval corresponds to the at least one sampling interval having a highest incidence of lowest results recorded. In the present example, only one cycle of the steps in FIG. 17 have been completed.

As a result, only the sampling interval for counter 502 has a recorded hit. The other sampling intervals corresponding to counters 504- 508, respectively, have no hits, i.e., a value of zero recorded for each counter in the memory 522. Hence, the sampling interval for counter 502 is selected as the synchronized sampling interval, because it is the sampling interval having the highest incidence of lowest results recorded. As previously mentioned, the value recorded for the sampling interval for counter 502 is one, i.e., the value assigned to the synchronized sampling interval. Had there been more than one sampling interval having a hit value of one, then a plurality of sampling intervals with such values would be selected as synchronized sampling intervals, respectively.

In step 728, the baud rate detection circuit 524 selects at least one comparison sampling interval from the plurality of sampling intervals, wherein each of the at least one comparison sampling interval is offset by a second predetermined time from a corresponding one of the at least one synchronized sampling interval. This step is similar to step 708 in FIG. 17 where a sampling interval is selected as a reference (or an out-of-phase . sampling interval). The second predetermined time is preferably the same as the first predetermined time, i.e., one-half a symbol interval. Hence, the comparison sampling interval selected is the one for counter 506, which has a sampling interval offset from the sampling interval of counter 502 by one-half a symbol interval (see FIG. 16). Had there been more than one synchronized sampling interval selected in step 726, then a corresponding equal number of comparison sampling intervals would be selected in step 728. For example, had the sampling intervals for counters 502 and 504 been selected as synchronized sampling intervals, then two corresponding comparison sampling intervals would have been selected. The comparison sampling interval selected for counter 502 would be the sampling interval corresponding to counter 506, as already mentioned above. The comparison sampling interval selected for counter 504 would be the sampling interval corresponding to counter 508, because the sampling intervals for counters 504 and 508 are offset by one-half a symbol interval (see FIG. 17).

Proceeding to step 730, the baud rate detection circuit 524 compares incidences recorded for the at least one synchronized sampling interval to a maximum threshold. The maximum threshold is selected according to the character of data transported by a multi-level FSK signal. For example, most communication protocols initially provide portable radio receivers predetermined data patterns generally referred to as synchronization patterns, or in one specific case a "comma pattern" (i.e., alternating one's and zero's) for synchronization purposes. When processing predetermined patterns such as a comma pattern, the maximum threshold is selected in a manner that is most likely to result in an accurate determination that a desired baud rate has been detected according to the procedures specified by the present invention. This determination is made by utilizing conventional simulation tools. It will be appreciated that for non-conforming data patterns, e.g., random data, a different maximum threshold is selected for detecting a desired baud rate. In step 732, the baud rate detection circuit 524 determines whether the at least one comparison sampling interval comprises a plurality of comparison sampling intervals, wherein each of the plurality of comparison sampling intervals is offset by the second predetermined time from a corresponding one of the plurality of sampling intervals. Since there are four sampling intervals in the present example, there would have to be four comparison sampling intervals for this condition to be satisfied. A selection of four comparison sampling intervals requires a corresponding set of four synchronized sampling intervals to be selected in step 726. Since only one synchronized sampling interval was selected, step 732 has not been satisfied, and the baud rate detection circuit 524 proceeds to step 736. Had four comparison sampling intervals been selected in step 728, the baud rate detection circuit 524 would proceed to step 734. In this step, the baud rate detection circuit 524 determines if incidences recorded for the plurality of comparison sampling intervals are greater than a minimum threshold.

Again the minimum threshold is selected based on expected data patterns in the multi-level FSK signal. The minimum threshold is utilized by the baud rate detection circuit 524 to allow a minimum number of false hits or incidences in the comparison (or out-of-phase) sampling intervals. When the plurality of comparison sampling intervals all indicate an incidence rate greater than the minimum threshold, it is assumed that the input signal (RFin) shown in FIG. 1 is a noise-only signal. Under such conditions, the baud rate detection circuit 524 rejects the signal intercepted by the receiver 100 in FIG. 1 by proceeding to step 746, which asserts the no signal present line as "true" in the demodulation bus 112 of FIG. 1.

Continuing with step 736, the baud rate detection circuit 524 determines whether incidences or hits recorded for the at least one synchronized sampling interval are greater than the maximum threshold. If they are, the baud rate detection circuit 524 proceeds to step 738. It will be appreciated that in an alternative embodiment, the baud rate detection circuit 524 could proceed directly to step 742, thereby accepting the multi- level signal as having the desired baud rate. Generally, steps 738 and 740 (which will be discussed shortly) may be disregarded when it is known that the expected data to be transported by the multi-level FSK signal is predetermined data such as a comma pattern as mentioned above. Under unpredictable data conditions, however, the preferred embodiment of the present invention includes steps 738 and 740.

If the synchronized sampling interval is less than the maximum threshold, the baud rate detection circuit 524 proceeds to step 744. In this step, the baud rate detection circuit 524 determines whether all the steps shown in FIG. 17 and steps 726-734 of FIG. 18 have been implemented on the plurality of recording intervals corresponding to each of the plurality of sampling intervals. That is, in the present example, the baud rate detection circuit 524 determines whether the algorithmic steps discussed thus far have been applied to all the recording intervals (shown in FIG. 16) for each of the plurality of counters 502-508. If they have, and step 736 has failed, then the baud rate detection circuit 524 proceeds to step 746 where the signal intercepted by the receiver 100 is rejected. If the plurality of recording intervals has not been exhausted, as in the present example where only the first two recording intervals of each sampling interval have been processed, then the baud rate detection circuit 524 proceeds to step 702 of FIG. 17, where the process of selecting a different set of first, second and third recording intervals for each of the plurality of sampling intervals is repeated.

Note when selecting a new set of first, second and third recording intervals, as specified by steps 704 and 710, the baud rate detection circuit 524 preferably selects recording intervals offset in time by one recording interval from the previous set of first, second and third recording intervals. Hence, where in the prior example the first and second recording intervals were selected as the recording intervals designated by the sequence numbers 1 and 2, the new set of first and second recording intervals are designated by the sequence number 2 and 3. The third recording interval must still be consistent with the sequence number of the first recording interval. Hence, the new third recording interval is designated by the sequence number 2. This shifting process of the recording intervals continues upon each application of the steps of FIG. 17 until all of the recording intervals have been processed by the steps of FIG. 17. Since the present discussion has only accounted for one cycle of the steps in FIG. 17, a single hit for the sampling interval of counter 502 will not be greater than the maximum threshold, unless, of course the maximum threshold was set to zero. Such a value would not be selected for the maximum threshold. Rather, the maximum threshold is selected such that the steps defined by FIG. 17 would have to occur over several cycles before the possibility arises that a selected synchronized sampling interval will have a higher number of recorded incidences than the maximum threshold. Selecting a maximum threshold in this manner reduces the possibility of an early false detection.

Assuming, however, that the incidences recorded for the synchronized sampling interval corresponding to counter 502 exceed the maximum threshold, the baud rate detection circuit 524 proceeds to step 738 where it compares incidences recorded for the at least one comparison sampling interval corresponding to counter 506 to the minimum threshold. If the incidences recorded for the at least one comparison interval are less than the minimum threshold, the baud rate detection circuit 524 proceeds from step 740 to step 742 where it accepts the multilevel FSK signal and asserts the baud rate detected signal (shown in FIG. 1) as "true," thereby indicating that the desired baud rate has been detected. If the incidences recorded for the at least one comparison interval are greater than the minimum threshold, the baud rate detection circuit 524 proceeds to step 744 where it determines whether the plurality of recording intervals for each of the plurality of sampling intervals have been processed by the steps of FIGs. 17 and 18. If they have, then the baud rate detection circuit 524 proceeds to step 746 where the signal intercepted by the receiver 100 is rejected. Otherwise, the baud rate detection circuit 524 continues to process the multi-level FSK signal intercepted by the receiver 100 according to the steps described above for FIGs. 17 and 18.

As should be apparent from the discussions of the steps included in FIGs. 17 and 18, the plurality of recording intervals for each of the plurality of sampling intervals do not all have to be processed to determine that a desired baud rate has been detected. Hence, in general, at least a minimum number of the plurality of recording intervals are processed before determining that a desired baud rate is present. Only in the worst case scenarios (e.g., data transported by the multi-level FSK signal has too many contiguous zero's or one's), will the plurality of recording intervals be virtually exhausted before a determination is made about the baud rate of the multi-level FSK signal.

In sum, the present invention provides several advantages to prior art baud rate detectors. First, the implementation of the present invention is primarily a digital circuit, thereby providing a high degree of manufacturability, low cost and low power consumption. Second, by utilizing the in-phase and quadrature signals for detecting frequency deviations, and the presence of a desired baud rate, the signal information contained in all levels of a multi-level FSK signal (i.e., inner and outer symbols) is utilized, thereby substantially improving the sensitivity and accuracy of the detectors described in the present invention. In contrast, prior art systems only utilize outer or inner symbol data, which results in a great loss of signal information. Consequently, the sensitivity performance of prior art systems is substantially less than that of the present invention.

Third, the present invention operates independent of adequate frequency lock to the multi-level FSK signal. Thus, the present invention can be extended to non-coherent super-heterodyne systems as well. In such a system, the sequence of state transitions generated by the state transition detector 113 is unidirectional (e.g., clockwise only rotation). Because the baud rate detector 111 is immune to frequency offsets, a unidirectional sequence does not affect the performance of the baud rate detector 111, or require re-design. Thus, the baud rate detector 111 is portable across multiple front-end systems. Lastly, the present invention can be adapted to detect predetermined patterns, e.g., comma patterns, by simply adjusting the minimum and maximum threshold discussed above, thereby providing a capability not present in analogous prior art systems.

FIG. 19 is an electrical block diagram of a selective call receiver (SCR) 800 utilizing the receiver 100 according to the present invention. The SCR 800 comprises the receiver 100 described above coupled to a conventional antenna 802, a power switch 808, a processor 810, and a user interface 821. The receiver 100 and antenna 802 are utilized for receiving multi-level FSK signals that include messages transmitted by a radio communication system. The receiver 100 generates digital data that is applied to the demodulation bus 112, which is then processed by the processor 810. Based on the digital data provided on the demodulation bus 112, the processor 810 is programmed to reject or accept the multilevel FSK signal as described in FIGs. 17 and 18 prior to processing messages included in the multi-level FSK signal.

The power switch 808 is a conventional switch, such as a MOS (metal oxide semiconductor) switch for controlling power to the receiver 100 under the direction of the processor 810, thereby providing a battery saving function. The processor 810 is used for controlling operation of the SCR 800. Generally, its primary function is to decode and process demodulated messages provided by the receiver 100, storing them and alerting a user of the received message. To perform this function, the processor 810 comprises a conventional microprocessor 816 coupled to a conventional memory 818 having nonvolatile and volatile memory portions, such as a ROM (read-only memory) and RAM (random-access memory). One of the uses of the memory 818 is for storing messages received from the radio communication system. Another use is for storing one or more selective call addresses utilized in identifying incoming personal or group messages to be intercepted by the SCR 800.

Once a message has been decoded and stored in the memory 818, the processor 810 activates the alerting device 822 (included in the user interface 821) which generates a tactile and/or audible alert signal to the user. The user interface 821, which further includes, for example, a conventional LCD display 824 and conventional user controls 820, is utilized by the user for processing the received messages. This interface provides options such as reading, deleting, and locking of messages. To communicate messages to the SCR's 800, the radio communication system preferably utilizes a protocol such as the FLEX protocol, developed by Motorola, Inc. (FLEX is a trademark of Motorola, Inc.) for transmitting synchronous messages. The FLEX protocol is a digital selective call signaling protocol that is presently used by various system operators in the United States and in several other countries. It will be appreciated that, alternatively, other signaling protocols that are suitable to the present invention can be used.

What is claimed is:

Claims

1. A method for processing a multi-level FSK (frequency shift keyed) signal received from a radio messaging system, comprising the steps of: converting the multi-level FSK signal into a sequence of state transitions; in a plurality of sampling intervals, wherein each of the plurality of sampling intervals is offset by a first predetermined time from other sampling intervals, and wherein each of the plurality of sampling intervals is further subdivided into a plurality of recording intervals, counting the sequence of state transitions that occur during at least a minimum number of the plurality of recording intervals; and accepting the multi-level FSK signal for further processing based on counts recorded during at least the minimum number of the plurality of recording intervals.

2. The method as recited in claim 1, further comprising the step of detecting a desired baud rate based on counts recorded during at least the minimum number of the plurality of recording intervals.

3. The method as recited in claim 1, further comprising the step of determining a frequency deviation of the multi-level FSK signal based on the sequence of state transitions counted.

4. The method as recited in claim 1, wherein the converting step comprises the steps of: mixing the multi-level FSK signal into an in-phase signal and a quadrature signal; and detecting a sequence of state transitions from the in-phase signal and the quadrature signal.

5. The method as recited in claim 2, wherein the step of detecting the desired baud rate comprises the steps of: selecting at least one synchronized sampling interval from the plurality of sampling intervals, wherein the at least one synchronized sampling interval is substantially synchronized to the multi-level FSK signal; selecting at least one comparison sampling interval from the plurality of sampling intervals, wherein each of the at least one comparison sampling interval is offset by a second predetermined time from a corresponding one of the at least one synchronized sampling interval; comparing results recorded during the at least one synchronized sampling interval and the at least one comparison sampling interval to predetermined criteria; accepting the multi-level FSK signal for further processing if the predetermined criteria is satisfied; and rejecting the multi-level FSK signal if the predetermined criteria is not satisfied.

6. The method as recited in claim 5, wherein the step of selecting the at least one synchronized sampling interval comprises the steps of: selecting a first sampling interval from the plurality of sampling intervals; selecting first and second recording intervals from the plurality of recording intervals corresponding to the first sampling interval; summing values of the sequence of state transitions counted in the first and second recording intervals; selecting a second sampling interval from the plurality of sampling intervals, wherein the second sampling interval is offset by a third predetermined time from the first sampling interval; selecting a third recording interval from the plurality of recording intervals corresponding to the second sampling interval; multiplying the third recording interval by a coefficient; subtracting the result of the multiplying step from the result of the summing step;, and selecting the at least one synchronized sampling interval based on the result provided by the subtracting step.

7. The method as recited in claim 6, wherein the step of selecting the at least one synchronized sampling interval comprises the steps of: repeating the foregoing steps preceding the step of selecting the at least one synchronized sampling interval for a different set of first and second sampling intervals selected from the plurality of sampling intervals until said steps have been applied to each of the plurality of sampling intervals; selecting at least one sampling interval from the plurality of sampling intervals having a lowest result from the subtracting step; recording an incidence for the at least one sampling interval having the lowest result; and repeating the foregoing steps for a different set of first, second and third recording intervals for each of the plurality of sampling intervals.

8. The method as recited in claim 7, wherein each of the plurality of recording intervals is equal to a symbol interval, and wherein the third predetermined time is equal to one-half a symbol interval.

9. The method as recited in claim 7, further comprising the step of accepting the multi-level FSK signal for further processing when the result provided by the subtracting step is substantially equal to zero.

10. The method as recited in claim 7, wherein the at least one synchronized sampling interval corresponds to the at least one sampling interval having a highest incidence of lowest results recorded, and wherein the step of accepting the multi-level FSK signal based on predetermined criteria comprises the steps of: comparing incidences recorded for the at least one synchronized sampling interval to a maximum threshold; and accepting the multi-level FSK signal for further processing if incidences recorded for the at least one synchronized sampling interval are greater than the maximum threshold.

11. The method as recited in claim 10, wherein the step of accepting the multi-level FSK signal based on incidences recorded further comprises the steps of: comparing incidences recorded for the at least one comparison sampling interval to a minimum threshold; and accepting the multi-level FSK signal for further processing if incidences recorded for the at least one comparison sampling interval are less than the minimum threshold.

12. The method as recited in claim 11, wherein the step of rejecting the multi-level FSK signal based on predetermined criteria comprises the step of rejecting the multi-level FSK signal if incidences recorded for the at least one synchronized sampling interval are less than the maximum threshold or if incidences recorded for the at least one comparison sampling interval are greater than the minimum threshold, and if the sequence of state transitions occurring during the plurality of recording intervals have been counted.

13. The method as recited in claim 11, when the at least one comparison sampling interval comprises a plurality of comparison sampling intervals, wherein each of the plurality of comparison sampling intervals is offset by the second predetermined time from a corresponding one of the plurality of sampling intervals, the multi-level FSK signal is rejected if incidences recorded for the plurality of comparison sampling intervals are greater than the minimum threshold.

14. A method for detecting a desired baud rate in a multi-level FSK (frequency shift keyed) signal, comprising the steps of: receiving the multi-level FSK signal from a radio messaging system; converting the multi-level FSK signal into an in-phase signal and a quadrature signal; detecting a sequence of state transitions from the in-phase signal and the quadrature signal; in a plurality of sampling intervals, wherein each of the plurality of sampling intervals is offset by a first predetermined time from other sampling intervals, and wherein each of the plurality of sampling intervals is further subdivided into a plurality of recording intervals, counting the sequence of state transitions that occur during at least a minimum number of the plurality of recording intervals; selecting a first sampling interval from the plurality of sampling intervals; selecting first and second recording intervals from the plurality of recording intervals corresponding to the first sampling interval; summing values of the sequence of state transitions counted in the first and second recording intervals; selecting a second sampling interval from the plurality of sampling intervals, wherein the second sampling interval is offset by a third predetermined time from the first sampling interval; selecting a third recording interval from the plurality of recording intervals corresponding to the second sampling interval; multiplying the third recording interval by a coefficient; subtracting the result of the multiplying step from the result of the summing step; repeating the foregoing steps for a different set of first and second sampling intervals selected from the plurality of sampling intervals until the steps above have been applied to each of the plurality of sampling intervals; selecting at least one sampling interval from the plurality of sampling intervals having a lowest result from the subtracting step; recording an incidence for the at least one sampling interval having the lowest result; repeating the foregoing steps for a different set of first, second and third recording intervals for each of the plurality of sampling intervals; selecting at least one synchronized sampling interval from the plurality of sampling intervals, wherein the at least one synchronized sampling interval is substantially synchronized to the multi-level FSK signal, and wherein the at least one synchronized sampling interval corresponds to the at least one sampling interval having a highest incidence of lowest results recorded; selecting at least one comparison sampling interval from the plurality of sampling intervals, wherein each of the at least one comparison sampling interval is offset by a second predetermined time from a corresponding one of the at least one synchronized sampling interval; comparing incidences recorded for the at least one synchronized sampling interval to a maximum threshold; accepting the multi-level FSK signal for further processing if incidences recorded for the at least one synchronized sampling interval are greater than the maximum threshold; and rejecting the multi-level FSK signal: if incidences recorded for the at least one synchronized sampling interval are less than the maximum threshold or if incidences recorded for the at least one comparison sampling interval are greater than a minimum threshold and if the sequence of state transitions occurring during the plurality of recording intervals have been counted, or if the at least one comparison sampling interval comprises a plurality of comparison sampling intervals, wherein each of the plurality of comparison sampling intervals is offset by the second predetermined time from a corresponding one of the plurality of sampling intervals, and if incidences recorded for the plurality of comparison sampling intervals are greater than the minimum threshold.

15. A receiver for processing a multi-level FSK (frequency shift keyed) signal received from a radio messaging system, the receiver comprising: a converter for converting the multi-level FSK signal into a sequence of state transitions; and a baud rate detector comprising: in a plurality of sampling intervals, wherein each of the plurality of sampling intervals is offset by a first predetermined time from other sampling intervals, and wherein each of the plurality of sampling intervals is further subdivided into a plurality of recording intervals, a plurality of counters for counting the sequence of state transitions that occur during at least a minimum number of the plurality of recording intervals; a memory for recording the sequence of state transitions counted by the plurality of counters during at least the minimum number of the plurality of recording intervals; and a baud rate detection circuit for detecting a desired baud rate based on counts recorded in the memory.

16. The receiver as recited in claim 15, further comprising a demodulator circuit for determining a frequency deviation of the multilevel FSK signal based on the sequence of state transitions counted.

17. The receiver as recited in claim 15, wherein the converter comprises: a mixer for converting the multi-level FSK signal into an in-phase signal and a quadrature signal; and a state transition detector for detecting a sequence of state transitions from the in-phase signal and the quadrature signal.

18. A selective call receiver comprising the receiver of claim 15.

19. The receiver as recited in claim 15, wherein the baud rate detection circuit is adapted to: select at least one synchronized sampling interval from the plurality of sampling intervals, wherein the at least one synchronized sampling interval is substantially synchronized to the multi-level FSK signal; select at least one comparison sampling interval from the plurality of sampling intervals, wherein each of the at least one comparison sampling interval is offset by a second predetermined time from a corresponding one of the at least one synchronized sampling interval; compare results recorded in the memory during the at least one synchronized sampling interval and the at least one comparison sampling interval to predetermined criteria; accept the multi-level FSK signal for further processing if the predetermined criteria is satisfied; and reject the multi-level FSK signal if the predetermined criteria is not satisfied.

20. The receiver as recited in claim 19, wherein the baud rate detection circuit is further adapted to: select a first sampling interval from the plurality of sampling intervals; select first and second recording intervals from the plurality of recording intervals corresponding to the first sampling interval; sum values of the sequence of state transitions counted in the first and second recording intervals; select a second sampling interval from the plurality of sampling intervals, wherein the second sampling interval is offset by a third predetermined time from the first sampling interval; select a third recording interval from the plurality of recording intervals corresponding to the second sampling interval; multiply the third recording interval by a coefficient; subtracting the result of the multiplication operation from the result of the summation operation; repeat the foregoing operations for a different set of first and second sampling intervals selected from the plurality of sampling intervals until the operations above have been applied to each of the plurality of sampling intervals; select at least one sampling interval from the plurality of sampling intervals having a lowest result from the subtraction operation; record an incidence for the at least one sampling interval having the lowest result; and repeat the foregoing operations for a different set of first, second and third recording intervals for each of the plurality of sampling intervals.

21. The receiver as recited in claim 20, wherein the at least one synchronized sampling interval corresponds to the at least one sampling interval having a highest incidence of lowest results recorded, and wherein the baud rate detection circuit is further adapted to: compare incidences recorded for the at least one synchronized sampling interval to a maximum threshold; and accept the multi-level FSK signal for further processing if incidences recorded for the at least one synchronized sampling interval are greater than the maximum threshold.

22. The receiver as recited in claim 21, wherein the baud rate detection circuit is further adapted to: compare incidences recorded for the at least one comparison sampling interval to a minimum threshold; and accept the multi-level FSK signal for further processing if incidences recorded for the at least one comparison sampling interval are less than the minimum threshold.

23. The receiver as recited in claim 22, wherein the baud rate detection circuit is further adapted to reject the multi-level FSK signal if incidences recorded for the at least one synchronized sampling interval are less than the maximum threshold or if incidences recorded for the at least one comparison sampling interval are greater than the minimum threshold, and if the sequence of state transitions occurring during the plurality of recording intervals have been counted.

24. The receiver as recited in claim 22, when the at least one comparison sampling interval comprises a plurality of comparison sampling intervals, wherein each of the plurality of comparison sampling intervals is offset by the second predetermined time from a corresponding one of the plurality of sampling intervals, the baud rate detection circuit is further adapted to reject the multi-level FSK signal if incidences recorded for the plurality of comparison sampling intervals are greater than the minimum threshold.

25. An apparatus for detecting a desired baud rate in a multi-level FSK (frequency shift keyed) signal received from a radio messaging system, the apparatus comprising: a mixer for converting the multi-level FSK signal into an in-phase signal and a quadrature signal; and a state transition detector for detecting a sequence of state transitions from the in-phase signal and the quadrature signal; and a baud rate detector comprising: in a plurality of sampling intervals, wherein each of the plurality of sampling intervals is offset by a first predetermined time from other sampling intervals, and wherein each of the plurality of sampling intervals is further subdivided into a plurality of recording intervals, a plurality of counters for counting the sequence of state transitions that occur during at least a minimum number of the plurality of recording intervals; a memory for recording the sequence of state transitions counted by the plurality of counters during at least the minimum number of the plurality of recording intervals; and a baud rate detection circuit for detecting the desired baud rate based on counts recorded in the memory, wherein the baud rate detection circuit is adapted to: select a first sampling interval from the plurality of sampling intervals; select first and second recording intervals from the plurality of recording intervals corresponding to the first sampling interval; sum values recorded in the memory corresponding to the first and second recording intervals; select a second sampling interval from the plurality of sampling intervals, wherein the second sampling interval is offset by a third predetermined time from the first sampling interval; select a third recording interval from the plurality of recording intervals corresponding to the second sampling interval; multiply the third recording interval stored in the memory by a coefficient; subtract the result of the multiplication operation from the result of the summation operation; repeat the foregoing operations for a different set of first and second sampling intervals selected from the plurality of sampling intervals until the operations above have been applied to each of the plurality of sampling intervals; select at least one sampling interval from the plurality of sampling intervals having a lowest result from the subtraction operation; record in the memory an incidence for the at least one sampling interval having the lowest result; repeat the foregoing operations for a different set of first, second and third recording intervals for each of the plurality of sampling intervals; select at least one synchronized sampling interval from the plurality of sampling intervals, wherein the at least one synchronized sampling interval is substantially synchronized to the multi-level FSK signal, and wherein the at least one synchronized sampling interval corresponds to the at least one sampling interval having a highest incidence of lowest results recorded; selecting at least one comparison sampling interval from the plurality of sampling intervals, wherein each of the at least one comparison sampling interval is offset by a second predetermined time from a corresponding one of the at least one synchronized sampling interval; compare incidences recorded for the at least one synchronized sampling interval to a maximum threshold; accept the multi-level FSK signal for further processing if incidences recorded for the at least one synchronized sampling interval are greater than the maximum threshold; and reject the multi-level FSK signal: if incidences recorded for the at least one synchronized sampling interval are less than the maximum threshold or if incidences recorded for the at least one comparison sampling interval are greater than a minimum threshold and if the sequence of state transitions occurring during the plurality of recording intervals have been counted, or if the at least one comparison sampling interval comprises a plurality of comparison sampling intervals, wherein each of the plurality of comparison sampling intervals is offset by the second predetermined time from a corresponding one of the plurality of sampling intervals, and if incidences recorded for the plurality of comparison sampling intervals are greater than the minimum threshold.

26. A selective call receiver comprising the apparatus of claim 25.