JP3399013B2 - Digital phase modulation signal demodulator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a demodulation device for a digital phase modulation signal that realizes diversity after detection so that a stable reception level is set in a mobile communication station such as a digital mobile phone using PSK. 2. Description of the Related Art In a land mobile radio station such as a cellular phone, a transmission wave from a base station arrives after being reflected and refracted by surrounding buildings and the like. Therefore, as the mobile station moves, in both the base station and the mobile station, the received wave is deep and fast fluctuating due to multipath fading, and a stable reception level is not ensured. Becomes difficult. In order to overcome such a phenomenon, for example, a diversity reception in which a plurality of antennas are installed at a receiving station, and signals received from each of the plurality of antennas are switched and selected is known. By adopting the diversity reception, the transmission power can be reduced and the frequency can be effectively used. [0004] In the case where such antenna diversity for selecting an antenna is performed, it is reported that diversity after detection is effective in consideration of the current state of digitization of mobile phones. In particular, it is necessary to realize the diversity after detection in a mobile phone using 1 / 4πDQPSK communication. [0005] The present invention has been made in view of the above points, and for example, 1 / 4πDQPSK
Provided is a digital phase modulation signal demodulation device that realizes diversity after detection in a mobile phone, thereby effectively ensuring a stable reception level in a digital mobile phone that often moves to the shadow of a building or the like. What you want to do. A digital phase modulation signal demodulating apparatus according to the present invention delays the phase-modulated first and second digital input signals by one symbol, respectively, and delays the delayed digital input signals by one symbol. A phase difference value between the first and second output phase values and the phase value of each of the first and second input signals is obtained, and one of the first and second phase difference values is selected by the selection means. I do. Then, at least 1 / 2π of the absolute value of the selected one phase difference value is detected.
A demodulated symbol clock and a demodulated data clock are extracted on the assumption that symbol information exists at an intermediate point of a detection signal equal to or more than π. The first and second phase difference value outputs are supplied to a diversity error detecting means. To be done. Here, the diversity error detecting means includes:
First and second sampling means for sampling a predetermined signal of the upper bit of each of the first and second phase difference values within one symbol before and after a demodulation point, and the first and second sampling means First and second fading error detecting means for judging the coincidence state of the sampling logical values from each other;
And the output of the second fading error detecting means controls the selecting means. In the output of the phase difference values of the first and second input signals, when the input signal level is high, the upper bits of the phase difference value, for example, the upper 2 bits are constant before and after the demodulation point. Although it is in a logic state, the logic of the upper 2 bits is not constant when the reception level is low. Therefore, if the sampling logic values from the first and second sampling means of the diversity error detection means are determined to be in a predetermined range, a stable reception level of the first and second input signals is set. The selection circuit is controlled based on the result of the determination, a stable reception level is set, and the selected reception signal is demodulated. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a demodulation device in a 1 / 4πDQPSK digital mobile phone.
An A-side phase θA and a B-side phase θB corresponding to the A-side and B-side reception signals from the two antenna devices are input. The phase values PA1 to PAn and PB1 to PBn of the A-side and B-side input phase modulation signals, respectively.
Are supplied to one-symbol delay units 111a and 111b constituting the phase difference detection unit 11, respectively.
1b outputs LPA1 to LPAn and LPB1
LPBn are compared with the input phase values PA1 to PAn and PB1 to PBn in the phase difference units 112a and 112b, respectively, and their phase difference value outputs DPA1 to DPAn and D
PB1 to DPBn are determined. The output phase difference values DPA1 to DPA corresponding to the A side and the B side from the phase difference detection unit 11 respectively.
n and DPB1 to DPBn are selectors (selection circuits)
12 and the selected phase difference values are DP1 -D
Output as Pn. The phase difference values DP1 to DPn selected by the selector 13 are converted into absolute values ABP1 to ABPn by the absolute value detection circuit 13, and the detected values are 1 / 2π or more.
And outputs a detection signal DT that detects 1 / 2π or more of the absolute value of the phase difference value. The detection signal DT equal to or greater than 1 / 2π is DPLL.
The detection signal DT is supplied to a demodulation 2
1 KHz symbol clock C21K and demodulation 42KH
z Extract clock C42K. This DPLL unit 15
An intermediate detection section 151 for detecting an intermediate point position of the detection signal DT at least 1 / 2π, and a DPL to which the intermediate point detection signal is supplied.
L152. The upper two bits DPn and DPn- of the phase difference values DP1 to DPn selected by the selector 12 are used.
1 is supplied to the decoding unit 16, and this decoding unit
16 includes a demodulation 21 KHz symbol clock and a demodulation 42
A KHz clock is supplied, and the phase difference values DPn and DPn-1 are decoded to decode the 42 Kbps demodulated data DA.
Get TA. The selector 12 is supplied with a detection signal from the diversity error detector 17 as a selection command signal. The diversity error detecting section 17 includes an error detecting circuit 171 and the A side and the B side from the error detecting circuit 171.
Error detection signals ERRA and A
Averaging units 172a and 172b each constituted by a counter to which the RRB is supplied are provided. Outputs from the averaging units 172a and 172b are compared by a comparing unit 173. The comparing unit 173 outputs a selection signal to the selector 12. SEL is supplied. The error detection circuit 171 is provided with an i-bit shift register 21a to which the second upper bits DPAn-1 and DPBn-1 of the A-side and B-side phase difference detection signals from the phase difference detector 11 are supplied, respectively. And outputs from the shift registers 21a and 21b are supplied to i-bit DFFs (delayed flip-flops) 22a and 22b. The outputs of the i-bit DFFs 22a and 22b are
23b, and i-bit DFFs 22a and 22b, respectively.
It is determined whether the logics of the outputs DA1 to DAi and DB1 to DBi are constant. Then, the determination result is supplied to averaging sections 172a and 172b. The demodulation device having such a configuration will be described according to a specific operation. In this description, the resolution n for expressing the phase θA and the phase θB is “5”.
(Phase θA is PA1 to PA5, phase θB is PB1 to PB
5), the resolution of the PLL is "4", and the sampling number i for fading error detection is "7". Here, for convenience of explanation of the demodulation operation, a description will be given as a fixed selection on the A side (the A side is selected by the selector 12). In the timing chart shown in FIG.
When 3 / 4π (01) is received, its input phase value PA
1 to PA5 are from "0" to "12", "0""3"
"6""9""12", then -1
When / 4π (10) is received, up to the phase difference “−4”,
It changes to “12” “11” “10” “9” “8”. The same applies to the following. When the phase difference between the input phase values PA1 to PA5 and the outputs LPA1 to LPA5 from the one-symbol delay unit 111a is compared by the phase difference unit 112a, the phase difference values DPA1 to DPA1 to PA5 are compared.
DPA5 is obtained, and "12 (=
12-0) "," -4 (= 8-12) "," 12 (= 2
0-8) The phase difference between “12”, “−4”, and 3 / 4π (01) and − ／ π (10) of the demodulated data so as to be “-4 (= 16−20)”. From this fact, a 21 KHz symbol clock is extracted at a timing at which the phase difference values “12” and “−4” can be extracted, and demodulation is performed based on the extracted symbol clock. The absolute values of the phase difference values DPA1 to DPA5 are obtained by the absolute value detection unit 13, and the absolute value of the phase difference is 1
1 / 2π or more, that is, “8” or more is 1 / 2π or more.
, The output DT is set to “1” in the range determined to be equal to or greater than 1 / “π”, and the phase difference value “12” having a decode timing in the middle of the section where the output is “DT = 1”
Will be present. Therefore, the intermediate point of the output DT of the detecting section 14 is detected by the intermediate detecting section 151 by 1 / 2π or more and multiplied by the DPLL to obtain the demodulated 21 KHz symbol clock C2.
Extract 1K and demodulated 42KHz clock C42K,
By decoding the phase difference value (here, "12" and "-4") at the midpoint of the DT, demodulation is enabled. Here, the decoding method is based on the phase differences DP1 to DP1.
DP5 (In this example, since A side is selected, DPA1 to DPA1
By decoding the upper two bits DP5 and DP4 (corresponding to PA5) based on the truth table of Table 1, 42
Kbps demodulated data can be extracted. [Table 1] That is, phase difference values DPA1 to DPA between phase values PA1 to PA5 and data LPA1 to LPA5 delayed by one symbol.
A5 is calculated by the phase difference section 112a, and the absolute value detection section 13 obtains the absolute values ABP1 to ABP5. The detection signal DT is obtained by detecting the absolute value of 1 / 2π or more in the detection unit 14 at 1 / 2π or more.
The LL unit 15 calculates an intermediate point of the detection signal DT,
Demodulation 21 KHz Symbol clock C21K and demodulation 4
The 2 KHz clock C42K is extracted, and demodulated data is extracted by the decoding unit 16 using the upper two bits DPA5 and DPA4 of the phase differences DPA1 to DPA5. A description will be given of the diversity error detecting unit 17 for performing diversity in the demodulating device that performs such a demodulating operation. Outputs DPA1 to DP from phase difference detector 11
A5 and DPA4 and DPB4, which are the second upper bits of DPB1 to DPB5, are converted to demodulation points (detection signal DT
When sampling i bits (7 bits in this case) with an arbitrary sampling width centered on the center point of), as shown in FIG.
It becomes constant at "0" or "1". However, the sampling width is set to “(i−1) <1 symbol”. In a state without fading, the value becomes constant at "0" or "1". However, when fading is present as shown in FIGS. Is “0” before and after the demodulation point
Or, “1” is not constant. Therefore, the second upper bits DPA4 and DPB4 of the phase difference value are sampled from the preceding and succeeding i bits at an arbitrary sampling width around the demodulation point, and the logic of this sampling value is all "0" or "1". ", It is determined that there is no fading error. If even one bit has a mismatch value, it is determined that there is a fading error. That is, in the i-bit shift registers 21a and 21b, the phase difference value DPA4 is set at an arbitrary timing.
And DPB4 are sampled, and when the phase difference values DPA4 and DPB4 are fetched by the 1-bit shift registers 21a and 21b for i bits centering on the demodulation point, the values of the i-bit shift registers 21a and 21b are set to i
Latched by bits DFF22a and 22b,
And 23b, if even one bit of the i-bit logic does not match, signals ERRA and ER indicating a fading error
RB is output, and if all of the i-bit logic is “0” or “1”, the signals ERRA and ER are output.
RB becomes “0”, and it is determined that there is no fading error. The time section 18 includes an i-bit DFF 23a and
At 223b, a timing signal TIM for latching i bits before and after the demodulation point is output. Averaging units 172a and 172b
In this example, "1" of ERRA and ERRB output from the non-coincidence parts 23a and 23b are counted, and the number of "1" is averaged over an arbitrary period. This averaged value ELVA
1 to ELVAj and ELVB1 to ELVBj
To compare. That is, it can be determined that the side having a smaller value compared by the comparing section 173 is less affected by fading. As shown in the timing chart of the diversity switching after detection shown in FIG. 6, the control flow shown in FIG. The selector 12 is controlled according to the following. In FIG. 7, in steps 301 and 302, the fading on the A side and the B side are detected, respectively, and in steps 303 and 304, the fading on the A side and the B side are averaged, respectively. In step 305, the average values of the fading obtained in steps 303 and 304 are compared. In step 306, the comparison result is determined. In step 307 or 308, the selector 12 selects the A or B side. To be done. FIG. 8 shows another embodiment of the diversity error detecting section 17, and FIG. 9 shows a timing chart for explaining the operation thereof. In the diversity after detection in this embodiment, A
Side and B side phase difference values DPA1 to DPAn and DP
The phase difference values DPAn-1 and DPBn-1 of the second highest bit of B1 to DPBn are input to the diversity error detector 17. That is, the input phase difference values DPAn-1 and DPBn-1 are input to the rising and falling detecting sections 31a and 31b constituting the error detecting circuit 171 respectively. The detection signals ELOA and ELOB from the detection units 31a and 31b are respectively OR circuits.
I-adic counters 33a and 33b via 32a and 32b
Is supplied as a signal for loading "-i-1". The output signals from the counters 33a and 33b are
F34a and 34b. This DFF34a and 34
The output from b is further supplied to DFFs 35a and 35b, and the outputs from DFFs 35a and 35b are averaged by averaging section 172.
a and 172b. In the time section 18, the sampling clock DICK and the signal DIL for loading the i-adic counters 33a and 33b immediately before starting the i-bit sampling of the phase difference values DPAn-1 and DPBn-1 for each symbol.
O, and the carry-out CO of the i-ary counters 33a and 33b immediately after sampling i bits for each symbol.
Is generated, and this clock is supplied to DFFs 34a and 34b. That is, i-bit counters 33a and 33
b is the input phase difference values DPAn-1 and D
"-I-1" is loaded when the input phase difference values DPAn-1 and DPBn-1 change just before i-bit sampling of PBn-1 and during i-bit sampling. In the rising and falling detecting sections 31a and 31b, the input phase difference values DPAn-1 and DPAn
Bn-1, specifically, changes in DPA4 and DPB4 are detected. DFFs 34a and 34b latch the carry-out CO of i-ary counters 33a and 33b immediately after sampling i bits, and invert the latched results. The output signal is output from XQ. In the DFFs 34a and 34b, the phase of the latch output signal of the carry-out CO of the i-ary counters 33a and 33b is adjusted. In this manner, the diversity error detector 17
, The input phase difference values DPAn-1 and DPBn-
1, More specifically, when DPA4 and DPB4 are sampled i-bits at an arbitrary sampling width centered on the demodulation point, the phase difference DP
If A4 and DPB4 do not change (constant at "1" or "0"), "1" is output to the carry-out CO of the i-ary counters 33a and 33b immediately after i-bit sampling, and the DFF 35a of the error detection circuit 171 And 35b
"0" is output from each of the outputs ERRA and ERRB as no fuzzing. Conversely, if the phase difference values DPA4 and DPB4 change during i-bit sampling due to fading, the i-ary counters 33a and 33b again set "-i-".
To load 1 ", i
The carry-out CO of the ternary counters 33a and 33b becomes "0", and the outputs ERRA and ERRB of the error detection circuit 171 are made "1" as there is fading. That is, the phase difference values DPAn-1 and DPBn-1 (here, DPA4 and DPB4) are i-bit sampled at an arbitrary width centered on the intermediate point of the detection signal DT at least 1 / 2π of the absolute value of the phase difference value. During this i-bit sampling, the phase difference values DPAn-1 and DPBn-1
Is constant at "1" or "0", thereby detecting a fading error. Then, based on the comparison result in the comparing section 173 based on the outputs from the averaging sections 172a and 172b based on the fading error detection signal, the A side or the B side is selected, and diversity after detection is performed. As described above, according to the digital phase modulation signal demodulating apparatus according to the present invention, 1 / 4πDQPSK
It is possible to realize diversity after detection in a mobile phone, and it is possible to effectively secure a stable reception level in a digital mobile phone that often moves to the shadow of a building or the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating a demodulation device in a digital mobile phone according to an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of this embodiment without fading. FIG. 3 is a first timing chart for explaining fading in the embodiment. FIG. 4 is also a second timing chart. FIG. 5 is also a third timing chart. FIG. 6 is a diagram showing a switching timing chart for explaining diversity after detection. FIG. 7 is a flowchart illustrating a diversity switching control state of the embodiment. FIG. 8 is a circuit diagram illustrating another embodiment of the present invention. FIG. 9 is a timing chart illustrating the operation of the embodiment. [Explanation of Codes] 11: Phase difference detection unit, 111a, 111b: 1 symbol delay unit, 11
2a, 112b: phase difference section, 12: selector, 13: absolute value detection section, 14: 1 / 2π or more detection section, 15: DPLL section, 16: decoding section, 17: diversity error detection section, 171: error detection circuit 172a, 172b... Averaging unit, 173... Comparison unit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00 H04B 7/00 H04L 1/00

Claims (1)

(57) Claims: First and second ones to which phase-modulated first and second digital input signals are supplied, respectively.
Symbol delay means; and first and second positions for obtaining a phase difference value between an output phase value from each of the first and second one-symbol delay means and a phase value of each of the first and second input signals. Phase difference detecting means, selecting means for selecting one of the first and second phase difference values from the first and second phase difference detecting means, respectively, and the one phase difference selected by the selecting means An absolute value detecting means for calculating an absolute value of the value; a 1 / 2π or more detecting means for detecting 1 / 2π or more of the absolute value output from the absolute value detecting means; DPLL means for generating a demodulated symbol clock and a demodulated data clock on the assumption that symbol information exists, and a diversity apparatus to which phase difference value outputs from the first and second phase difference detecting means are supplied. The diversity error detecting means comprises: first and second sampling means for sampling a predetermined signal of the upper bit of each of the first and second phase difference values within one symbol before and after a demodulation point. Sampling means, and first and second fading error detecting means for judging a coincidence state of the sampling logical values from the first and second sampling means, respectively, the first and second fading error detecting means The selection means is controlled by the output of
Wherein a phase difference value corresponding to one of the input signals is selected.