JP3594323B2 - Receiver for digital mobile communication - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a receiver for digital mobile communication used in a 1 / 4.pi.DQPSK digital mobile phone which performs diversity after detection.
[0002]
[Prior art]
Digital mobile phones that perform mobile communication are used under various environmental conditions, and are often used, for example, in the shadows of large buildings. Therefore, for example, the reception conditions such as fading are not constant, and there are many cases where the communication condition is extremely poor.
[0003]
In order to improve the communication state with respect to fading and the like, diversity after detection is considered together with antenna diversity.However, it is hoped that a more correct reception system will be selected and the reception sensitivity will be further improved. It is rare.
[0004]
[Problems to be solved by the invention]
The present invention has been made in view of the above points, and in particular, an abnormality on the side selected by diversity after detection is effectively detected, and the correct side is reliably selected and received. Another object of the present invention is to provide a receiving apparatus for digital mobile communication used in a 1 / 4.pi.DQPSK digital mobile phone or the like in which the receiving sensitivity is more stably improved.
[0005]
[Means for Solving the Problems]
The present invention is characterized in that first and second input signals received and detected by first and second reception systems are input, respectively, and a first phase difference value indicating a phase difference of the first input signal; A phase difference detector for detecting a second phase difference value indicating a phase difference of a second input signal, the first phase difference value and the second phase difference value being input, and A first and a second transition abnormality detecting means for respectively sampling a phase difference value of a plurality of times before and after the symbol timing and detecting a phase transition abnormality, and the first and the second transition abnormality detecting means, respectively. And a diversity error detecting means for comparing the detection signals from the two and detecting which one has no or less transition abnormality. Then, the decode data selection means selects the first or second phase difference value corresponding to the one having no or less transition abnormality detected by the diversity error detection means, and the selected one is selected by the decode data selection means. The demodulated signal is obtained by decoding the phase difference value.
[0006]
[Action]
In the receiving apparatus in the digital mobile communication configured as described above, for example, the phase difference change of each of the first and second phase difference value signals based on the signals received by the first and second antenna systems, A phase transition abnormality such as an amount is detected, and one of the signals received by the first and second antenna systems, which has no abnormality or less abnormality, is selected and output as decoded data. Will be done. Then, decoding is performed based on the selected data and demodulated data is output, and demodulated data based on a received signal from a system with the least abnormality is always obtained, and stable reception sensitivity is obtained. Become like
[0007]
【Example】
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a receiving apparatus for performing digital mobile communication such as a 1 / 4.pi.DQPSK digital mobile phone, which is received by first and second independently configured antennas (not shown). And the first and second input signals .theta.A and .theta.B obtained by detecting.
[0008]
The phase values PA1 to PAn and PB1 to PBn of the first and second input signals θA and θB are input to one-symbol delay units 111 and 112 constituting the phase difference detection unit 11, respectively. The master clock MCK is input to each of the one-symbol delay units 111 and 112, and the one-symbol delay units 111 and 112 delay the phase values PA1 to PAn and PB1 to PBn by one symbol, respectively. And outputs two signals LPA1 to LPAn and LPB1 to LPBn.
[0009]
The signals LPA1 to LPAn and LPB1 to LPBn are input to the phase difference units 113 and 114 together with the input phase values PA1 to PAn and PB1 to PBn, respectively, to determine the phase difference. The upper two bits DPAn, DPAn-1 and DPBn, DPBn-1 of the outputs from the phase difference units 113 and 114 of the phase difference detection unit 11 are input to the decode data selection unit 121 constituting the selection unit 12. At the same time, the data is input to the DPLL data selection unit 122.
[0010]
The output data DPAn, DPAn-1 and DPBn, DPBn-1 of the phase difference detector 11 are supplied to the diversity error detector 13. The diversity error detector 13 includes phase difference change detectors 131 and 132 to which data DPAn, DPAn-1 and DPBn, DPBn-1 from the phase difference detector 11 are respectively input. The signals EDPA and EDPB that have detected the abnormal phase transition error from the respective units 132 and 132 are input to the comparison unit 133. The comparator 133 selects one having no or less phase transition abnormality based on the output from the phase difference change detectors 131 and 132.
[0011]
Further, in addition to the outputs of the phase difference change detection units 131 and 132 , an external input signal SLRSSI for adding diversity of another system is input. The output signal SLDED from the comparison unit 133 is supplied to the decode data selection unit 121 as a selection signal, and the output signal SLPLD is supplied to the PLL data selection unit 122 as a selection signal.
[0012]
The switching signal SLPLD from the comparing unit 133 is input to the PLL data selecting unit 122 together with the data DPAn-1, DPAn, DPBn, and DPBn-1 from the phase difference detecting unit 11, and based on the switching signal, the data DPAn -1, DPAn and one of DPBn and DPBn-1 are selected, and the selected signals DPn and DPn-1 are supplied to the DPLL 14.
[0013]
The DPLL 14 outputs a 21 kHz symbol clock C21K and a 42 kHz demodulated data clock C42K. The signals C21K and C42K are supplied to the decoding unit 15 to which the outputs DEDn and DEDn-1 from the decoding data selection unit 121 are supplied.
[0014]
In this decoded data select section 121, one of the 2-bit signal DPAn-1, DPAn and DPBn-1, DPBn from the phase difference comparison section 11 is selected based on the switching signal SLPLD from comparing portion 133, The selected data DEDn and DED n-1 are supplied to the decoding unit 15. The decoding unit 15 outputs demodulated data 42 Kbps based on the supplied data.
[0015]
The operation of the receiving apparatus thus configured will be described with reference to the timing chart shown in FIG. The phase difference detector 11 samples the phase values of the A-side and B-side input signals θA and θB using a master clock MCK that is an integral multiple of the symbol rate, and the upper bits (2 bits) DPAn of the phase difference value , DPAn-1 and DPBn, DPBn-1 are input to the phase difference change detectors 131 and 132 of the diversity error detector 13.
[0016]
When an abnormality occurs in phase transition as seen on the side A at time T3 in FIG. 2 due to fading or the like, the phase difference transits to ± 1/4 and further to other than ± 3/4 (phase difference transition abnormality). Therefore, the upper bits (DPAn.DPAn-1, DPBn.DPBn-1) of the phase differences (DPA1 to DPAn, DPB1 to DPBn) before and after the phase switching do not become constant at “0” or “1”. Therefore, the phase difference change detecting sections 131 and 132 detect a case where they are not constant at "0" and "1" in an arbitrary range before and after the phase switching. That is, a phase transition abnormality is detected by detecting a case where the value is not constant at “0” and “1” in an arbitrary range before and after the phase switching.
[0017]
The comparator 133 detects no phase transition abnormality based on the signals EDPA and EDPB that detect the phase transition abnormality of the phase difference change detectors 131 and 132, respectively, and the external input signal SLRSSI when the diversity of another system is added. Alternatively, an output SLPLD for selecting the upper two bits on the side considered to have less phase transition abnormality is output.
[0018]
The PLL data selection unit 122 of the selection unit 12 selects one of the upper two bits of the input phase difference value based on the output SLPLD from the comparison unit 133, outputs the phase difference values DPn and DPn−1, and outputs it to the DPLL 14. input. The DPLL 14 detects a leading or lagging phase from the symbol timing extraction signals DPn and DPn-1 from the PLL data selecting unit 122. Then, the frequency division ratio of the master clock MCK is controlled to extract a 21 KHz symbol clock and a 42 Hz demodulated data clock.
[0019]
In the decode data select section 121 of the select section 12, based on the select signal SLDED from the comparison section 133, the decoded data obtained by selecting the upper 2 bits on the side where there is no or little phase transition from the phase difference detection section 11 is selected. DEDn and DEDn−1 are output and input to the decoding unit 15. In the decoding unit 15, the 42 Kbps demodulated data is selected based on the decoded data obtained by selecting the upper 2 bits of the output phase difference value from the decoded data selecting unit 121 and the 21 KHz symbol clock and 42 KHz demodulated data clock extracted by the DPLL 14. Create
[0020]
In this manner, the phase transition abnormality is detected based on the input signals on the A side and the B side, and decoding is performed based on the phase difference data on the side considered to have no or little phase transition abnormality. Therefore, the improvement of the reception sensitivity to fading is effectively realized. Further, by connecting a switching signal of another diversity to the external switching signal SLRSSI, the receiving sensitivity can be further improved.
[0021]
For example, the received signals from the A-side and B-side antennas are respectively detected by the A-side and B-side detectors, and the outputs of the A-side and B-side detectors are compared by a comparison circuit. Correspondingly, an external selection signal SLRSSI is obtained.
[0022]
FIG. 3 shows the second embodiment. FIG. 4 shows a table of the phase difference values, and FIG. 5 summarizes the lower 3 bits of the phase difference value (here, 3 bits because n = 5). Showing things.
[0023]
In this embodiment, the diversity error detector 13 is constituted by NG range detectors 134 and 135, and the outputs EDPA and EDPB from these NG range detectors 134 and 135 are supplied to the comparator 133. . The NG range comparison units 134 and 135 are supplied with the output phase difference values DPAn-2 to DPAn and DPBn-2 to DPBn from the phase difference units 113 and 114 of the phase difference detection unit 11, respectively. Other components are the same as those in FIG.
[0024]
Focusing on the lower n-2 bits of the phase difference value, if there is no phase transition due to fading or the like, the lower n-2 bits of the phase difference are DPBn-2 (DPAn-DPn) for both ± 1 / 4π and ± 3 / 4π. 2)-DPB1 (DPA1) = "10 ... 0"
(“100” in FIGS. 4 and 5).
[0025]
Due to fading or the like, the lower n-2 bits of the phase difference are in the vicinity of DPBn-2 (DPAn-2) to DPB1 (DPA1) = "00... 0"("000" in FIGS. 4 and 5). When the phase transitions, it is difficult for the decoding unit 14 to determine the phase.
[0026]
Therefore, an arbitrary range around DPBn-2 (DPAn-2) to DPB1 (DPA1) = "00... 0" is determined as an NG range, and when the phase shifts to this NG range, it is processed as a phase transition abnormality. Thus, the lower two bits DPAn-2 (DPBn-2) to DPA1 (DPB1) of the phase difference value on the other side are selected and decoded.
[0027]
FIG. 6 shows a third embodiment, and FIGS. 7 (A) and 7 (B) show constellation diagrams with and without facing, respectively, and FIGS. 8 (A) and 8 (B) 2 shows coordinate change tables in the case where there is no fading and in the case where there is, respectively.
[0028]
In this embodiment, the phase values PA1 to PAn and PB1 to PBn of the inputs θA and θB on the A side and the B side are input to the coordinate abnormality detection units 136 and 137 constituting the diversity error detection unit 13. The outputs EDPA and EDPB from the coordinate abnormality detection units 136 and 137 are input to the comparison unit 133.
[0029]
In the constellation diagram shown in FIG. 7A, the coordinates of 0 to 1 / 2π, 1 / 2π to π, π to -1 / 2π, and -1 / 2π to 0 are represented by [1] [2] [3] If [4] is set, the path of the phase transition from ± 1 / 4π to ± 3 / 4π is as shown in the coordinate change table shown in FIG. When there is fading, the coordinate change table shown in FIG. 8B other than FIG. 8A is used.
[0030]
The upper two bits of the phase change amount indicate the coordinates of the phase transition. From this, when the upper two bits of the phase change amount change other than those shown in FIG. In the coordinate abnormality detecting units 136 and 137. The case where the upper two bits of the phase change amount change other than that shown in FIG. 8A is determined by the comparing unit 133 as having a phase transition abnormality, and the comparison result from the comparing unit 33 is The upper 2 bits (DPBn, DPBn-1 or DPAn, DPAn-1) of the phase difference, which is the other decoded data without phase transition abnormality, are selected by the switching signal SLSED based on the switching signal SLSED. So that improvements can be realized.
[0031]
9 shows a fourth embodiment, and FIG. 10 shows a timing chart for explaining the operation thereof. FIGS. 11A and 11B show timing charts with and without fading, respectively. Is shown.
[0032]
In this embodiment, the diversity error detection unit 13 includes a phase change point / phase change amount detection unit 138 to which upper two bits DPAn and DPAn-1 of the phase difference value on the A side of the phase difference detection unit 11 are supplied, and a B side. And the phase change point / phase change amount detection section 139 to which the upper two bits DPBn and DPBn-1 of the phase difference value are supplied. The outputs EDPA and EDPB from the detection sections 138 and 139 are compared with the comparison section 133. To be supplied.
[0033]
At time T3 shown in FIG. 10, a case where a 3 / 4π phase transition should occur, but a phase transition abnormality occurs on both the A side and the B side, and a case where the degree of the phase transition abnormality is particularly large on the A side will be considered. Focusing on the upper bits of the phase difference (here, DPAn-1 and DPBn-1 of the second highest bit), the A side having a higher degree of phase transition abnormality has a phase switching point (the center of the sampling range). Is changing close to.
[0034]
From this, the point at which the phase changes from “0” to “1” or from “1” to “0” at the phase change point / phase change amount detectors 137 and 139 of the diversity error detector 13 switches the phase. The side farther from the point or the number of “0” or “1” within the arbitrarily set sampling range is counted, and the side whose count value changes farther from the point where the phase is switched has less abnormal phase transition. Thus, the phase difference value on the side where the phase transition abnormality is considered to be small is selected by the decode data selection unit 121. The decoding unit 15 decodes the phase difference value on the side where the phase transition abnormality selected by the selecting unit 121 is considered to be small, thereby improving the receiving sensitivity.
[0035]
FIG. 12 shows a fifth embodiment of the post-detection diversity, in which the phase transition abnormality detecting section 16 detects a diversity error. The phase transition abnormality detection section 16 includes phase abnormality detection sections 161 and 162 to which phase difference values PA1 to PAn and PB1 to PBn on the A side and the B side are supplied, respectively. And decoding and phase difference result detection units 163 and 164 to which the upper two bits DPAn-1, DPAn and DPBn-1, DPBn of the phase difference value of the B side value are supplied. The outputs DEA and DEB from the decode / phase difference result detectors 163 and 164 are supplied to a mismatch detector 165, the output DION from the mismatch detector 165 and the output EA from the phase abnormality detectors 161 and 162 respectively. And EB are supplied to a comparing section 166. The switching signal SLDED from the comparing section 166 is supplied to the decoded data selecting section 121, and the switching signal SLPLD is supplied to the PLL data decoding section 122.
[0036]
In this embodiment, the decoding (or the phase difference result) is detected on both the A side and the B side, and when the decoding (or the phase difference result) does not match on both the A side and the B side, the diversity switching due to the phase transition abnormality detection is performed. Operable. Therefore, even though the decoding result is the same, diversity switching due to careless detection of a phase transition does not occur, and the receiving sensitivity is not reduced.
[0037]
【The invention's effect】
As described above, according to the receiving apparatus in digital mobile communication according to the present invention, in particular, an abnormality on the side selected by diversity after detection is effectively detected, and the correct side is always reliably selected. A signal from the selected antenna is received, so that the reception sensitivity of, for example, a 1 / 4πDQPSK digital mobile phone is effectively improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating a receiving apparatus in digital mobile communication that performs diversity after detection according to an embodiment of the present invention.
FIG. 2 is a timing chart illustrating the embodiment.
FIG. 3 is a configuration diagram illustrating a second embodiment of the present invention.
FIG. 4 is a view for explaining a phase difference value in the embodiment.
FIG. 5 is a diagram showing lower 3 bits of a phase difference value.
FIG. 6 is a configuration diagram illustrating a third embodiment of the present invention.
FIGS. 7A and 7B are constellation diagrams for the case without fading and the case with fading in the above embodiment.
FIGS. 8A and 8B are diagrams for explaining coordinate change states in a case without fading and in a case with fading in the embodiment.
FIG. 9 is a configuration diagram illustrating a fourth embodiment of the present invention.
FIG. 10 is a timing chart illustrating the embodiment.
FIGS. 11A and 11B are diagrams for explaining respective operation timings in the above embodiment when there is no facing and when there is fading;
FIG. 12 is a configuration diagram illustrating a fifth embodiment of the present invention.
[Explanation of symbols]
11: phase difference detection section, 111, 112: 1 symbol delay section, 113, 114: phase difference section, 12: selection section, 121: decode data selection section, 122: PLL data selection section, 13: diversity error detection section, 131, 132: phase difference change detecting section, 133: comparing section, 134, 135: NG range detecting section, 136, 137: coordinate abnormality detecting section, 138, 139 ... phase change point / phase change amount detecting section, 14: DPLL , 15... A decoding section, 16... A phase transition abnormality detecting section, 161, 162... A phase abnormality detecting section, 163, 164... A decoding / phase difference result detecting section, 165.

Claims (1)

First and second input signals received and detected by the first and second receiving systems, respectively, are input, a first phase difference value indicating a phase difference between the first input signal, and the second input signal. Phase difference detection means for detecting a second phase difference value indicating a phase difference between signals;
The first phase difference value and the second phase difference value are input, respectively, and the first and second phase difference values are sampled a plurality of times before and after the symbol timing at which the phase difference is switched , and the phase transition is performed. First and second transition abnormality detecting means for respectively detecting abnormality;
A diversity error detection unit that compares detection signals from the first and second transition abnormality detection units and detects whether there is no or little transition abnormality,
Decode data selection means for selecting the first or second phase difference value corresponding to one having no or less transition abnormality detected by the diversity error detection means;
Digital signal receiving apparatus in a digital mobile communication; and a decoding means for obtaining a demodulated signal by decoding the retardation values selected in the decoded data selection means.

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