WO1998033276A1 - Field programmable processor - Google Patents
Field programmable processor Download PDFInfo
- Publication number
- WO1998033276A1 WO1998033276A1 PCT/GB1998/000248 GB9800248W WO9833276A1 WO 1998033276 A1 WO1998033276 A1 WO 1998033276A1 GB 9800248 W GB9800248 W GB 9800248W WO 9833276 A1 WO9833276 A1 WO 9833276A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- switches
- busses
- memory cells
- group
- alu
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
Definitions
- the invention relates to such a device comprising: a plurality of processin devices; a connection matrix interconnecting the processing devices and including a plurality of switches; a plurality of memory cells for storing data for controlling the switches to define the configuration of the interconnections of the connection matrix.
- Figure 3 shows one level of interconnections between the locations of the arithmetic logic units, which are illustrated by squares with rounded corners.
- a group of four 4-bit busses v8, v4w, v4e, vl6 extend vertically across each column of ALU locations 12.
- the leftmost bus v8 in each group is in segments, each having a length generally of eight tiles.
- the leftmost but one bus v4w in each group is in segments, each having a length generally of four tiles.
- the rightmost but one bus v4e in each group is in segments, again each having a length generally of four tiles, but offset by two tiles from the leftmost but one bus v4w.
- the rightmost bus vl6 in each group is in segments, each having a length generally of sixteen tiles.
- the lengths of the segments may be slightly greater than or shorter than specified above.
- the decoder 34a determines which of the four branches from it leads to the address and supplies an ENABLE signal 30b to a further decoder 34b in that branch, together with a 4-bit address 32b to the decoders 34b in all four branches.
- the decoder 34b receiving the ENABLE signal 30b determines which of the four branches from it leads to the required address and supplies an ENABLE signal 30c to a further decoder 34c in that branch, together with a 4-bit address 32c to the decoders 34c in all four branches.
- the decoder 34c receiving the ENABLE signal 30c then supplies the ENABLE signal 34d to the required address where it can be stored in a single bit memory cell.
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/341,565 US6262908B1 (en) | 1997-01-29 | 1998-01-28 | Field programmable processor devices |
DE69822796T DE69822796T2 (en) | 1997-01-29 | 1998-01-28 | USER PROGRAMMABLE PROCESSOR |
EP98901401A EP0956645B1 (en) | 1997-01-29 | 1998-01-28 | Field programmable processor |
JP53175598A JP3885119B2 (en) | 1997-01-29 | 1998-01-28 | Field programmable processor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97300562A EP0858167A1 (en) | 1997-01-29 | 1997-01-29 | Field programmable processor device |
EP97300562.2 | 1997-01-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998033276A1 true WO1998033276A1 (en) | 1998-07-30 |
Family
ID=8229198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/GB1998/000248 WO1998033276A1 (en) | 1997-01-29 | 1998-01-28 | Field programmable processor |
Country Status (5)
Country | Link |
---|---|
US (2) | US6262908B1 (en) |
EP (2) | EP0858167A1 (en) |
JP (1) | JP3885119B2 (en) |
DE (1) | DE69822796T2 (en) |
WO (1) | WO1998033276A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000077627A1 (en) | 1999-06-15 | 2000-12-21 | Hewlett-Packard Company | Memory and instructions in computer architecture containing processor and coprocessor |
US7383424B1 (en) | 2000-06-15 | 2008-06-03 | Hewlett-Packard Development Company, L.P. | Computer architecture containing processor and decoupled coprocessor |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7266725B2 (en) | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
DE19651075A1 (en) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like |
DE19654595A1 (en) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures |
EP1329816B1 (en) | 1996-12-27 | 2011-06-22 | Richter, Thomas | Method for automatic dynamic unloading of data flow processors (dfp) as well as modules with bidimensional or multidimensional programmable cell structures (fpgas, dpgas or the like) |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
DE19861088A1 (en) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Repairing integrated circuits by replacing subassemblies with substitutes |
AU5805300A (en) | 1999-06-10 | 2001-01-02 | Pact Informationstechnologie Gmbh | Sequence partitioning in cell structures |
EP1342158B1 (en) | 2000-06-13 | 2010-08-04 | Richter, Thomas | Pipeline configuration unit protocols and communication |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US7581076B2 (en) * | 2001-03-05 | 2009-08-25 | Pact Xpp Technologies Ag | Methods and devices for treating and/or processing data |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
US7844796B2 (en) | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
WO2005045692A2 (en) | 2003-08-28 | 2005-05-19 | Pact Xpp Technologies Ag | Data processing device and method |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
EP1402382B1 (en) | 2001-06-20 | 2010-08-18 | Richter, Thomas | Data processing method |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7434191B2 (en) | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
US8281108B2 (en) | 2002-01-19 | 2012-10-02 | Martin Vorbach | Reconfigurable general purpose processor having time restricted configurations |
ATE402446T1 (en) | 2002-02-18 | 2008-08-15 | Pact Xpp Technologies Ag | BUS SYSTEMS AND RECONFIGURATION PROCEDURES |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
US6844757B2 (en) | 2002-06-28 | 2005-01-18 | Lattice Semiconductor Corp. | Converting bits to vectors in a programmable logic device |
WO2004021176A2 (en) | 2002-08-07 | 2004-03-11 | Pact Xpp Technologies Ag | Method and device for processing data |
US7657861B2 (en) | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
AU2003289844A1 (en) | 2002-09-06 | 2004-05-13 | Pact Xpp Technologies Ag | Reconfigurable sequencer structure |
US6980390B2 (en) * | 2003-02-05 | 2005-12-27 | Quantum Corporation | Magnetic media with embedded optical servo tracks |
US7219325B1 (en) * | 2003-11-21 | 2007-05-15 | Xilinx, Inc. | Exploiting unused configuration memory cells |
US7853774B1 (en) * | 2005-03-25 | 2010-12-14 | Tilera Corporation | Managing buffer storage in a parallel processing environment |
JP2009524134A (en) | 2006-01-18 | 2009-06-25 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Hardware definition method |
WO2008028330A1 (en) * | 2006-08-31 | 2008-03-13 | Beijing Xizheng Microelectronics Co. Ltd. | A programmable interconnect network for logic array |
WO2008154775A1 (en) * | 2007-06-20 | 2008-12-24 | Agate Logic, Inc. | A programmable interconnect network for logic array |
JP5336398B2 (en) | 2010-02-01 | 2013-11-06 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit and semiconductor integrated circuit configuration changing method |
EP2575597B1 (en) | 2010-05-25 | 2022-05-04 | The General Hospital Corporation | Apparatus for providing optical imaging of structures and compositions |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US5426379A (en) * | 1994-07-29 | 1995-06-20 | Xilinx, Inc. | Field programmable gate array with built-in bitstream data expansion |
US5583450A (en) * | 1995-08-18 | 1996-12-10 | Xilinx, Inc. | Sequencer for a time multiplexed programmable logic device |
Family Cites Families (12)
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US5233539A (en) | 1989-08-15 | 1993-08-03 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure, input/output structure and configurable logic block |
US5204556A (en) | 1991-05-06 | 1993-04-20 | Lattice Semiconductor Corporation | Programmable interconnect structure for logic blocks |
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US5498975A (en) * | 1992-11-19 | 1996-03-12 | Altera Corporation | Implementation of redundancy on a programmable logic device |
JP3547446B2 (en) | 1994-02-15 | 2004-07-28 | ジリンクス,インコーポレーテッド | Tile type structure of field programmable gate array |
US5453706A (en) * | 1994-04-01 | 1995-09-26 | Xilinx, Inc. | Field programmable gate array providing contention free configuration and reconfiguration |
GB2289354B (en) | 1994-05-03 | 1997-08-27 | Advanced Risc Mach Ltd | Multiple instruction set mapping |
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US5659785A (en) | 1995-02-10 | 1997-08-19 | International Business Machines Corporation | Array processor communication architecture with broadcast processor instructions |
GB9611994D0 (en) | 1996-06-07 | 1996-08-07 | Systolix Ltd | A field programmable processor |
-
1997
- 1997-01-29 EP EP97300562A patent/EP0858167A1/en not_active Withdrawn
-
1998
- 1998-01-28 DE DE69822796T patent/DE69822796T2/en not_active Expired - Lifetime
- 1998-01-28 JP JP53175598A patent/JP3885119B2/en not_active Expired - Fee Related
- 1998-01-28 EP EP98901401A patent/EP0956645B1/en not_active Expired - Lifetime
- 1998-01-28 US US09/341,565 patent/US6262908B1/en not_active Expired - Fee Related
- 1998-01-28 WO PCT/GB1998/000248 patent/WO1998033276A1/en active IP Right Grant
-
2001
- 2001-06-25 US US09/891,847 patent/US20010038298A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US5426379A (en) * | 1994-07-29 | 1995-06-20 | Xilinx, Inc. | Field programmable gate array with built-in bitstream data expansion |
US5583450A (en) * | 1995-08-18 | 1996-12-10 | Xilinx, Inc. | Sequencer for a time multiplexed programmable logic device |
Non-Patent Citations (3)
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BORRIELLO G ET AL: "THE TRIPTYCH FPGA ARCHITECTURE", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 3, no. 4, 1 December 1995 (1995-12-01), pages 491 - 500, XP000542422 * |
BURSKY D: "GATE ARRAYS FACE ONSLAUGHT OF DENSE AND FLEXIBLE FPGAS", ELECTRONIC DESIGN, vol. 43, no. 13, 26 June 1995 (1995-06-26), pages 85/86, 88, 90, 94, 96, XP000531702 * |
D. BURSKY: "SRAM BLOCKS AND ANTIFUSE LOGIC COMBINE IN NEW FPGAS", ELECTRONIC DESIGN, vol. 43, no. 16, 7 August 1995 (1995-08-07), CLEVELAND, USA, pages 115, 116, 118, XP000531682 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000077627A1 (en) | 1999-06-15 | 2000-12-21 | Hewlett-Packard Company | Memory and instructions in computer architecture containing processor and coprocessor |
US7383424B1 (en) | 2000-06-15 | 2008-06-03 | Hewlett-Packard Development Company, L.P. | Computer architecture containing processor and decoupled coprocessor |
Also Published As
Publication number | Publication date |
---|---|
EP0956645B1 (en) | 2004-03-31 |
EP0858167A1 (en) | 1998-08-12 |
EP0956645A1 (en) | 1999-11-17 |
US20010038298A1 (en) | 2001-11-08 |
US6262908B1 (en) | 2001-07-17 |
JP3885119B2 (en) | 2007-02-21 |
DE69822796D1 (en) | 2004-05-06 |
DE69822796T2 (en) | 2005-03-10 |
JP2001509336A (en) | 2001-07-10 |
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