EP1342158B1 - Pipeline configuration unit protocols and communication - Google Patents

Pipeline configuration unit protocols and communication Download PDF

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Publication number
EP1342158B1
EP1342158B1 EP20010984500 EP01984500A EP1342158B1 EP 1342158 B1 EP1342158 B1 EP 1342158B1 EP 20010984500 EP20010984500 EP 20010984500 EP 01984500 A EP01984500 A EP 01984500A EP 1342158 B1 EP1342158 B1 EP 1342158B1
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Prior art keywords
pae
configuration
subconf
ct
configured
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French (fr)
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EP1342158A2 (en
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Armin NÜCKEL
Volker Baumgarte
Gerd Ehlers
Frank May
Martin Vorbach
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Krass Maren
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KRASS MAREN
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path

Description

  • The present invention is concerned with methods that enable efficient configuration and reconfiguration of one or more reconfigurable assemblies by one or more configuration units (CT) at high frequencies. It describes how to set up efficient and synchronized networking to control multiple CTs.
  • The term module or cell includes classic FPGA cells, bus systems, memory, peripherals as well as ALUs and processor arithmetic units. Reference is made in this context to the definitions of the same applicant / assignee. In particular, any type of configurable and reconfigurable elements is basically understood as an assembly. For a parallel computer system, an assembly can be understood as a complete node of any function (but in particular computing, memory and data transfer functions).
  • The method described is applicable, in particular, to integrated components having a plurality of one-dimensionally or multi-dimensionally arranged assemblies which are connected to one another directly or by a bus system.
  • The genus of building blocks includes systolic arrays, neural networks, multiprocessor systems, processors with multiple arithmetic units and logic cells, as well as well-known building blocks of the type FPGA, DPGA, XPUTER, etc ..
  • In the following description, building blocks of an architecture are used whose arithmetic units and bus systems are freely configurable. The architecture is in DE4416881 , as well as PACT02, PACT08, PACT10, PACT13 already published and is called in the following VPU. This architecture consists of arbitrary arithmetic, logical (also memory) or communicative (IO) cells (PAEs), which can be arranged to form a one- or multi-dimensional matrix (PA), wherein the matrix can have different arbitrarily configured cells, including the bus systems are understood as cells. Associated with the matrix as a whole or parts thereof is a configuration unit (CT) that affects the networking and function of the PA.
  • A special feature of VPUs is the automatic and deadlock-free reconfiguration at runtime. Necessary protocols and methods are known from PACT04,05,08,10,13, which are incorporated by reference in its entirety. The publication number for these internal file numbers can be found in the appendix.
  • From the WO 00/17771 A method for configuring configurable hardware blocks is known. The methods should be characterized in particular by the generation of the configuration data, using which the hardware blocks are configured. Due to the configuration data generation described, both the configuration data generation itself and the hardware block configuration using this configuration data should be simple, quick and efficient to carry out.
  • 1. Basic states of PAEs and bus protocol of the configuration
  • Each PAE is assigned states which influence the configurability. Whether these states are coded locally or managed by one or more switching mechanisms, in particular the CT itself is insignificant. A PAE knows at least two states:
    • "not configured" In this state, the PAE is inactive and does not process data and / or triggers. In particular, it does not accept any data and / or triggers and does not generate any data and / or triggers. Only configuration-related data and / or triggers can be recorded and / or processed. The PAE is completely neutral and can be configured. However, the possibility of initializing the registers for data and / or triggers to be processed, in particular by the CT in this state, should be mentioned here.
    • "configured" The function and networking of the PAE is configured. The PAE processes and generates data and / or triggers to be processed. Such states can also be multiple times largely independently contained in separate parts of a PAE.
  • If the separation between data and / or triggers for processing on the one hand and data and / or triggers for the configuration of one or more cells on the other hand follows from the context, it is not explicitly stated explicitly.
  • During the configuration, the CT, together with a valid configuration word (KW), sends a signal indicating the validity (RDY). This can be omitted if the validity is ensured in another way, for example at continuous transmission or by coding in KW. Furthermore, the address of the PAE to be configured is generally coded in a KW.
  • A PAE decides according to the criteria described below and in the referenced applications whether it is able to accept the KW and change its configuration or whether the data processing must not be interrupted or falsified by a new configuration. In any case, the information whether or not configurations are accepted is forwarded to the CT if the decision does not already take place there. The following protocol would be possible: If a PII accepts the configuration, it sends the acknowledge ACK (acknowledge) to the CT. If the configuration is rejected, a PAE indicates this by sending REJ (reject) to the CT.
  • Within the data processing elements (PAEs) it is decided by the latter whether they can be reconfigured since the data processing has ended or whether they are still processing data. In addition, no data is corrupted by unconfigured PAEs.
  • 2. Deadlock freedom and correctness of the data 2.1 FILMO principle
  • It is important to efficiently manage a variety of configurations, each consisting of one or more KW and possibly other control commands and can be configured overlapping on the PA. This is because that often there is a large distance between the CT and the cells to be configured, which is disadvantageous in the transmission of configurations. At the same time, the technology ensures that no data or states are corrupted by reconfiguration. For this purpose, the following rules are defined, which are called the FILMO principle:
  1. a) PAEs that currently process data are not reconfigured. A reconfiguration should take place only when the data processing is completely completed or it is ensured that no further data processing is required. (Explanation: Reconfiguring PAEs that are currently processing data or waiting for pending data results in incorrect calculation or loss of data.)
  2. b) The state of a PAE should not change from "configured" to "unconfigured" during a FILMO run. In addition to the procedure according to PACT10, a special additional procedure is described below that allows exceptions (explicit / implicit LOCK). This has the following implications: When a subconf is understood as a set of configuration words to be collectively configured into the cell array at the appropriate time or purpose, a situation may arise where two different subconfs (A, D) are the same Sharing resources, in particular a PAE X. SubConf A is temporally before SubConf D. Thus SubConf A must occupy the resources before SubConf D. If now PAE X is still "configured" at the configuration time of SubConf A, but before the configuration of SubConf D the state changes to "unconfigured", a deadlock situation can arise without special measures, namely if SubConf A can no longer configure the PAE X and SubConf D eg only PAE x occupied, but the remaining resources, which are already occupied by SubConf A, can no longer be configured. Neither SubConf A nor SubConf D can be executed. It would create a deadlock.
  3. c) A subconfset should either successfully configure or allocate all PAEs belonging to it or have received a rejection (REJ) before configuring the subsequent subconf. However, this only applies if the two configurations completely or partially share the same resources. If there is no resource conflict, both SubConf can be configured independently. Even if a configuration was rejected for a SubConf PAE (REJ), the configuration of the subsequent SubConf is carried out. Since the status of PAEs does not change during a FILMO run (LOCK, as described in section b)), it is ensured that no PAEs that would have required the previous configuration are configured in the subsequent configuration. Explanation: If a SubConf to be configured later would allocate the PAEs of a SubConf to be configured beforehand, a deadlock occurs because no SubConf can be completely configured.
  4. d) Within a SubConf it may be necessary to configure or start certain PAEs in a certain order. Explanation: A PAE, for example, may only be connected to a bus after the bus has been configured for the SubConf. An intrusion on a foreign bus would lead to the processing of incorrect data.
  5. e) For certain algorithms, the order of configuration of SubConf may need to correspond exactly to the order of the triggers arriving at the CT. For example, if the trigger that triggers the configuration of SubConf 1 precedes the trigger that triggers the configuration of SubConf 3, SubConf 1 must be fully configured before SubConf 3 can be configured. If the sequence of the triggers is reversed, this can, depending on the algorithm, lead to a faulty sequence of the subgraphs (SubConf, see PACT13).
  • Procedures that satisfy many or all of the above requirements are known from PACT05 and PACT10.
  • The management of the configurations, their timing and the arrangement and design of the associated components, in particular the configuration register, etc., has, however, been found to be fundamental to the technique described and, therefore, possible improvements of the known prior art are still to be discussed.
  • The object of the present invention is to provide new products for commercial use.
  • The solution to this problem is claimed in an independent form. Preferred embodiments can be found in the subclaims.
  • In order to ensure requirements e) as required, it is proposed to store incoming triggers which are related to the status of a SubConf or a cell and / or a reconfigurability by means of a simple FIFO, in particular the CT associated with the CT, in the correct order. Each FIFO entry contains the inputs received in one clock trigger, in particular all received in one clock trigger can be stored. If no triggers occur, no FIFO entry is generated. The CT processes the FIFO in the order of the incoming triggers. If an entry contains several triggers, the CT optionally either (i) prioritizes or (ii) unprioritises each trigger individually before the next FIFO entry is processed. Since a trigger is usually sent to the CT only once per configuration, it is usually sufficient to set the maximum depth of the FIFO to the set of all the trigger lines wired to the CT. Alternatively, a TimeStamp protocol according to PACT18 can be used.
  • From PACT10 two basic types of FILMO are known:
    • Separate FILMO: The FILMO is run as a separate memory and separated from the normal CT memory, which caches the SubConf. Only KWs that could not be configured in the PA are copied to the FILMO.
    • Integrated FILMO: The FILMO is integrated in the CT memory. KWs that could not be configured are managed by flags and pointers.
  • The methods according to the invention described below are applicable either to both types of FILMO or a particular species.
  • 2.2 Differential Reconfiguration
  • For many algorithms, it makes sense to change the configuration only minimally during operation due to certain events that are represented by triggers or time synchronization, without the configuration of the PAEs being completely deleted. In most cases this concerns the interconnection of the bus systems or certain constants. If, for example, only one constant is to be changed, it makes sense to be able to write a KW to the relevant PAE without the PAE being in the "unconfigured" state. This reduces the amount of Kofigurationsdaten to be transmitted and is therefore advantageous. This can be achieved with a configuration mode "differential reconfiguration". The KW contains coded or explicitly the information DIFFERENTIAL when writing the KW. DIFFERENTIAL indicates that the KW is to be sent to an already configured PAE. The acceptance of the differential configuration and the acknowledgment is exactly the opposite of the normal configuration: a configured PAE accepts the KW and sends an ACK. An unconfigured PAE denies the acceptance of the KW and sends REJ, as a prerequisite for DIFFERENTIAL is a configured PAE.
  • There are several ways to perform the differeent reconfiguration. Either the different reconfiguration is enforced without regard to the data processing process that actually takes place, for example, in a cell; then it is desirable to ensure an exact synchronization with the data processing, which can be done by appropriate design and layout of the program. To relieve the programmer of this task, however, the differential reconfigurability can also be made dependent on other events, such as the presence of a particular state in another or the partially reconfigurable cell. A particularly preferred variant is therefore to store the configuration data, in particular the differential configuration data in or at the cell, for example in a dedicated register and then, depending on a specific state, to derive the register contents or to read them into the cell. This can be done, for example, by switching a multiplexer.
  • Also, the wave reconfiguration methods described below can be used. It may also be useful to make a differential configuration dependent on the success (ACK / REJ) of a previously normal configuration. In other words, the differential configuration is performed only after the arrival of the ACK for the previous non-differential.
  • A particularly preferred variant of the synchronization of the differential kofiguration is generally applicable regardless of how many different differential configurations are actually needed. This is made possible by not pre-storing the differential configuration locally, but with a first cell generating a particular state, such as a data input end or the like, generating a signal that stops the cell to be differentially reconfigured. Such a signal may be a STOP signal. After or simultaneously with the stopping of data processing in the cell to be differentially reconfigured, a signal is sent to the CT requesting the differential reconfiguration of the suspended cell. In particular, this differential reconfiguring request signal can be generated and transmitted by that cell which also generates the STOP_signal. The CT will then send the data required for differential reconfiguration to the stalled cell, causing the differential reconfiguration. After differential reconfiguration will cancel the STOP_Mode; this can be caused in particular by the CT. It should be noted that in the method of differential reconfiguration also cache techniques can be used.
  • 3. Task of triggers
  • In VPU blocks, so-called triggers are used to transmit simple information as exemplified below. Triggers are transmitted by means of any particular configurable bus system (network). Source and destination of a trigger are programmable.
  • A large number of triggers can be transmitted simultaneously within a block. In particular embodiments, in addition to direct transmission from a source to a destination, it is also possible to transmit a source to multiple destinations or multiple sources to a destination.
  • Triggers are primarily, but not exclusively, transmitted
    • * Status information from calculators (ALUs) like
      • Carry
      • Division by Zero
      • zero
      • negative
      • Under- / Overflow
    • * Results of comparisons
    • * n-bit information (for small n)
    • * Interrupt requests that are generated internally or externally
    • * Blocking and release orders
    • * Requirements of configurations
  • Triggers are generated by arbitrary cells and are triggered by arbitrary events in each cell. For example, the status and / or flag register of prior art ALUs or processors may be used to generate triggers. Also, triggers may be generated from a CT and / or external device located outside the cell array or the device.
  • Triggers are received by arbitrary cells and evaluated in any way. In particular, triggers may be evaluated by a CT or external device located outside the cell array or device.
  • A significant area of use of triggers is the synchronization and control of conditional executions and / or schedulers in the array, e.g. can be realized by sequencers, and their exchange of information.
  • 3.1 Semantics of triggers
  • For example, triggers are used for the following actions within PAEs:
    • STEP: Execute an operation within a PAE when the trigger arrives.
    • GO: Performing operations within a PAE when the trigger arrives. The execution is stopped by STOP.
    • STOP: Stop the execution started with GO; see. also the above explanations regarding the STOP signal
    • LOCAL RESET: Stop execution and transition from allocated or configured state to not configured state.
    • WAVE: Stop execution of operations and load a so-called wave reconfiguration to be loaded by the CT.
  • In a WAVE reconfiguration, one or more PAEs should be reconfigured subsequently to traverse the end of a data packet. It is then preferred direct and unmitable after reconfiguration, which can also be done as a differential reconfiguration, the processing of another Datenpaektes done. For example, a first audio data packet with first filter coefficients is to be processed; After passing through the first audio data packet, a partial reconfiguration is to take place and then a different audio data packet is to be processed with a second filter coefficient set. For this purpose, the new reconfiguration data, for example the second filter coefficients, can be stored in or at the cell and the reconfiguration can be automatically initiated upon detection of the end of the first data packet without, for example, the further intervention of a CT or other external control unit must be required. The recognition of the end of the first data packet or of the time. where reconfiguration is to be performed can be done by generating a wave reconfiguration trigger. This can be generated, for example, in a cell recognizing one data end at a time; a reconfiguration then proceeds with the cell-to-cell trigger as soon as it has completed the processing of the first data packet, comparable to the passage of a LA OLA through a football stadium. For this, a single cell can generate the trigger and, for example, send it to a first cell to indicate that the end of a first packet is going through. This first cell to be reconfigured, addressed by the wave trigger generation cell, in particular, simultaneously with the results derived from the last data of the first packet, which are sent to one or more subsequently processing cells, also passes the wave trigger signal to these subsequently processing cells. The Wavetriggersignal can also be sent or forwarded in particular to those cells that are currently not involved in the processing of the first data packet and / or received from the last data derived results. Then, the first cell to be reconfigured addressed by the wave trigger signal generating cell is reconfigured and takes up the processing of the data of the second data packet; During this time, subsequent cells are still busy processing the first data packet. It should be noted that the wave trigger signal generating cell is not just one single cell but several cells to be reconfigured. This may result in an avalanche-like propagation of the wave configuration.
  • Once the wave reconfiguration is fully configured, data processing will continue. With WAVE you can select whether the data processing will continue immediately after complete configuration, or wait for the arrival of a STEP or GO.
  • SELECT: Selects an input bus for forwarding to the output. Example: Either bus A or B should be switched to an output. SELECT selects the position of the multiplexer and thus the selection of the bus.
  • Triggers are used, for example, for the following actions within CTs:
    • CONFIG: A configuration should be configured by the CT in the PA.
    • PRELOAD: A configuration is to be preloaded by the CT into their local memory. As a result, the configuration does not have to be loaded until the arrival of CONFIG. It creates the effect of a predictable caching.
    • CLEAR: A configuration is to be deleted from the memory of the CT.
  • Incoming triggers refer to a specific configuration. The corresponding method will be described below.
  • The semantics are not assigned to a trigger signal in the network. Rather, a trigger represents only one state. How this state is used by the respective receiving PAE is configured in the receiving PAE. In other words, the sending PAE merely sends its state, the receiving PAE generates the semantics that are valid for it. If several PAEs receive a trigger, a different semantics can be used in each PAE, i. another REACH done. For example, a first PAE can be stopped and a second PAE reconfigured. If several PAEs send a trigger, the triggering event in each PAE may be different.
  • It should be mentioned that even with bus systems, etc., a wave reconfiguration and / or a partial reconfiguration can take place. A partial RE configuration of a bus can be done, for example, with the RE-configuration only in sections.
  • 3.2 System status and program pointer
  • Depending on the implementation, a system is a block or a group of blocks coupled to each other. In order to manage an array of PAEs - which is designed to be cross-module in a system - it does not make sense to know the state or program pointer of each PAE. For a better understanding, a distinction is made between several cases:
    • PAEs as devices without processor properties. Such PAEs do not need their own program pointer. The state of a single PAE is usually meaningless, since only certain PAEs have a usable state (compare PACT01: There, the state represented by a PAE is not a program counter but a data counter). The state of a group of PAEs is determined by linking the states of each relevant PAE. In other words, the information within the network represents the trigger's state.
    • PAEs as processors. These PAEs have their own internal program pointer and status. Preferably, only the information of a PAE that is relevant for the other PAEs or another PAE is exchanged by triggers.
  • Interaction of the PAEs with each other gives a common status that can be evaluated, such as in CT, to determine how to reconfigure. If necessary, it can be considered how the possibly configurable network of the lines or buses used for trigger transmission is currently configured.
  • The array of PAEs (PA) thus has a global state. The essential information is passed to the CT by means of certain triggers, by means of which the program execution is carried out Reconfiguration controls. It is particularly noteworthy that there is no longer a program counter.
  • 4. (Re) configuration
  • VPU blocks are configured or reconfigured due to events. These events can be represented by triggers (CONFIG) that are transmitted to a CT. An incoming trigger references a specific configuration (SubConf) for specific PAEs. The referenced SubConf is sent to one or more PAEs.
  • The referencing is done by means of a prior art lookup system or any other address translation. For example, using the number of an incoming trigger, the address of the configuration to be executed (SubConf) could be calculated if the SubConf have a fixed length: Offset + (trigger number * SubConfLength).
  • VPU devices have three configuration modes:
    1. a) Global configuration, the entire VPU is reconfigured. The entire VPU must be in a configurable state, ie must be unconfigured.
    2. b) Locale configuration, part of the VPU is reconfigured. The local part of the VPU to be reconfigured must be in a configurable state, ie, unconfigured.
    3. c) Differential configuration, an existing configuration is modified. The PAEs that are to be reconfigured must be in a configured state, ie must be configured.
  • A configuration consists of a set of configuration words (KWs). Each configuration can be referenced per se, for example by a reference number (ID), which can be unique as needed.
  • In the following, a set of KWs identified by an ID shall be referred to as subconfiguration (SubConf). In a VPU, several different, as well as similar SubConf can be configured, which run simultaneously on different PAEs.
  • A PAE may have one or more configuration registers, with one configuration word (KW) each describing a configuration register. A KW is always assigned the address of the PAE to be configured. Similarly, a KW is usually associated with information indicating the type of configuration. This information can be technically realized by flags or a coding. Flags are described in detail below.
  • 4.1 ModulID
  • For most operations it is sufficient that the CT knows the assignment of a configuration word and the relevant PAE to a SubConf. However, for more complex operations in the processing array, it makes sense to store the ID of the subconf assigned to it in each PAE.
  • An ID stored within the PA is referred to below as ModulID for distinguishing the ID within the CTs.
  • There are several reasons for the introduction of the ModulID, some are to be described:
    • A PAE may only be connected to a bus that also belongs to the corresponding SubConf. If a PAE is switched to a wrong (foreign) bus, this can lead to the processing of incorrect data. Basically, this problem can be solved by configuring busses in time before PAEs, resulting in a rigid order of KW within a SubConf. By introducing ModulID, this can be circumvented by having a PAE compare its stored ModulID with its assigned bus, and then switch to a bus if its ModulID matches that of the PAE. As long as the two ModulIDs are different, the bus connection will not be established. Alternatively, a bussing administration can be realized, cf. PAct 07.
    • PAEs can be set to the "unconfigured" state by a LocalReset signal. Local reset get from a PAE in the array and not from a CT; therefore "local".
      For this, the signal must be connected between all PAEs of a SubConf. This procedure becomes problematic if a SubConf is to be deleted that has not yet been completely configured and therefore not all PAEs are connected to LocalReset. Using the ModulID, the CT can broadcast a command to all PAEs. The PAEs with the corresponding ModulID change their state to "unconfigured"
    • In some applications, a SubConf may only be started at a certain point in time, but can already be configured in advance. Using the ModulID, the CT can broadcast a command to all PAEs. The PAEs with the corresponding ModulID then start the data processing.
  • In principle, the module ID can also match the ID stored in the CT.
  • The ModulID is written to a configuration register in the respective PAE. Since IDs for ordinary have a substantial width of mostly more than 10 bits, providing such a large register in each PAE is inefficient.
  • It is therefore proposed to derive the ModulID of the respective SubConf from the ID that it has a narrow width and is unique. Since the amount of all modules within a PA is typically comparatively low, a ModulID is width of a few bits (eg 4-5 bits) is sufficient. ModulID and ID can be bijectively mapped to each other. In other words, the ModulID uniquely identifies a configured module within an array at a particular time. The ModulID is assigned before the configuration of a SubConf so that the SubConf can be uniquely identified in the PA at execution time. A SubConf can be configured several times at the same time in the PA (see Macros, described below). For unambiguous assignment, a unique module ID is assigned for each configured SubConf.
  • The translation of an ID to a ModulID can take place via lookup tables or lists. Since numerous imaging methods are known, only one possibility will be explained in more detail:
    • A list whose length is 2 ModulID contains the set of all IDs currently configured in the array, with one ID assigned to each list entry. The entry "0" indicates an unused ModulID. If a new ID is configured, it must be assigned to a free list entry whose address yields the corresponding ModulID. The ID is entered in the list at ModulID.
    • When deleting an ID, the corresponding list entry is reset to "0".
    4.2 PAE states
  • Each KW is provided with additional flags that check and control the state of a PAE:
    • CHECK: An unconfigured PAE is allocated and configured. If the state of the PAE is "unconfigured", the PAE is configured with the KW. The process is acknowledged with ACK.
  • If the PAE is in the "configured" or "allocated" state, the KW is not accepted. The rejection is acknowledged with REJ.
  • After CHECK has arrived, a PAE enters the "allocated" state. Each additional CHECK is rejected, but data processing is not started.
  • DIFFERENTIAL: The configuration registers of an already configured PAE are modified. If the state of the PAE is "configured" or "allocated", the PAE is modified with the KW. The process is acknowledged with ACK.
  • If the PAE is in the "unconfigured" state, the KW is not accepted, it is acknowledged by REJ (reject).
  • GO: The data processing is started. GO can be sent individually or together with CHECK or DIFFERENTIAL.
  • WAVE: A configuration is linked to the data processing. As soon as the trigger WAVE arrives, the configuration marked with the flag WAVE is loaded into the PAE. If WAVE is configured before the triggers arrive, the KW marked with the WAVE flag remain stored until the trigger arrives and become active only with the trigger. If the trigger WAVE before the KW with the flag WAVE arrives, the data processing is stopped until the arrival of KW.
  • At least CHECK or DIFFERENTIAL must be set for each transmitted KW. CHECK and DIFFERENTIAL are not allowed at the same time. CHECK and GO, respectively DIFFERENTIAL and GO are allowed and start the data processing.
  • In addition, a flag is implemented that is not assigned to a KW and is explicitly set by CT:
    • LOCK: A PAE can not switch arbitrarily to the "not configured" state. If so, for example, the cell could still be configured and involved in processing data while attempting to write a first configuration from the FILMO memory into the cell; then the cell stops its activity during the further FILMO run. In principle, ie without further measures, a stored second configuration following in the FILMO, which may actually only be executed after the first one, could then prove these cases. This can then lead to DEADLOCK situations. By temporarily restraining the change of configurability of this cell by the command LOCK, such a lock can be avoided while preventing the cell from becoming configurable at an unintentional time. This curl of the cell against reconfiguration may, in particular, either occur when the FILMO is run, namely regardless of whether it is a cell that is actually accessed for reconfiguration purposes.
    • Alternatively, the cell may be lured to reconfiguration by, for example, being forbidden to reconfigure a particular phase of the cell for the first unsuccessful access to the cell by a first configuration of the cell in the film, which prevents the second configuration from being configured only for those cells which is to be accessed with a previous configuration.
  • According to the FILMO principle, a change is only permissible during certain states in the FILMO. By LOCK as discussed, the FILMO state machine controls the transition to the "not configured" state.
  • Depending on the implementation, the PAE transmits its current state to a higher level control unit (e.g., the associated CT), or stores it locally.
  • Transition tables
  • The simplest realization of a state machine to comply with the FILMO protocol is possible without the use of WAVE and CHECK / DIFFERENTIAL. Only the GO flag is implemented, a configuration consists of KW, which are transmitted together with GO. The following states can be implemented:
    • not configured: The PAE behaves completely neutral, ie it accepts no data or trigger and does not send any data or trigger. A configuration is expected. Differential configurations, if implemented, are rejected.
    • configured: The PAE is configured and processes data and triggers. Other configurations are rejected, differential configurations, if implemented, are accepted.
    • wait for lock: The PAE received a request for reconfiguration (eg by local reset or setting a bit in a configuration register). The data processing is set, the PAE expects the LOCK to be canceled in order to be able to change the state to "not configured".
    current PAE state event next state not configured GO flag Configured Configured Local reset trigger wait for lock wait for lock LOCK flag not configured
  • A completed state machine according to the described method allows the configuration of a PAE that requires several KWs. This is e.g. then the case, if a configuration is to be transmitted, which refers to several constants and these constants after or with the actual Einkonfigurierung should also be written into the PAE. This requires another condition.
  • Allocated: The PAE was checked by CHECK and was ready for configuration. The PAE is processed in the allocated state no data yet. Further KW marked with DIFFERENTIAL will be accepted. KW marked with CHECK will be rejected.
  • The corresponding transition table is shown below, WAVE is not yet implemented: current PAE state event next state not configured CHECK-Flag allocated not configured GO flag Configured allocated GO flag Configured Configured Local reset trigger wait for lock wait for lock LOCK flag not configured
  • 4.2.1 Implementation of GO
  • GO will
    either immediately when configuring a PAE together with
    the KW set to start the data processing immediately, or sent to the respective PAEs after completion of the entire SubConf.
  • The GO flag can be implemented differently:
  • a) Register
  • Each PAE has a register that is set to start processing. The technical realization is relatively simple, but for each PAE is a configuration cycle required. GO is transmitted as a flag according to the previous description together with the KW.
  • In the event that the order in which PAEs of different PACs belonging to an EnhSubConf are configured is not insignificant, another method is proposed to ensure compliance with this time dependency. Since several PACs by definition also have multiple CTs, they communicate with each other to exchange information as to whether all PAEs that must be configured before each next PAC have already accepted their GO from the same configuration.
  • One way to resolve the temporal dependencies and prevent the sending of unallowed GOs is to reorder the KW to ensure correct order through the sequence of its configuration by the FILMO. The FILMO then remembers, possibly by a flag, for each configuration whether all the GOs of the current configuration have been accepted so far. If this is not the case, further GOs of this configuration will no longer be sent. The initial state of each new configuration is as if all GOs have been accepted so far.
  • In order to increase the probability that some PAEs are already no longer configured during configuration, one can reorder the KW of an at least partially sequential configuration so that KW of the PAEs concerned are configured later in time. As well if necessary, you can enable certain PAEs earlier by rearranging KW of the configuration in question so that the PAEs concerned are configured earlier in time. These methods are particularly applicable if the order of the KW is not already determined by temporal dependencies, which must be met even after the resorting, completely.
  • b) Wiring via cable
  • As with the use of the LocalReset signal, PAEs are grouped together to be started together. Within this group, all PAEs are connected to a line for distribution of GO. If a group is to be started, a first PAE GO is signaled, which is realized by sending a signal or setting a register (see a)) of this first PAE. From this PAE, GO is forwarded to all other PAEs. To start, a configuration cycle is required. Forwarding requires a latency to bridge larger distances.
  • c) broadcast
  • A modification of a) and b) offers a high performance (only one configuration cycle) with comparatively little effort.
  • All modules receive a ModulID, which is usually not equal to the SubConfID.
  • The size of the ModulID should be kept as small as possible, if possible it should have a width of a few bits (3-5) suffice. The use of ModulID is described in detail below.
  • Each PAE writes the corresponding module ID during configuration.
  • GO is then started by broadcasting by sending the ModulID to the array along with the GO command. The command is received by all PAEs, but only executed by the PAEs with the appropriate ModulID.
  • 4.2.2 Saving the PAE state
  • The state of a PAE must not change from "configured" to "unconfigured" within a configuration or a FILMO run. Example: Two different SubConf (A, D) share the same resources, in particular a PAE X. In FILMO, SubConf A is ahead of SubConf D in time. SubConf A must therefore allocate the resources before SubConf D. PAE X is "configured" at the configuration time of SubConf A, but changes state to "unconfigured" before configuring SubConf D. This creates a deadlock situation because SubConf A can no longer configure PAE X, but SubConf D can no longer configure the remaining resources that are already occupied by SubConf A. Neither SubConf A nor SubConf D can be executed.
  • As mentioned, LOCK ensures that the state of a PAE does not change without permission during a FILMO run. It is insignificant for the FILMO principle, how the condition assurance is carried out, nevertheless several possibilities are to be discussed:
  • LOCK basic principle
  • Before starting the first configuration and each time the FILMO is run, the status of the PAEs is saved or locked. After completion of each pass, the status is released again. Certain status changes are only allowed once per run.
  • Explicit LOCK
  • The lock signal is set only after the first REJ from the PA since the start of a FILMO pass. This is possible because all PAEs could previously be configured and thus already in the "unconfigured" state. Only one PAE generating a REJ could change its state from "configured" to "not configured" during the further FILMO run. Only then could a deadlock occur, namely if a first KW received a REJ and a later time is configured. Immediately setting LOCK to a REJ prevents the transition from "configured" to "not configured" immediately. The main advantage of this method is that during the first pass phase PAEs can still change their states, that is, in particular, may change to the state "unconfigured". If a PAE changes from "configured" to "not configured" during a run before a failed configuration attempt, it can be configured in the same configuration phase.
  • Implicit LOCK
  • An even more efficient extension of the explicit LOCK is the implicit handling of LOCK within a PAE. In general, only PAEs are affected by the condition assurance condition that rejected a configuration (REJ). Therefore, during a FILMO run, it is sufficient to save the status only within the PAEs that generated a REJ. All other PAEs remain unaffected. LOCK is no longer generated by a higher-level entity (CT). Rather, after a FILMO pass through a signal FREE, the status backup in the affected PAEs is canceled again. FREE can be broadcasted to all PAEs directly after a FILMO pass and can also be pipelined through the array.
  • Extended transition tables for implicit LOCK:
  • A Rejection (REJ) generated by a PAE is stored locally in each PAE (REJD = rejected). Only when returning to "not configured" will the information be deleted. current PAE state event next state not configured CHECK-Flag Allocated not configured GO flag Configured allocated GO flag Configured Configured Local Reset Trigger & Rejection (REJD) wait for free Configured Local reset trigger & no rejection (not REJD) not configured wait for free FREE-Flag not configured
  • The transition tables are exemplary. A real implementation depends on the respective configuration.
  • 4.2.3 Configuration of a PAE
  • In this section, the configuration process is to be shown again from the point of view of CT. Parts of a PAE also apply as PAEs if they independently manage the states that were previously decrypted.
  • If a PAE is reconfigured, the first KW must set the CHECK flag to check the status of the PAE. A configuration for a PAE is constructed so that either only one KW is configured CHECK DIFFERENTIAL GO KW X - * KW0
    or several KWs are configured, whereby the first CHECK is set and with all further DIFFERENTIAL. CHECK DIFFERENTIAL GO KW X - - KW0 - X - KW1 - X - CW2 - X * KWn (X) set, (-) not set, GO is optional (*).
  • If CHECK is rejected (REJ), no subsequent KW with DIFFERENTIAL flag is sent to the PAE. After accepted CHECK (ACK), all other CHECKs are rejected until they return to the status "not configured", the PAE is allocated for the accepted SubConf. Within this SubConf, the next KWs are configured exclusively with DIFFERENTIAL. This is permissible since CHECK knows that this SubConf has access rights to the PAE.
  • 4.2.4 Reset to the status "not configured"
  • A specially configured trigger (LocalReset) propagates a signal that triggers the local resetting of the "configured" state to "not configured" in the receiving PAEs, at the latest after a received LOCK or FREE. The reset can additionally be triggered by other sources, for example by a configuration register.
  • LocalReset can be forwarded from the source that generates the signal over all existing configurable bus connections, ie all trigger buses and all data buses, to each PAEs connected via the buses. Basically, for example, every LocalReset receiving PAE forwards the signal via all connected buses.
  • However, in order to prevent a forwarding of LocalReset beyond the limit of a local group, it is possible to configure independently for each cell whether and via which connected buses the LocalReset should be forwarded.
  • 4.2.4.1 Delete not fully configured SubConf
  • In some cases, the configuration of a SubConf may begin and it may be noted during configuration that the SubConf is either no longer needed or not fully needed. LocalReset may not change the state of all PAEs to "unconfigured" because the bus has not yet been fully established.
  • Two possibilities are proposed according to the invention for the solution. In both methods, the PAE that generated the LocalReset sends a trigger to the CT. The CT then informs the PAEs as follows:
  • 4.2.4.2 When using ModulID
  • If a possibility for storing the ModulID is provided within each PAE, by means of a simple broadcast in which the identification is sent, each PAE with this specific identification can be requested to go into the state "not configured".
  • 4.2.4.3 When using the GO signal
  • If a GO line is wired in exactly the same order as PAEs are configured, it is possible for the GO line Assign a reset line that sets all PAEs to the "not configured" state.
  • 4.2.4.4 Explicit Reset by Configuration Register
  • In each PII, a bit or code is defined within the configuration registers, and by setting this bit or code through the CT, the PII is reset to the "not configured" state.
  • 4.3 Keep the data in the PAEs
  • Particularly advantageous is in building blocks of the genus according to the invention, when data and states of a PAE can be kept over a reconfiguration. In other words, it is possible to obtain data stored within a PAE despite reconfiguration. By corresponding information in the KW is defined for each relevant register whether it is reset by the reconfiguration.
  • Example:
  • For example, if a bit within a KW is logical 0, the current register value of the associated data or status register is maintained, a logical 1 resets the value of the register. A corresponding KW could be structured as follows: input register output register state flags A B C H L equal / zero overflow
  • As a result, the data retention can be selected with every reconfiguration.
  • 4.4 Setting data in the PAEs
  • It is also possible to write data from the CT to the registers of the PAEs during reconfiguration. The relevant registers can be addressed by KWs. A special bit indicates whether the data is treated as a constant or as a data word.
    • A constant will persist until it is reset.
    • A data word is valid for exactly a certain number of allocations, eg exactly one set-off. After processing the data word, the data word written by the CT into the register no longer exists.
    5. Extensions
  • The bus protocol can be extended so that the KWs and ACK / REJ signals can also be pipelined via registers.
  • This is particularly advantageous and is considered by itself or in conjunction with other than patentable.
  • In each cycle a KW or several KWs should be able to be sent. The FILMO principle should be adhered to. The basic principle is to build up an assignment to a KW written in the PA such that the time-delayed acknowledgment is subsequently assigned to the KW. KW dependent on the acknowledgment are re-sorted in such a way that they are processed only after receipt of the acknowledgment.
  • The alternative methods described below meet the requirements, the methods having different advantages:
  • 5.1 Lookup Tables (STATELUT)
  • Each PAE sends its status to a lookup table (STATELUT) that is locally implemented in the CT. When sending a KW, the CT checks the state of the addressed PAE by means of a lookup in the STATELUT. The acknowledgment (ACK / REJ) is generated by the STATELUT.
  • In detail, the procedure works as follows:
  • In a CT, the state of each individual PAE is managed in a memory or register file. For each PAE there is an entry indicating in which mode ("configured", "unconfigured") the PAE is located. Based on the entry, the CT checks whether the PAE can be reconfigured. The condition is checked internally by the CT, ie without demand at the PAEs. Depending on the implementation, each PAE sends its status independently or as requested to the CT-internal STATELUT. If the LOCK is set or the FREE is missing, no status changes are sent from the PAEs to the STATELUT or taken over by the STATELUT.
  • A simple mechanism is used to monitor the condition of the PAEs, with the mechanisms already described State control and the known states are realized:
  • Set the state "configured"
  • When writing a KW provided with the CHECK flag, the addressed PAE is checked in the STATELUT.
    • If the PAE is in a reconfigurable state, the PAE is noted as "allocated" in the STATELUT.
    • As soon as the PAE is started (GO), the PAE is entered as "configured".
    Resetting the state "configured" to "unconfigured"
  • Several methods can be used depending on the application and implementation:
    1. a) Each PAE sends a status signal to the table when its state changes from "configured" to "unconfigured". This status signal can be sent pipelined.
    2. b) A status signal (LocalReset) is sent for a group of PAEs indicating that the status for the entire group has changed from "configured" to "unconfigured". A list is used to select all PAEs belonging to the group and to change the state for each PAE in the table. What is essential is that the status signal from the last PAE of a group removed by LocalReset be sent to the CT. Otherwise, there may be inconsistencies between the STATELUT and the actual state of the PAEs, as the STATELUT identifies a PAE as "unconfigured". but that is actually still in the "configured" state.
    3. c) Upon arrival of a LOCK signal, which is preferably pipelined, each PAE whose status has changed since the last LOCK arrival sends its status to the STATELUT. LOCK receives rather the semantics "TRANSFER STATUS". However, since PAEs transfer their status only after this request and the status change is otherwise LOCKed, the process remains the same except for the opposite semantics.
  • To check the state of a PAE during configuration, the STATELUT is queried when the address of the target PAE of a KW is sent, and accordingly an ACK or REJ is generated. A KW is sent to a PAE only if no REJ was generated or if the DIFFERENTIAL flag is set.
  • Through this procedure, the chronological order of KW is ensured. Only valid KWs are sent to the PAEs. The disadvantage is the effort of implementing the STATELUT as well as the return of the PAE states to the STATELUT and the required bus bandwidth and runtime.
  • 5.2 Rearrange the KW
  • Essential for the application of the following method is the use of the CHECK flag for each first KW sent to a PAE (KW1).
  • The SubConf is reordered as follows:
    1. 1. First, KW1 of a first PAE is described. In the time (DELAY) until receipt of the acknowledgment (ACK / REJ), exactly as many empty cycles (NOPs) follow as clocks pass.
    2. 2. Then the KW1 of a second PAE is described. During DELAY, the remaining KW of the first PAE can be described. Any remaining clocks will be filled with empty cycles. The configuration block from KW1 to DELAY is called Atom.
    3. 3. The same procedure is followed for every other PAE.
    4. 4. If more than one cycle in a PAE is described as being paced while DELAY is pending, the remainder is distributed to the following atoms. Alternatively, the DELAY can be actively lengthened, creating a larger one
  • Number of KW can be written in the same atom. When ACK arrives for a KW1, all other KWs are configured for the corresponding PAE. If the PAE acknowledges with REJ, no further, the PAE concerning KW is configured.
  • The procedure ensures compliance with the order of configuration.
  • The disadvantage is that not the optimal configuration speed can be achieved. Since the waiting time of an atom must be filled with empty cycles (NOPs) in order to maintain the order, the usable bandwidth decreases and the size of a SubConf increases through the NOPs.
  • Furthermore, a paradox causes an irresolvable restriction of the configuration speed:
  • In order to minimize the amount of configuration data and cycles, the number of configuration registers should be kept as small as possible. As DELAY becomes compulsorily larger at higher frequencies, this conflicts with the requirement to make good use of DELAY by filling up with KW.
  • The method therefore seems to be usefully usable only with serial transmission of the configuration data. By serializing the KW, the data stream is long enough to fill the waiting time.
  • 5.3 Evaluating the ACK / REJ acknowledgment with latency (CHECKACKREJ)
  • The CHECK signal is sent with the KW to the addressed PAE via one or more pipeline stages. The addressed PAE acknowledges (ACK / REJ) also pipelined to the CT.
  • In each cycle, a KW is sent, whose acknowledgment (ACK / REJ) arrives at n-bars later in the CT and is evaluated. During this time, however, n more KWs will be sent. This results in two problem areas:
    • Control of the FILMO
    • Adherence to the order of KWs
    5.3.1 Control of the FILMO
  • Within the FILMO it must be noted which KW was accepted by a PAE (ACK) and which were rejected (REJ). The rejected KWs will be resent in a later FILMO run. For this later run, it makes sense to go through only the HCs that were rejected for reasons of configuration efficiency.
  • The described requirements can be realized as follows: The FILMO is assigned a further memory (RELJMP), which has the same depth as the FILMO. A first counter (ADR_CNT) points to the address of the KW in the FILMO that is currently being written to the PAE array. A second counter (ACK / REJ_CNT) points to the position of the KW in the FILMO whose acknowledgment (ACK / REJ) is currently coming back from the array. A register (LASTREJ) stores the value of ACK / REJ_CNT pointing to the address of the last KW whose configuration was acknowledged with REJ. A subtractor calculates the difference between ACK / REJ_CNT and LASTREJ. When a REJ occurs, this difference is written to the memory location with the address LASTREJ in the memory RELJMP.
  • RELJMP thus contains the relative jump distance between a rejected KW and its successor.
    1. 1. Each accepted KW is assigned a RELJMP entry "0" (zero).
    2. 2. Each rejected KW is assigned a RELJMP entry ">0" (greater than zero). By adding the current address with the RELJMP entry, the address of the next rejected KW is calculated in the FILMO.
    3. 3. The last rejected KW is assigned a RELJMP entry "0" (zero), indicating the end.
  • The memory location of the first address of a SubConf is assigned a NOP in the FILMO. The assigned RELJMP contains the relative jump to the first KW to be processed.
    1. 1. The first time through the FILMO, the value is "1" (one).
    2. 2. On a subsequent pass, the value points to the first KW to be processed, ie ">0" (greater than zero).
    3. 3. If all KWs of the SubConf have been configured, the value is "0" (zero). How the state machine detects the complete execution of the configuration.
    5.3.2 Compliance with the order (BARRIER)
  • In the procedure described under 5.3 it is not possible to guarantee a certain configuration order. The method only ensures the FILMO requirements according to 2.1 a) -c).
  • In certain applications, compliance with the configuration order within a SubConf (2.1 e)) and compliance with the configuration order of the individual SubConf itself are relevant (2.1 d)).
  • Order compliance is achieved by partitioning SubConf into multiple blocks. Between each block, a token (BARRIER) is inserted, which is only skipped if none of the previous KW has been rejected (REJ).
  • If the configuration meets a BARRIER and REJ occurred previously, the BARRIER must not be skipped.
  • There are at least two types of BARRIERs:
    1. a) NonBlocking: The configuration is continued with the following SubConf.
    2. b) Blocking: The configuration is continued with further runs of the current SubConf. The BARRIER is skipped only if the current SubConf has been completely configured.
  • Considerations for optimizing the configuration speed:
    • Usually, it is not necessary to maintain the order of configuration of each KW. However, the order of activation of the individual PAEs (GO) must be maintained exactly. The speed of the configuration can be increased by rearranging the KWs such that all KWs in which the GO flag is not set, before the BARRIER be pulled. Likewise, all HCs with the CHECK flag set must be pulled in front of the BARRIER. If a PAE is configured with only one KW, the KW must be split into two words, with the CHECK flag in front of the BARRIER and the GO flag after the BARRIER.
  • At the BARRIER it is known whether all CHECKs have been acknowledged with ACK. Since a rejection (REJ) only occurs with the CHECK flag set, all KWs behind the BARRIER are always executed in the correct order. The KW behind the BARRIER are run exactly once only and the start of each PAEs runs properly.
  • 5.3.3 Garbage Collector
  • The method according to 5.3 offers two different implementations of a garbage collector (GC):
    1. a) A GC implemented as an algorithm or simple state machine. At the beginning, two pointers point to the starting address of the FILMO: A first pointer (ReadPointer) points to the current KW to be read by the GC, a second pointer (WritePointer) points to the position to which the KW is to be written. ReadPointer is incremented linearly. Each KW whose RelJmp is not equal to "0" (zero) is written to the address WritePointer. RelJmp is set to "1" and WritePointer is incremented.
    2. b) The GC is integrated into the FILMO by adding a WritePointer to the FILMO readout pointer.
  • The WritePointer points at the beginning of the FILMO run on the first entry. Any KW rejected with a REJ when configuring a PAE is written to the memory location pointed to by WritePointer. After that, WritePointer is incremented. An additional FIFO-like memory (eg also a shift register) is required, which stores the KW sent to a PAE in the correct order until the ACK / REJ belonging to the KW arrives at the FILMO again. When an ACK arrives, the HC is ignored. Upon arrival of REJ, the KW is written to the memory location pointed to by WritePointer (as described earlier). The memory of the FILMO is preferably designed as a multiport memory.
  • In this method, at the end of each FILMO run, a new memory structure results, in which the unconfigured KW are located linearly at the beginning of the memory. Additional GC runs are not necessary. Also, the implementation of RelJmp and the associated logic can be completely dispensed with.
  • 5.4 Prefetching the ACK / REJ acknowledgment with latency
  • Finally, a further development of 5.3 will be described. Disadvantage of this method is the comparatively high latency which corresponds to three times the length of the pipeline.
  • The addresses and / or flags of the respective PAEs to be configured are stored on a separate bus system before the actual configuration sent. The timing is designed in such a way that at the time of the intended actual writing of the configuration word into a PII, its ACK / REJ information is present. If acknowledged with ACK, the CONFIGURATION is performed; in the case of a rejection (REJ), the KW are not sent to the PAE (ACK / REJ-PREFETCH). The FILMO protocol, in particular the LOCK, ensures that there is no unauthorized state change of the PAEs between ACK / REJ-PREFETCH and the CONFIGURATION.
  • 5.4.1 Structure of the FILMO
  • The FILMO works as follows: The KWs are obtained in the correct order, either (i) from the memory of the CT or (ii) from the FILMO memory.
  • The PAE addresses of the read out KW are sent via a first bus system pipelined to the PAEs. The complete KW are written in a FIFO-like memory with a fixed delay time (which can also be configured as a shift register, for example).
  • The addressed PAE acknowledges depending on its status by sending ACK or REJ. The depth of the FIFO corresponds to the number of clocks that elapse between the sending of the PAE address to a PAE and the receipt of the acknowledgment of the PAE. The cycle from sending the address to a PAE until receipt of the PAE acknowledgment is called Prefetch.
  • Due to the specific delay in the FIFO-like memory, which is not identical here with the FILMO, the acknowledgment of a PAE arrives exactly at the time at the CT, to which the KW belonging to the PAE is also present at the output of the FIFO. When ACK arrives, the KW is sent to the PAE, an acknowledgment is no longer expected. The PAE condition has not changed in the meantime without permission, the assumption is guaranteed.
  • When REJ arrives, the KW is not sent to the PAE but written back to the FILMO memory. An additional pointer is available for this, which points to the first address when linear read-out of the FILMO memory begins. With each value written back, the pointer is incremented. This will automatically linearize the rejected KWs, which corresponds to an integrated garbage collector sweep. (see also 5.3). This implementation is particularly advantageous and is considered inherently protectable.
  • 5.4.2 Sending and acknowledging via a register pipeline
  • The method described herein serves to ensure a uniform clock delay between sent messages and received responses thereto when different numbers of registers are switched between a sender and several possible recipients of messages. An example of this is when receivers are located at different distances from the sender. The message sent may Receiving nearby recipients reach earlier than more distant.
  • In order to achieve the same duration for all replies, the reply is not sent back directly by the recipient, but continues to a receiver furthest from the sender. This path must have exactly the same number of registers that the answer arrives at the time at which a message sent simultaneously with the first message would arrive at this point. From here, the return is the same as if the response was generated in this receiver itself.
  • Whether the response is actually sent to a farthest receiver or into another chain of registers that has the same timing is irrelevant.
  • 6. Hierarchical CT protocol
  • As described in PACT10, VPU devices are scalable by constructing a tree of CTs, each of whose leaves has the lowest-level CTs (low-level CTs) of the PAs. A CT with its associated PA is called a PAC. In general, any data or commands can be exchanged between the CTs. For this purpose, any technically meaningful protocol can be used first.
  • However, if communication (inter-CT communication) causes SubConf to start on different low-level CTs within the CT tree (CTTREE), the requirements of the FILMO principle should be met to ensure deadlock freedom.
  • In general, there are two cases:
    1. 1. In a low-level CT, the start of a SubConf is requested, which runs only locally on the low-level CT and its associated PA. This case can be edited at any time within the CTTREE and requires no special synchronization with other LOW-LEVEL_CTs.
    2. 2. A low-level CT requests the start of a configuration that runs on multiple low-level CTs and their associated PAs. In this case, care must be taken that the call of the configuration on all CTs involved is atomic, ie inseparable. The easiest way is to make sure that no one else is started during the call and startup of a particular SubConf. Such a protocol is known from PACT10. However, an even more optimized protocol is desirable.
  • The protocol from PACT10 is inefficient as soon as a pipelined transmission at higher frequencies is necessary because the bus communication is subject to a high latency.
  • The following sections perform a procedure.
  • The main task of the inter-CT communication is to ensure that PAC-wide SubConf (Enhanced SubConfiguration = EnhSubConf) is started deadlock-free. EnhSubConf are SubConf that are not only run on a local PAC but distributed across multiple PACs. An EnhSubConf contains several SubConf, which are started via the involved low-level CTs. A PAC is understood as meaning a PAE group with at least one CT. To ensure deadlock freedom, the following condition is necessary:
  • In order for several EnhSubConf to be able to run deadlock-free on identical PACs, a suitable mechanism is used to prioritize their execution, for example within the CTTREE. If several different EnhSubConf are to be started from SubConf, which run on one and the same PACs, the respective PACs start the subconf in the time sequence according to the prioritization of the EnhSubConf.
  • Example: Two EnhSubConf are to be started, namely EnhSubConf-A on the PACs 1,3,4,6 and EnhSubConf-B on the PACs 3,4,5,6. It must be ensured that on the PACs 3,4,6 always EnhSubConf-A is configured exclusively either before or after EnhSubConf-B. If, for example, PAC 3 and 4 EnhSubConf-A are configured before EnhSubConf-B and PAC 6 is EnhSubConf-A after EnhSubConf-B Deadlock because EnhSubConf-A could not be started on PAC 6 and EnhSubConf-B could not on PAC 3 and 4. Such a case is referred to below as cross or crossed.
  • It is sufficient to prevent EnhSubConf from crossing. Should there be an algorithmic dependency between two EnhSubConf, which means that one algorithm must start one EnhSubConf after the other, this is normally resolved by one EnhSubConf starting the other.
  • Exemplary embodiment of the protocol according to the invention:
  • Inter-CT communication distinguishes between two types of data:
    1. a) a SubConf containing the configuration information,
    2. b) an IDChain containing a list of IDs to start; together with the specification on which PAC the SubConf referenced by the ID should be started. By a IDChain a EnhSubConf is translated to the individual to be executed SubConf: ID Enhsubconf → IDChain {(PAC1: ID SubConf1), (PAC 2: ID Subconf2), (PAC 3: ID SubConf3), ··· (PAC n: ID SubConfn )}
  • Inter-CT communication distinguishes between the following transmission modes:
    • REQUEST: The start of an EnhSubConf is requested by a low-level CT requesting its parent CT - or one parent CT in turn requesting its parent. This is repeated until either a CT is reached that has the IDChain stored, or the RootCT that the IDChain always has in memory is reached.
    • GRANT: A higher-level CT commissioned a lower-level CT with the start of a SubConf. Either it is a single SubConf or several SubConf according to the IDChain.
    • GET: A CT requests a subconf to its higher-level CT by sending the corresponding ID. If the parent CT has cached the SubConf, it will send it to the lower CT, otherwise it will request the subconf at its parent and send it to the deeper one upon receipt. At the latest the RootCT saved the SubConf.
    • DOWNLOAD: Loading a SubConf to a Lowered CT.
  • REQUEST runs the CTTREE until either the RootCT, that is, the root (the highest CT) in the CTTREE, is reached, or a CT in the CTTREE has saved the IDChain. The IDChain can only be stored by a CT that has all CTs included in the list of IDChain, as leaves or branches. The RootCT always has access to the IDChain in its memory (CTR, see PACT10). Thereafter, GRANT is sent to all CTs listed in the IDChain. The sending of GRANT happens atomically, ie all branches of a CT receive GRANT either simultaneously or sequentially, but without interruption by another activity between one of the CTs concerned and any one another that affects the order of SubConf's startup of various EnhSubConf on the PACs.
  • Importantly, a low-level CT that arrives at GRANT instantly and uninterruptedly configures the appropriate SubConf into the PA, writes to the FILMO, or writes to a list that shows the configuration order, that is, exactly when the SubConf must be written to the FILMO or configured in the PA. The order is essential to avoid deadlock. If the SubConf is not already stored in the low-level CT, the low-level CT must request the SubConf via GET at its parent CT. In order to comply with the method according to the invention, between GET and the arrival of the SubKonf (DOWNLOAD), as far as the algorithm permits or requires, local subconf (ie SubConf which are not called by an EnhSubConf but only the local PA) are configured or entered into the FILMO be loaded. SubConf of another EnhSubConf, which are started by a later arriving GRANT, may only be started after the arrival of DOWNLOAD, as well as the configuration or loading into the FILMO.
  • Examples of the structure of SubConf are known from patent applications PACT05 and PACT10. An essential difference of the method according to the invention is the separate handling of calls from SubConf by IDChains. An IDChain is a special configuration of a SubConf with the following property:
  • For performance reasons, it makes sense to save individual SubConf within the CTTREE, so to speak, to cache. If necessary, a SubConf then does not have to be completely reloaded, but is sent directly to the subordinate CT by a CT that caches the corresponding SubConf. In the case of an IDChain, it is essential that all subordinate CTs are loaded from a central CT in accordance with the protocol according to the invention. The most efficient way to do this is to have the IDChain cached on the CTTREE deepest CT, which still has all the PACs named in the IDChain as leaves. Even lower-lying CTs are no longer allowed to cache because they are no longer centrally located above all IDChain PACs. Higher level CTs lose efficiency as a longer communication path is needed. If a request reaches a CT with full IDChain for the requested EnhSubConf, this triggers CT GRANTs to the deeper CTs involved, splitting the information from the IDChain (splitting) in that at least the part required in the respective branches is transmitted in each case. In order to prevent cross-splitting during this splitting, it must be ensured that the next CT stage also triggers all GRANTs of its part of the EnhSubConf, without being interrupted by GRANT's other EnhSubConf. One way of doing this is to atomically transfer the relevant parts of the IDChain. In order to control the caching of IDChains, it makes sense to mark a shared IDChain during the transmission, for example by a "SPLIT" flag.
  • An IDChain is split as soon as it is loaded onto a CT that is no longer centrally located within the hierarchy of the CTTREE over all the PACs referenced within the IDChain. In this case, the IDChain is no longer managed and cached by a single CT within the hierarchy. Several CTs each process the part of the IDChain that contains the PACs that are sheets of the respective CT. A REQUEST must always be forwarded to a CT that manages all the PACs concerned. That is, the hierarchically first and most efficient CT (as viewed from the PACs) that REQUEST can convert to GRANT is the first ascending order CT from the leaves that has a complete undivided IDChain. Management of the list of PAC to ID assignments need no further explanation. The list can either be processed by a program running within a CT, or be made up of a series of assembler instructions to drive the subordinate CTs.
  • A complete IDChain is structured as follows: ID EnhsubConf → IDChain {SPLIT, (PAC 1: ID Subconf1), (PAC 2: ID Subconf2), (PAC 3: ID SubConf3), ··· (PAC n: IDSubConfn)}
  • 6.1 Precache of SubConf
  • Within the CTTREE SubConf are preloaded under certain conditions, ie cached before they actually needed. This method significantly increases the performance within the CTTREE.
  • EXAMPLES
  • There are a variety of precache requirements available. The two most common are:
    1. a) Within a SubConf currently being processed on a low-level CT, a load request is programmed for another SubConf.
    2. b) During data processing within the PA, it is decided which SubConf is to be preloaded. The CT assigned to the PA is prompted to pre-load a SubConf by means of a trigger which is correspondingly translated within the CT to the ID of a SubConf. It is also possible that the ID of a SubConf is calculated in the PA or was previously configured there. Then the message to the associated CT contains the ID directly.
  • The SubConf to be loaded is only cached but not started. The start takes place only at the time when the SubConf would have been started without the previous caching. The difference is that at the time of the start request, the SubConf is already stored in the low-level CT or one of the middle CTs and therefore either configured immediately or loaded very fast on the low-level CT and then started. There is no need for time-consuming traversing of the entire CTTREE.
  • A compiler that generates the SubConf decides which SubConf should be cached next. Within the program flow graph you can see which SubConf could be executed next. These are each cached. The program execution decides at runtime which of the cached SubConf will actually be started.
  • According to the mechanism to precharge certain subconf, a mechanism is implemented which removes cached subconf to make room for other subconfs in the memory of the CTs. Like preloading, the compiler deletes certain SubConfs from the program execution graph.
  • In addition, the usual mechanisms for deleting SubConf are implemented in the CTs (e.g., the last configured one, the first configured, the least configured (see PACT10)) to appropriately manage the memory of the CTs. It is essential that not only explicitly preloaded SubConf can be deleted, but generally any SubConf in a CT memory. If the garbage collector has already removed the specific subconf, the explicit deletion will lose its validity and be ignored.
  • An explicit deletion can be effected by a command that can be started by any SubConf. This includes any CT within the tree, the own CT or even the explicit deletion of the same SubConf (ie the deletion of the own SubConf in the Command stands, whereby thereby the correct scheduling must be ensured).
  • Another possibility of explicit deletion is to generate a trigger within the PAs due to a particular state, which is forwarded to the CT and evaluated as a request for explicit deletion.
  • 6.2 Dependencies between the PAEs
  • In the event that the order in which PAEs of different PACs belonging to an EnhSubConf are configured is not insignificant, another method is proposed to ensure compliance with this time dependency. Since several PACs by definition also have multiple CTs, they communicate with each other to exchange information as to whether all PAEs that must be configured before each next PAC have already accepted their GO from the same configuration.
  • One way to resolve the temporal dependencies and prevent the sending of unauthorized GOs is to exchange the exclusive right to configure between the CTs and to rearrange the KW so as to ensure correct order through the sequence of its configuration and the transfer of the configuration right , Depending on how strong the dependencies are, it can also be sufficient if both CTs configure their assigned PA in parallel up to a synchronization point, then wait for each other and then until the next synchronization point or - if not available - continue to configure in parallel until the end of the EnhSubConf.
  • 7. SubConf macros
  • Caching SubConf is particularly efficient if as many SubConfs as possible can be cached. The efficient use of caching is particularly useful with regard to high-level language compilers, as compilers at assembler level - in VPU technology SubConf level - often generate recurring routines.
  • To reuse SubConf as often as possible, SubConf macros (SubConfM) should be introduced with the following property
    • no absolute PII addresses are specified. Rather, a SubConf is a pre-routed macro that uses only relative addresses;
    • Application-dependent constants are passed as parameters.
  • Only at the moment when a SubConf is loaded into the PA are the absolute addresses calculated. Parameters are replaced by their actual values. For this purpose, a modified copy of the original SubConf is created such that either (i) this copy is stored in the memory of the CT (integrated FILMO) or (ii) immediately written to the PA and only the rejected KWs (REJ) in the FILMO written (separate FILMO). Especially in the case (ii) For performance reasons, an embodiment of the address adder in hardware, which sits directly at the interface port of the CT to the PA / FILMO, is available. Likewise, hardware implementations of the parameter transformation are conceivable, for example by a lookup table that is loaded before the configuration.
  • 8. Restoring Cache Statistics
  • Out WO 99/44120 (PACT10) is an application-dependent cache statistics and control known. This method additionally offers a data-dependent optimization of the cache behavior, since the data-dependent program behavior is expressed directly in the cache optimization.
  • Disadvantage of the known method is that the cache behavior optimized only during runtime. When the application is restarted, the statistics are lost. Often even more critical is that when removing a SubConf from the cache and their statistics is lost and even within the same application processing in a new call is no longer available.
  • According to the invention, the cache statistics together with the ID in question when scheduling an application or removing a SubConf from the cache first by means of the known inter-CT communication to send to the next higher CT until the ROOT CT the respective Statistics received. SubConf This saves the statistics in a suitable memory, depending on the application in a volatile, nonvolatile or mass storage. The memory may be accessed via a host. The storage takes place in such a way that it is assigned to the respective SubConf such that the statistics can be loaded during a reload of the SubConf.
  • SubConfWhen the SubConf is restarted, it is also loaded to the low-level CT.
  • The compiler builds either a neutral empty statistics or generates according to a suitable procedure already a statistic which seems at first suitable. The statistics given by the compiler are then optimized according to the procedure described at runtime, stored and is available in a further call of the application in the optimized version.
  • SubConf
  • If a SubConf is used by several applications or within an application of different low-level CTs (or is called by different routines), it is not useful to keep a cache statistic, since it must be assumed that and expiration behavior will each cause different statistics.
  • Depending on the application, either a statistic is omitted or a SubConfM is used.
  • When using a SubConfM, the parameter transfer is extended in such a way that the cache statistics are transferred as parameters. If a SubConfM terminates, the cache statistics are written back to the subconf (formerly called SubConfM) (ORIGIN). The parameters are then stored together with the ORIGIN cache statistics during the ORIGIN termination in accordance with the method described, and are loaded accordingly in a subsequent call and passed on to the SubConfM as a parameter.
  • The management and saving of application-related cache statistics is basically also suitable for microprocessors, DSPs, FPGAs and similar building blocks.
  • 9. Structure of the Ronfigurationsbussystems
  • PACT07 describes a data bus system that is addressed and pipelined. This bus system is generally also suitable for the transmission of configuration data.
  • In order to transmit data and configurations over the same bus system, status signals are introduced which indicate the type of data transmitted.
  • The bus system is designed in such a way that the CT can optionally read back configuration and data registers from a PAE previously addressed by the CT.
  • Both global data in the sense of PACT07 and KWs are transmitted via the bus system. The CT acts as its own Bus node. A status signal indicates the transmission mode. The following structure with the signals S0 and S1 is possible, for example: S1 S0 importance 0 0 Write data 0 1 Read data 1 0 Write a KW and / or a PAE address 1 1 Returning a KW or any register from the addressed PAE
  • To the bus protocol (ACK) after PACT07, the signal REJ is added to signal the CT rejections according to the FILMO protocol.
  • 10. Combine individual registers
  • For the logical separation of configuration data independent configuration registers are used. The logical separation is particularly required for the differential configuration because logically separate configuration data is usually not known when performing a differential configuration. This creates a large amount of individual configuration registers, each containing relatively little information. In the following example, the 3-bit configuration values KW-A, B, C, D should be written or modified independently: 0000 0000 0000 0 KW-A 0000 0000 0000 0 KW-B 0000 0000 0000 0 KW-C 0000 0000 0000 0 KW-D
  • Such a register set is inefficient because the bandwidth of the CT bus is used only to a fraction.
  • The structure of configuration registers can be significantly optimized by assigning an enable value to each configuration value, which indicates whether the value should be overwritten during the current configuration transfer.
  • The configuration values KW-A, B, C, D of the above example are summarized in a configuration register. Each value is assigned an enable. For example, if EN-x is logical "0", KW-x is not changed during the current transfer, ENx is logical "1" KW-x is overwritten by the current transfer. En-A KW-A En-B KW-B IE-C KW-C End KW-D
  • 11. Wave Reconfiguration (WRC)
  • From PACT13 a reconfiguration method (Wave Reconfiguration = WRC) is known in which the reconfiguration is synchronized directly and temporally with the data stream ( FIG. 24 in PACT13).
  • Essential for the wave reconfiguration function is that unconfigured PAEs neither accept nor send data and triggers. This means that an unconfigured PAE completely neutral. This can be achieved in VPU technology by using handshake signals (RDY / ACK) for trigger and data buses (see PACT02). An unconfigured PAE generates it
    • no RDYs, which do not send data or triggers,
    • no ACKs, which will not receive data or triggers.
  • This functionality is not only helpful for wave reconfiguration, but is one of the possible foundations for runtime reconfigurability of VPU technology.
  • The following is an extension of the method: The reconfiguration is synchronized with the current data processing. Within the data processing in the PA is decidable,
    1. i. which next SubKonf becomes necessary during the reconfiguration;
    2. ii. at which time the SubConf must become active, that is with which data packet (ChgPkt) the SubKonf must be linked.
  • The decision as to which configuration is loaded is made by conditions and represented by triggers (WaveConfigurationPreload = WCP).
  • The linking of the data packets with the KWs of a SubConf is ensured by the data bus (RDY / ACK) and CT bus (CHECK, ACK / REJ) protocols. An additional Signal (WaveConfigurationTrigger = WCT) indicates which data packet (ChgPkt) should be reconfigured and, if so, which new configuration should be executed or loaded. WCT can be realized by simple additional lines or the triggering system of VPU technology. Multiple WCTs can be used simultaneously in the PA, with each signal controlling a different reconfiguration.
  • 11.1 Controlling Wave Reconfiguration
  • It is possible to distinguish between two application-dependent WRCs:
    • A1) Wave reconfiguration within a SubConf
    • A2) Wave reconfiguration of different SubConf
  • In terms of hardware, a distinction is preferably made between two basic implementation types:
    • I1) Implementation in CT and execution as required
    • I2) Implementation through additional configuration registers (WRCReg) in the PAEs. Possible embodiments of the WRCReg are described below. The WRC will either be
      1. a) preloaded by the CT during the first configuration of the relevant SubConf,
      2. b) or summoned by the CT during the execution of a SubConf depending on the incoming WCP.
  • During data processing, the valid WRCRs are selected by one or more WCTs.
  • In the following, the effect of wave reconfiguration on the FILMO principle will be discussed:
  • 11.1.1 Implementation of the WRC according to A1
  • Within one and the same SubConf (A1) the reconfiguration via WRC is possible at any time. First, the SubConf is configured normally, which ensures the FILMO principle. One requirement is that WRCs use only resources already allocated to the subconfigured resources during program execution.
  • Case I1)
  • The WRC is performed by differential configuration of the respective PAEs. WCP is directed to the CT. Depending on the WCP, a token is jumped within the configured SubConf: beginSubConf main:
  •  PAE 1, CHECK & GO
        PAE 2, CHECK & GO
        PAE n, CHECK & GO
        ...
        set TriggerPort1 // WCT 1
        set TriggerPort2 // WCT 2
     scheduler:
        on TriggerPort1 do main1 // Jump depending on WCT
        on TriggerPort2 do main2 // Jump depending on WCT 
     wait:
        wait for trigger
     main1:
        PAE 1, DIFFERENTIAL & GO
        PAE 2, DIFFERENTIAL & GO
        ...
        PAE n, DIFFERENTIAL & GO
        wait for trigger
     main2:
        PAE 1, DIFFERENTIAL & GO
        PAE 2, DIFFERENTIAL & GO
        ...
        PAE n, DIFFERENTIAL & GO
        wait for trigger
     endSubConf 
  • The interface (TrgIO) between CT and WCP is configured by "set TriggerPort". TrgIO behaves like a PAE to CT, according to the FILMO protocol. TrgIO corresponds exactly to the CHECK, DIFFERENTIAL, GO protocol and responds individually to each trigger or group together with ACK or REJ.
  • Depending on whether a particular trigger
    • already configured with REJ
      or
    • ready for configuration with ACK.
  • FIG. 8 from PACT10 is to expand this protocol accordingly.
  • When WCT arrives, the respective PAE starts the corresponding configuration.
  • Case I2)
  • Either
    the WRCR are already described during the configuration and the WCP is no longer necessary, since the entire SubConf has already been loaded into the respective PAE
    or
    Depending on certain WCP, CTs that are determined by CT are loaded into different WRCRs defined in the WRC. This is particularly necessary if, starting from a SubConf, a WRT occurs and branches into several different WRCs than physical WRCRegs.
  • The TriggerPorts within the PAEs are configured to select certain WRCRs by certain incoming WRTs:
    • beginSubConf
    • Main:
      • PAE1_TriggerPort1
      • PAE1_TriggerPort2
      • PAE1_WRCReg1
      • PAE1_WRCReg2
      • PAE1_BASE, CHECK & GO
      • PAE2_TriggerPort1
      • PAE2_TriggerPort2
      • PAE2_WRCReg1
      • PAE2_WRCReg2
      • PAE2_BASE, CHECK & GO
        ...
      • PAEn_TriggerPort1
      • PAEn_TriggerPort2
      • PAEn_WRcReg1
      • PAEn_WRCReg2
      • PAEn_BASE, CHECK & GO
    • endSubConf
    11.1.2 Carrying out the WRC in accordance with A2 Case I1)
  • Carrying out a WRC between different SubConf by CT corresponds in principle to A1 / 11. It is essential that the trigger ports and the internal CT sequence comply with the FILMO principle. KWs rejected by the PAEs (REJ) are written to the FILMO. The basics are already known from PACT10.
  • All WCP are executed by the CT, which ensures a deadlock free (re-) configuration.
  • Similarly, the time of reconfiguration indicated by WCT is passed to the CT and atomized by the CT, ie all PAEs affected by the reconfiguration receive the reconfiguration request by WCT either at the same time or at least without interruption by another reconfiguration request, which in turn ensures deadlock freedom.
  • Further embodiments are described in advance within this document.
  • Case I2)
  • Either
    the WRCR are already described during the configuration and the WCP is no longer necessary, since the entire SubConf has already been loaded into the respective PAE
    or
    Depending on certain WCP, CTs that are determined by CT are loaded into different WRCRs defined in the WRC. This is particularly necessary if, starting from a SubConf, a WRT occurs and branches into several different WRCs than physical WRCRegs.
  • It must be prevented that several WCTs are routed to different PAEs at different times, as this causes deadlocks. Example: WCT1 of a SubConf SA reaches the PAE p1 at clock t1, WCT2 of a SubConf SB reaches the PAE p2 at the time. The PAEs are configured accordingly. At time t2 WCT1 reaches p2 and WCT2 p1. A deadlock has occurred. It should be noted that this example in principle also A2-I1 can be applied, which is why there WCT is guided via the trigger port of the CT and handled by the CT.
  • Deadlock is also prevented by prioritizing the WCTs generated by different PAEs (sources) from a central entity (ARB) such that exactly one WCT is sent to the relevant PAEs at a time. Various methods are applicable for prioritization, by way of example some are to be mentioned:
    • a) Using an arbiter according to the prior art, in particular, the Round-Robin Arbiter PACT10 is suitable. The exact chronological order of appearance of the WCT is lost for ordinary.
    • b) If the chronological order is to be adhered to, the following procedures can be used, for example:
    • b1) A FIFO first stores the incoming WCT according to their order. At the same time incoming WCT are stored together, if no WCT occur at a time, no entry is generated. An arbiter downstream of the FIFO selects one of the entries, if several occurred simultaneously.
    • b2) From PACT18 a method is known, which allows a temporal sorting of events by means of an allocated time information (timestamp). By evaluating the timestamp, the chronologically correct sequence of the WCT can be ensured.
  • By properly forwarding the WCT from ARB to the PAEs concerned, it is ensured that the prioritized WCTs arrive in the correct order at the PAEs. The easiest way to ensure the order is that all triggers originating from ARB have exactly the same length and duration for the respective PAEs. This is ensured by proper programming or layout by a router by matching the routing accordingly and by using latency matching registers at the appropriate points. Also, to ensure proper routing, the method known in PACT18 for time synchronization of information may be used.
  • An explicit prioritization of the WCP is not necessary, since the WCP guided to the CT by the FILMO principle within the CT are processed properly as already explained. If necessary, compliance with the chronological order can be adhered to, in particular in accordance with the FILMO principle (see 2.1e).
  • 11.1.3 Note for all cases
  • The additional configuration registers of the PAEs for wave reconfiguration behave in accordance with the FILMO principle, ie the registers support the described states and implemented sequences and react accordingly to the protocols (eg CHECK / ACKREJ).
  • 11.2 Reconfiguration protocols and structure of the WRCReg
  • Three alternative reconfiguration protocols will explain the Wave Reconfiguration procedure in more detail: Normal CT Protocol : The CT reconfigures each PAE one at a time after a reconfiguration request is received, with the CT receiving a reconfiguration request for each PAE that reaches ChgPkt. This method is inefficient, since the communication effort is very high, especially for pipelined bus systems.
  • Synchronized Pipeline: This protocol is already much more efficient. The pipelined CT bus is used as a buffer by the pipeline register allocated to a PAE, which stores KW of that PAE until that PAE can pick up the KW. The CT-Bus Pipeline (CBP) is thus blocked, but can be completely filled with the KWs of the wave reconfiguration.
    1. a) If the CBP is in the same direction as the data pipeline, a few clock latencies are lost each time until, after a PAE has acquired a KW, the KW of the immediately following PAE arrives at its pipeline register.
    2. b) If the CBP runs counter to the data pipeline, the CBP can be filled completely with KW that are already pending at the particular PAE. This allows wave reconfiguration without delay.
  • Synchronized Shadow Register (Most Efficient Protocol): CT immediately after selecting SubConf (i) before ChgPkt (ii) arrives, writes the new KWs to shadow registers of all PAEs. The shadow registers can be implemented in any desired configuration. The following options are particularly useful: a) the register stage switched before the actual configuration register, b) parallel register set which is selected via multiplexer, c) FIFO stage before the actual configuration registers. At the time ChgPkt (ii) arrives at a PAE, it copies the shadow register into the corresponding configuration register. The copying happens in the optimal case such that no power stroke is lost. If, despite the arrival of ChgPkt, the shadow register is not written (ie empty), the data processing lapses until KW arrives in the shadow register. If necessary, the reconfiguration request with the ChgPkt within a pipeline is forwarded from one PAE to the next.
  • 12. Forms of parallelism and sequential processing
  • By means of sufficiently high reconfiguration performance, sequential arithmetic models can be mapped into arrays by making the low-level CTS more or less a conventional codefetcher and operating the array as a VLIW-ALU with microprogrammable networking.
  • Furthermore, all forms of parallelism can be mapped into arrays of computational elements:
    • Pipelining: Pipelines can be built by connecting PAEs in series. The VPU-compliant protocols allow easy control of the pipeline.
    • Instruction Level Parallelism: Parallel data paths can be built by parallel PAEs. The VPU-compliant protocols and especially the trigger signals allow easy control.
    • SMP, Multitasking and Multiuser: The deadlock-free configuration processes allow independent tasks to run automatically in parallel in a PA.
  • With a sufficient number of PAEs, all significant parts of conventional microprocessors can be configured to the PA. Then a sequential processing of a task can be done without CT. This must become active again only if the configured processor is to receive a partially different functionality, for example in the ALU, or to be completely replaced.
  • 13 embodiments and diagrams
  • In the Figures 1-3 is the exemplary structure of a SubConf shown. CW-PAE identifies the number of a KW within a PAE with the address PAE (eg 2-3 is the 2.KW for the PAE with the address 3). Furthermore, the flags are shown (C = Check, D = Differential, G = Go), a set flag is marked with "*".
  • In FIG. 1 is the simplest linear structure of a SubConf, as it is customary according to PACT10. A PAE is tested during the first configuration (C), then further configured (D) and finally started (G) (see PAE with address 0). Simultaneous test and start is also possible (CG, see PAE with address 1, 0101).
  • In FIG. 2 a sorted SubConf is shown that a barrier (0201) was introduced. Before the barrier, all PAEs must be tested. The barrier then waits for the receipt of all ACKs or REJs. If no REJ occurs, the barrier is skipped, the differential configurations are made and the PAEs are started. If a REJ occurs, the barrier is not skipped, instead FILMO runs are executed until no REJ occurs, then Barrier is skipped.
  • Each PAE must be tested before the barrier, and only then can the PAEs be differentially configured and started. If test and start were originally in the same cycle, the KW must now be separated (0101 -> 0202, 0203).
  • In FIG. 3 a subconf is resorted such that no barrier is needed, instead a latency is inserted between check and the arrival of ACK / REJ, during which no further check may be performed. For this purpose, the KWs are combined into atoms (0301), whereby the first KW of an atom performs a check (0302) and the block then with differential KWs or possibly NOPs (0303) until the sequence the latency is filled. The number of differential KWs depends on the latency. For reasons of representation, a latency of 3 bars was selected as an example. At 0304, ACK / REJ arrives, at which time a decision is made as to whether the configuration will be continued (0305) with the next KW, which may or may not contain a check, or aborted due to a REJ to maintain order.
  • It is essential that when configuring a PAE X first check is performed, then waiting for the arrival of ACK / REJ - during this time, an already checked PAE can be further configured, or NOPs must be introduced. Only then can PAE X be further configured. Example: Check of the PAE (0302), continuation of the configuration (0306). For 0307, NOPs must be introduced after a check because there are no differential configurations available. 0308 shows splitting configurations across multiple blocks (here 3), omitting a check (0309).
  • FIG. 4 shows a possible state machine for realizing the PAE states. The default state is IDLE (0401). By configuring the check flag (0405), the state machine enters the "allocated" state (0402). Configuring the LAST flag (0409, 0408) starts the PAE, the state is "configured" (0404). LocalReset (0407) causes the PAE to go to the "unconfigured" state (0403). In this embodiment goes the PAE only returns to IDLE after querying its status with LOCK / FREE (0406).
  • LocalReset and LAST can also be sent by the CT through a broadcast, see ModulID.
  • The Figures 5-9 show possible implementations of the FILMO method according to section 5. Only the relevant modules serving as interface to the PA are shown. Interfaces to CT are not described. These are largely implementable according to the state of the art (PACT10) and possibly require only minor modifications.
  • FIG. 5 shows the structure of a CT interface to the PA when using a STATELUT according to 5.1. A CT 0501 with RAM and integrated FILMO (0502) is shown abstracted and will not be explained in more detail, since the function is sufficiently known by PACT10 and PACT05 according to the prior art. The CT queries the status of the PA (0503) by setting the signal LOCK (0504), whereupon each PAE whose status has changed since the last LOCK, forwards this change to the STATELUT (0505) (0506). This forwarding is done in such a way that the STATELUT can unambiguously assign each PAE its status. For this purpose, several prior art methods are available, for example, each PAE can send its address along with the status to the STATELUT, which stores its status for each PAE at its address.
  • The CT first writes KWs (0510) in a register (0507). At the same time, a lookup is performed at the address (#) of the PAE concerning the respective KW in the STATELUT (0505). If the status of the PAE is "unconfigured", the CT receives an ACK (0509), otherwise a REJ. A simple protocol converter (0508) converts an ACK into an RDY to write the KW into the PA, REJ is converted to notRDY to prevent writing to the PA.
  • It should also be noted that the forwarding of LOCK, RDY, and KW to the PA and in the PA, as well as the feedback of the status of the PAEs, are pipelined by the PA, i. passes through registers.
  • In FIG. 6 the method according to 5.2 is exemplified. The technical complexity is relatively low. A CT (0601) with integrated FILMO (0602) is modified such that only for the first KW (0604) of an atom sent to the PA (0603) an acknowledgment (0605) (ACK / REJ) is expected. The receipt is evaluated at the last KW of an atom. With ACK the configuration is continued with the next atom, REJ causes the abort of the configuration of the SubConf.
  • FIG. 7 shows the structure of a FILMO (0701) according to 5.3. The FILMO is assigned the RELJMP memory (0702), whereby each entry in the RELJMP is assigned to a FILMO entry. The FILMO is designed as an integrated FILMO according to PACT10, so that RELJMP represents a linked list of KWs to be configured. In addition, it should be especially on it It should be noted that in this case the FILMO may also contain CT commands and concatenations of those according to PACT10. The linked list in RELJMP is generated as follows:
  • The read pointer (0703) points to the KW currently being configured. In 0704 is stored the address of the KW which was last rejected (REJ). If the currently configured KW (0706) is accepted by the PA (0707) (ACK, 0708), the value stored in 0702 at the address pointing to 0703 will be added to 0703. This results in a relative jump.
  • If, on the other hand, the currently configured KW is rejected (REJ, 0708), first the difference between 0703 and 0704, which is calculated by means of a subtractor (0705), is stored in RelJmp, at the address of the last rejected KW, which is stored in 0704 , In 0704, the current value of 0703 is stored. Thereafter, the value stored in 0702 at the address pointing to 0703 is added to 0703. This results in a relative jump. The controller adopts a state machine (0709), the implementation of which takes place in accordance with the procedure described. Via a multiplexer (0710) the address for the RelJmp is determined by 0709 depending on the operation by selecting between 0703 and 0704. In order to efficiently address differently 0701 and 0702 at the same time, it is useful to physically separate 0701 from implementation 0702 in order to obtain two separate memories which can be addressed separately.
  • 0711 shows the operation of the relative addressing. The address that points to an entry in RelJmp adds to the contents of RelJmp and returns the address of the next entry.
  • FIG. 8 shows a possible implementation of the method according to 5.3 with modified garbage collector. The entries in FILMO (0801) are managed linearly, which means that RelJmp is not needed. 0801 is implemented as a separate FILMO. A read pointer (0804) addresses the KWs (0803) which are written to the PA (0802). All KWs are written in the order of their configuration in a FIFO or FIFO-like memory (0805), which may for example also be designed as a shift register. The memory is just as deep as clocks from sending a KW to the PA pass until the acknowledgment (RDY / ACK, 0806) arrives.
    • Upon arrival of a REJ, the rejected KW assigned to the REJ, which at this time is at the output of the FIFO, is written in 0801. REJ is used as a write signal for the FILMO (REJ-> WR). The write address is generated by a write pointer (0807), which is incremented after the write access.
    • When an ACK arrives nothing happens, the configured KW assigned to the ACK is ignored, 0807 remains unchanged.
  • This creates a new linear sequence of rejected KWs in the FILMO. The implementation of the FILMO as dual-ported RAM with separate read and write ports is proposed for performance reasons.
  • FIG. 9 shows an implementation of the method according to 5.4. It can be seen that this is a modification of the method according to 5.3.
  • By means of a read pointer (0909), the KW (0902) to be written to the PA (0901) is addressed in the FILMO (0910). The address and flags (0902a) of the PII to be configured from 0902 are first sent as a test to the PA. The KW with the address of the PAE to be configured is written to a FIFO-like memory (0903, corresponding to 0805). 0902a is pipelined to the PA. The access is evaluated and acknowledged in the addressed PII. The acknowledgment (RDY / ACK) is also sent back in pipelined form (0904). 0903 delays as long as clocks from the sending of 0902a to the PA pass until the receipt of the acknowledgment (RDY / ACK, 0904).
    • If acknowledged with ACK, the complete KW (0905) (address + data) at the output of 0903 assigned to the corresponding acknowledgment is sent to the PA in pipelined form (0906). A receipt for this is not expected since it is already known that the addressed PAE accepts the KW.
    • At REJ, the KW is written back to the FILMO (0907). A write pointer (0908) corresponding to 0807 is used for this purpose. The pointer is incremented.
  • 0904 is thereby converted by means of a simple protocol converter (0911) (i) at ACK into a write signal for the PA (RDY) and (ii) at REJ into a write signal 0901 for the FILMO (WR).
  • The result is a new linear sequence of rejected KWs in the FILMO. The implementation of the FILMO as dual-ported RAM with separate read and write ports is proposed for performance reasons.
  • FIG. 10 shows an embodiment of the inventive Inter-CT protocol. 4 levels of CT are shown. The RootCT (1001), CTs of 2 intermediate levels (1002a-b and 1003a-d), the low-level CTs (1004a-h) and their FILMOs (1005a-h). In the PA associated with 1004e, a trigger is generated which can not be translated to any local subconf within 1004e, but is assigned to an EnhSubConf. 1004e sends a REQUEST to 1003c for this EnhSubConf. 1003c did not cache the IDChain. The EnhSubConf is partially executed even on 1004g, which is not a sheet of 1003c. Thus, 1003c forwards the REQUEST to 1002b. The hatching indicates that 1002b could have cached the IDChain, since 1004g is a 1002b leaf. However, assuming 1002b has not yet cached IDChain, it requests it at 1001. 1001 loads the IDChain from the CTR (see PACT10) and sends it to 1002b. The process will hereafter referred to as GRANT. 1002b cached the IDChain since all involved CT leaves are of 1002b. Then, 1002b sends the GRANT to 1003c and 1003d atomically, without interruption by another GRANT. In doing so, the IDChain is split and sent to two different CTs, so that none of the recipients can be a common manager of all the leaves. The flag Split is set, the receivers and all lower CTs can no longer cache the IDChain. In turn, 1003c and 1003d atomically send the GRANT to the low-level CTs 1004f and 1004g, respectively. The low-level CTs directly store the incoming GRANT in a corresponding list which characterizes the order of the SubConf characterizing list, which for example can be configured separately or can result from the direct execution of the configuration with an optionally entered entry of rejected KWs into the FILMO.
  • There are two variants for the low-level CTs:
    • Either you have already cached the IDChain corresponding subconf to be started, then the configuration is started immediately.
    • Or they have not yet cached the SubConf corresponding to the ID according to IDChain, then they must first request this from the higher-level CTs. The request (GET) is in FIG. 11 clarifies, again, it is assumed that none of the CTs from the intermediate levels has cached the SubConf. The respective SubConf is therefore loaded by the RootCT from the CTR and sent to the low-level CTs (DOWNLOAD). The process is principle known from PACT10 and should therefore not be specified.
  • In any case, however, it is essential that after the arrival of a GRANT, this is executed before any further GRANT. If GRANT A arrives before GRANT B, then GRANT A must be configured before GRANT B. This is true even if the SubConf of GRANT A has to be loaded first, while GRANT B's SubConf would be cached in the low-level CT and could be started immediately. The order of the incoming GRANTs must be adhered to, otherwise a deadlock can occur under the EnhSubConf.
  • In a particular embodiment of the method described, CTTREE CTs can directly access configurations without involving the overlying CTs by connecting to a hardwired, volatile or non-volatile memory or mass storage. This memory can be, for example, an SRAM, DRAM, ROM, Flash, CDROM, hard disk or server system, which may also be connected via network (WAN, LAN, Internet). It should be expressly mentioned that therefore also the direct access of a CT bypassing the overlying CTs to a memory for configuration data is possible. Also in such a case, the synchronization of the configuration within the CTTREE, particularly at EnhSubConf, takes place involving the overlying CTs.
  • FIG. 12 shows three examples ( FIGS. 12a-12c ). Shown is the configuration stack of 8 CTs (1201-1208). Of the Configuration Stack is the list of SubConf to configure. The SubConf are configured in the same order as they are in the list. A configuration stack is formed, for example, by the concatenation of individual subconfs, as described in PACT10 FIGS. 26-28. Another possibility is a simple list of IDs pointing to the SubConf, as in FIG. 12 , Lower entries are configured first, higher ones last.
  • In FIG. 12a There are two EnhSubConf (1210, 1211) that are correctly located in the configuration stack of each CT. The individual SubConf of the EnhSubConf are configured deadlock-free in the correct order. The order of the GRANTs was considered.
  • Also the example in FIG. 12b is correct. Three EnhSubConf are shown (1220, 1221, 1222). 1220 is a great EnhSubConf that affects all CTs. 1221 only affects the CTs 1202-1206, another concerns the CTs 1207 and 1208. All SubConf are configured deadlock-free in the correct order. The GRANT for 1222 was completely processed before the GRANT for 1220 and this before the GRANT for 1221.
  • The example FIG. 12c shows several deadlock situations. In 1208, the order of the GRANTs of 1230 and 1232 was reversed. The result is that resources assigned to 1230 are allocated in the PA allocated in 1208, and resources allocated to 1232 in the 1208 associated PA. The resources are all fixed. This creates a deadlock because no EnhSubConf can be executed or deconfigured.
  • Also, in the CTs 1204 and 1205, the GRANTs of 1230 and 1231 are temporally reversed. This also creates a deadlock for the same reasons.
  • In FIG. 13a is a performance optimized version of the inter-CT communication shown. In this case, a download is carried out directly to the low-level CT, ie CTs of the middle levels do not have to first receive, save and then forward the SubConf. Rather, these CTs only "hear" (1301, 1302, 1303, LISTENER) and cache the SubConf.
  • The schematic bus structure is in FIG. 13b shown. A bypass (1304, 1305, 1306), usually in the form of a register, passes the download on the mid-level CTs.
  • FIG. 14 shows the possible construction of a circuit between CT and PA, for easy configuration of SubConf macros. A KW is transmitted via the bus (1401) from the CT. The KW is decomposed into its configuration data (1402), as well as the PAE addresses X (1403) and Y (1404) (in case of multi-dimensional addressing, correspondingly more addresses have to be decomposed). 1405 adds an X offset to the X address and 1406 adds a Y offset to the Y address. The offsets may be different and are stored in a register (1407). The parameterizable portion of the data (1408) is passed as an address to a look-up table (1409) in which the actual values are stored. The values are linked with the non-paramatable data (1412) (1410). A multiplexer (1413) can be used to select whether a lookup should be performed or whether the data should be used directly without a lookup. The selection is made by means of a bit (1411). All addresses and data are re-linked and routed as a bus (1413) to the PA. Depending on the implementation of the FILMO the circuit described upstream or downstream; integrated FILMOs are connected upstream, separate FILMOs downstream. Via the bus 1415, the CT sets the address offsets and the parameter translation in 1409. For the sake of simplicity, 1409 may be configured as dual-ported RAM.
  • The structure of a corresponding KW is as follows: X address Y address dates Address for 1409 MUX = 1 X address Y address dates dates MUX = 0 If MUX = 1, a lookup is performed in 1409, with MUX = 0 the data is forwarded directly to 1414.
  • In FIG. 15 is the execution of a graph illustrated. The respectively next possible nodes (1..13) of the graph are prefetched, accordingly previous nodes and unused jumps are deleted. Within a loop, the nodes of the loop are not deleted (10,11,12), the corresponding nodes are only removed after termination. Nodes are only loaded if they are not already in the memory of the CT. Repeated execution of (eg) 11 therefore does not lead to multiple occurrences load 12 or 10. "delete 8.9" will be ignored in 11 if 8 and or 9 have already been removed.
  • FIG. 16 schematizes the multiple instantiation of a SubConf macro (1601). Various SubConf (1602, 1603, 1604) call 1601. The parameters for 1601 are preloaded (1610) by the calling SubConf in a LookUp table (1605). 1605 is implemented only once, in FIG. 16 but drawn several times to symbolize the different contents.
  • 1601 is called. The KWs are transmitted to 1605, 1606 and 1607. These elements work as follows:
    • Based on a lookup, the corresponding content of 1605 is reconnected to the KWs (1606). After the multiplexer 1413 (1607), which selects whether the original KW is valid or a lookup has been performed, the KW is sent to the PA (1608).
  • FIG. 17 schematically shows the process of a wave reconfiguration. Plain hatched areas represent data processing PAEs, with 1701 showing PAEs after reconfiguration and 1703 PAEs before reconfiguration. Double hatched areas (1702) show PAEs that are currently being reconfigured or waiting to be reconfigured. Figure 17a shows the influence of wave reconfiguration on a simple sequential algorithm. Here it is possible to reconfigure exactly the PAEs to which a new task is assigned. Because in every bar a PAE is a new one This task can be done efficiently, namely at the same time.
  • For example, shown is a set of PAEs from the matrix of all PAEs of a VPU. Indicated are the states in the clocks after clock t with one clock delay.
  • In FIG. 17b the temporal effect of reconfiguration is shown in large parts. For example, shown is a set of PAEs of a VPU. Indicated are the states in the clocks after clock t with a different delay of several clocks.
  • While initially only a small portion of the PAEs are reconfigured or waiting for reconfiguration, this area becomes larger with time until all PAEs are reconfigured. The larger the area means that due to the time delay of the reconfiguration more and more PAEs are waiting for the reconfiguration (1702). As a result, computing power is lost.
  • It is therefore proposed to use a wider bus system between the CT (in particular the memory of the CT) and the PAEs, which provides enough lines to simultaneously reconfigure several PAEs within one cycle. NOT CONFIGURED WAVE TRIGGER W C D X - X X - Wave reconfiguration X - X - X REJ - X X X - REJ - X X - X Differential wave reconfiguration - normal configuration
  • FIG. 18 shows by way of example different configuration strategies for a reconfiguration method similar to the "synchronized shadow register" according to 11.2. Shown in each case schematically is the CT (1801), as well as one of several PAEs (1804), wherein within the PAE only the configuration registers (1802, 1803) are shown, as well as a unit for selecting the active configuration (1805). Other functional units within the PAE were not shown for reasons of clarity. The CT has in each case n SubConf (1820), whereby in cases -I1 the respective KW of a SubConf is loaded in a WCP occurring (1 (n)) and in cases -I2 the KW of m SubConf is calculated from the total amount of n to be loaded (m (n)). The different connection of WCT (1806) and WCP (1807) is shown, as well as the optional WCP (1808) as described below.
  • In A1-I1 , within the same SubConf, a next WCP configuration selects a next configuration that uses the same resources or whose resources are at least already pre-reserved and are not occupied by any other than possibly the WCP-generating SubConf. Through the CT (1801) the configuration is loaded. In the example shown here, the configuration is not directly executed but loaded into one of several alternate registers (1802). By a second trigger WCT, exactly at the time of the required reconfiguration, one of the alternative registers is selected such that the configuration previously loaded due to WCP is executed.
  • Basically, a specific configuration is determined and preloaded by WCP, and WCT determines the timing of the actual functional change corresponding to the preloaded reconfiguration.
  • Both WCP and WCT can be a vector so that one of several configurations is precharged by WCP (v 1 ), where by the source of WCP the preloaded configuration is specified. WCT (v 2 ) selects one of several pre-loaded configurations accordingly. In this case, a number of 1802 corresponding to the set of v2 selectable configurations is required, with the number usually fixed so that v2 is equal to the maximum amount.
  • On the basis of this, in A1-I2 a version with a register set 1803 with a plurality of 1802 is shown. In the optimal case, the number of registers in 1803 is so large that all possible subsequent configurations can be directly pre-charged, thus rendering WCP can be omitted, so that only the time of the function change and the change itself by WCT (v 2 ) is specified.
  • A2-I1 shows the WRC such that a next configuration is selected that does not use the same resources or whose resources are not pre-reserved or occupied by any other than possibly the WCP (v 1 ) generating SubConf. The deadlock-free configuration is ensured by the FILMO-compliant reaction and configuration on WCP (v 1 ). The starting of configurations by WCT (v 2 ) (1806) is also performed atomically by the CT by the FILMO-compliant atomic response to the arrival of triggers (ReconfReq) indicating a reconfiguration time.
  • In A2-I2 , all subsequent SubConfs are either precharged to the configuration registers 1803 the first time a SubConf is loaded, or if necessary, unless the number of configuration registers is sufficient, reloaded by the CT using the known handling of an occurring WCP (v 1 ).
  • The triggers (ReconfReq, 1809), which determine a reconfiguration time and initiate the actual reconfiguration, are first decoupled in time via a suitable prioritizer (1810) and passed to the PAEs as WCT (v 2 ), so that only exactly one WCT (v 2 ) is active at a time at a PAE and the order of the WCT (v 2 ) is the same for all PAEs concerned.
  • For A2-I1 and A2-I2 , an additional triggering system is used in these embodiments. Both in the processing of WCT by 1801, so even when processing by 1810 can occur a significant delay until forwarding to 1804. However, it is essential that the time ChgPkt be kept exactly in time since otherwise the PAEs would incorrectly process the subsequent data. Therefore, another trigger (1811, WCS = WaveConfigurationStop) is used, which only stops the data processing of the PAEs until the new configuration is activated by the arrival of the WCT. WCS is usually generated within the currently active SubConf. In many cases, ReconfReq and WCS can be identical, since, as long as ReconfReq is generated within the currently active SubConf, this signal usually also marks the achievement of ChgPkt.
  • FIG. 19 shows an implementation variant of A1-I2 and A2-I2, wherein instead of a register file, a FIFO memory (1901) is used to manage the KW. The order of the SubConf specified by WCP is fixed. By the occurrence of WCT (or WCS, alternatively represented by 1902), only the next configuration can be loaded from the FIFO. The essential function of WCS, that is, stopping the current data processing is exactly the same as in FIG. 18 described.
  • In FIG. 20 FIG. 12 illustrates a portion of a line of PAEs to exemplify a reconfiguration process similar to the "Synchronized Pipeline" of FIG. 11.2. A CT (2001) is assigned to several CT Interface Assemblies (2004) by PAEs (2005). 2004 is integrated in 2005 and is shown deprecated for better representation function of WAIT and WCT only. The signals for transmitting the configuration data from 2004 to 2005 are not shown for reasons of abstraction.
  • The CT is connected to the 2004 by means of a pipelined bus system, with 2002 being the pipeline stages. 2002 consists of a register (2003b) for the configuration data (CW) and another register (2003a) with integrated decoder and logic. 2003a decodes the address transmitted in CW and sends a signal RDY 2004 if the local PAE concerned is addressed or a signal RDY to the next stage (2002) unless the local PAE is addressed. Accordingly, 2003a accepts the acknowledgment (GNT), executed as RDY / ACK according to the known protocol, either from 2002 or from 2004.
  • This creates a pipelined bus that transfers the CW from the CT to the addressed PAE and their acknowledgment back to the CT.
  • If WCT is active in 2004, the pending CW, which are marked with WAVE as described, are configured in 2004, GNT is acknowledged with ACK.
  • As long as WCT is not active, but CW is present for configuration, GNT will not be acknowledged, i. the pipeline is blocked until the configuration is completed.
  • Expected in 2005 a wave reconfiguration, characterized by an active WCT and no WAVE marked CW are 2004, quit 2004 with WAIT to put the PAE (2005) in a waiting, non-data processing state until CW marked WAVE in 2004 were configured.
  • CWs that were not transferred using WAVE will be rejected during data processing with REJ.
  • It should be noted that this figure is intended to illustrate only the basic principle. By application-specific special configurations optimizations can be performed. For example, a register stage in 2004 that caches the incoming WAVE labeled CW until WCT arrives and the reconfiguration associated with it, can prevent pipeline stalling if CWs sent by the CT are not immediately dropped from the addressed 2004.
  • 2010 and 2011 should mark the direction of data processing for further explanation.
  • If data processing is progressing towards 2010, fast wave reconfiguration of the PAEs is possible as follows: The CT sends the CW labeled WAVE into the pipeline so that first the CWs of the farthest PAE are sent. Unless the CW can be configured immediately, the farthest pipeline stage (2002) is blocked. Thereafter, the CT sends the CW to the now farthest PAE and so on until the last data is sent to the next PAE.
  • As soon as ChkPkt runs through the PAEs, the new CWs can now be configured in each cycle. The method is also efficient if ChgPkt runs concurrently with the transmission of the CW from the CT by the PAEs, since the CW required for the configuration at the respective PAE can also be present in each cycle.
  • If the data processing is in the opposite direction (2011), the pipeline can also be configured from the CT most distant PAE to the closest PA to the CT. If ChgPkt does not occur at the same time as the data transfer of the CW, the process remains optimal, since when CgPkt occurs, the CW can be immediately transferred from the pipeline to the 2004.
  • However, if ChgPkt appears at the same time as the CW of the wave reconfiguration, wait cycles occur. For example, when ChgPkt occurs at clock n, PAE B should be configured. The CW are up and will be configured in 2004. At clock n + 1, ChgPkt (and thus WCT) is at PAE C. The CW of However, PAE C will only be broadcast in PAE B in 2002 at the best, as PAE B was still using CW in the previous 2002 measure. Only in time to n + 2 are the CWs of PAE C in their 2002 and can be configured. In clock n + 1, a waiting cycle has arisen.
  • FIG. 21 shows the most common synchronization strategy for wave reconfiguration. A first PAE 2101 recognizes the need for reconfiguration due to an occurring condition. The recognition can be carried out according to usual methods, for example a comparison of data or states. By recognizing, 2101 sends a request (2103), which may be made by a trigger, to one or more PAEs (2102) to be reconfigured, which stops the data processing. Further, 2101 sends a signal (2105), which may also be the same signal 2103) to a CT (2104) to request reconfiguration. 2104 reconfigures 2102 (2106) and informs (2107) after reconfiguration of all PAEs 2101 to be reconfigured, if appropriate by means of reconfiguration via the completion of execution. In response, the suspend request 2103 will decrease in 2001 and data processing will continue. 2108 and 2109 each symbolize data and trigger inputs and outputs.
  • FIG. 22 illustrates one way to provide routing for proper time-forwarding of WCT. From a central instance (2203) will be multiple WCT generated for different PAEs (2201), but which should be timed to each other. The different distances of the 2201 in the matrix lead to different transit times or latencies. This is achieved in the present example by the appropriate insertion of pipeline stages (2202) by the router associated with the compiler (see PACT13). The resulting latencies are indicated by d1-d5. It can be seen that the same latencies occur in the direction of the data flow (2204) in each stage (column). For example, 2205 would not be necessary because the distance of 2206 from 2203 is very small. However, since 2202 and 2208 each have to insert a 2202 due to the runtime resulting from the longer distance, 2205 is necessary to match the runtime.
  • FIG. 23 should show an application of wave reconfiguration. A major advantage of VPU technology is to be shown, namely the optional use of PAE resources or reconfiguration time to solve a task, resulting in a compiler or programmers adjustable intelligent Tradeoff between cost and performance.
  • A data stream shall (2301) be calculated in an array (2302) of PAEs (2304-2308). The array is assigned a CT (2303), which is responsible for its reconfiguration. 2304 is responsible for detecting the final state of the data processing which requires a reconfiguration. The detection is signaled to the CT. 2306 identifies the Beginning and 2309 the end of a branch symbolized by (2307a, 2307b, and 2307ab, respectively). The PAEs 2308 are not used. The different triggers are represented by 2309.
  • In FIG. 23a is selected by 2305 one of the two branches 2307a, 2307b and activated by trigger at the same time as the data arriving from 2306.
  • In FIG. 23b should not be completely preconfigured from 2307a and 2307b, but both possible branches should share the resources 2307ab by reconfiguration. 2305 continues to select the branch necessary for data processing. The information is now on the one hand led to 2303, on the other hand to 2306, according to FIG. 21 stop the data processing until the complete reconfiguration of 2307ab.
  • FIG. 24 represents a possible alternative implementation according to 4.2 of a state machine for sequential control of the PAE: The following states are implemented:
    • Not Configured (2401)
    • Allocated (2402)
    • Wait for Lock (2403)
    • Configured (2404)
    • The following signals trigger a change of state:
    • LOCK / FREE (2404, 2408)
    • CHECK (2405, 2407)
    • RECONFIG (2406, 2409)
    • GO (2410, 2411)
  • FIG. 25 shows the known from PACT 13 construction of a high-level language compiler, which translates, for example, ordinary sequential high-level languages (C, Pascal, Java) to a VPU system. Sequential code (2511) is separated from parallel code (2508), which processes 2508 directly in the array of PAEs.
  • For 2511 there are three execution options:
    1. 1. Within a sequencer of a PAE (see PACT13, 2910)
    2. 2. Using a sequencer configured in the VPU. On the one hand, the compiler generates a sequencer optimized for the task, and on the other hand directly generates the algorithm-specific sequencer code (see PACT13, 2801).
    3. 3. On an ordinary external processor (see PACT13, 3103)
    4. 4. By rapidly reconfiguring by means of a CT by choosing the ratio between the number of PAEs within a PAC and the number of PACs such that one or more PACs can be set up as dedicated sequencers whose opcodes and instruction execution from the associated CT in be configured for each work step. The assigned CT responds to the status of the sequencer to determine the respective subsequent program sequence. The status is transmitted by means of the trigger system.
  • Which option is chosen depends on the architecture of the VPU, the computer system and the algorithm.
  • The principle is known from PACT13. However, it should be pointed out expressly to the extensions of the router and placer (2505) according to the present disclosure.
  • The code (2501) is first separated (2517) in a preprocessor (2502) into data flow code (2516) (which has been written in a special version of the particular programming language optimized for data flow) and ordinary sequential code. 2517 is examined for parallelizable subalgorithms (2503), the sequential subalgorithms are discarded (2518). The parallelizable subalgorithms are provisionally placed and routed as macros.
  • In an iterative process, the macros are placed, routed, and partitioned using the data flow optimized code (2513) (2505). A statistic (2506) evaluates the individual macros and their partitioning in terms of efficiency, whereby the reconfiguration time and the effort of the reconfiguration are included in the efficiency analysis. Inefficient macros are removed and discarded as sequential code (2514).
  • The remaining parallel code (2515) is compiled and assembled together with 2516 (2507) and VPU object code is output (2508).
  • Statistics on the efficiency of the generated code, as well as the individual (including the macros removed with 2514) is output (2509), the programmer thus receives significant information on speed optimizations of the program.
  • Each macro of the remaining sequential code is examined for its complexity and requirements (2520). From a database that depends on the VPU architecture and the computer system (2519), the appropriate sequencer is selected and output as VPU code (2521). A compiler (2521) generates the assembly code of the respective macro for the respectively selected sequencer of 2520 and outputs it (2511). The 2510 and 2520 are closely linked. If necessary, the processing is iterative to find the most suitable sequencer with minimal and fastest assembler code.
  • A linker (2522) summarizes the assembler codes (2508, 2511, 2521) and generates the executable object code (2523).
  • definitions
  • ACK / REJ Acknowledge log of a PAE to a (re) configuration attempt. ACK indicates that the configuration has been accepted, REJ indicates that the configuration has been rejected. The protocol stipulates that the arrival of either ACK or REJ is waited for and, if necessary, waiting cycles are inserted.
  • CT unit to interactively configure and reconfigure configurable items. A CT has a memory for caching and / or caching SubConf. In particular embodiments, CTs that are not root CT also have a direct connection to a memory for SubConf, which in this case is not loaded by an overlying CT.
  • CTTREE One or multidimensional tree of CTs.
  • EnhSubConf configuration that contains several SubConf that have to be executed on different PACs.
  • Configuration Complete executable algorithm.
  • configurable element Physically arbitrary element whose exact function within the implemented possibilities is determined by a configuration. In particular, a configurable element as a logical Functional unit, arithmetic functional unit, memory, peripheral interface, bus system be configured; in particular, elements of known technologies such as FPGAs (eg CLBs), DPGAs, VPUs and all elements known under "reconfigurable computing" are included. A configurable element can also be a complex combination of several different functional units, eg an arithmetic unit with an integrated assigned bus system.
  • KW configuration word. One or more data that determines the configuration or part of a configuration of a configurable item.
  • Latency Delay within a data transfer that is usually clock-based in synchronous systems and therefore specified in clock cycles.
  • PA processing array, arrangement of several differently designed PAEs
  • PAC A PA with the associated CT responsible for configuring and reconfiguring this PA
  • PAE Processing Array Element, configurable element
  • ReconfReq trigger will be generated due to a condition requiring reconfiguration and will identify it.
  • Reconfigure Loading a new configuration, possibly simultaneously or superimposed or in parallel to a data processing, without hindering or falsifying the processing of data.
  • Root CT Highest CT in the CTTREE, but usually not exclusively the only CT connected to the configuration memory.
  • SubConf part of a configuration consisting of several KW.
  • WCT Indicates the time to reconfigure. It can optionally select one of several possible configurations by transmitting additional information. Usually, WCT runs exactly synchronously with the termination of the data processing currently in progress and for reconfiguration. If WCT is transferred later for implementation reasons, WCS is used to synchronize the data processing.
  • WCP Requests one or more alternative next configuration (s) in CT to (re) configure to.
  • WCS Stops the data processing until the arrival of WCT. Must only be used if, due to the implementation, WCT does not exactly indicate the time of the required reconfiguration, but only arrives at the respective PAE after the actual end of the data processing of the configuration to be terminated.
  • Cell configurable element
  • references
  • PACT01
    4416881
    PACT02
    19781412.3
    PACT04
    19654842.2-53
    PACT05
    19654593.5-53
    PACT07
    19880128.9
    PACT08
    19880129.7
    PACT10
    19980312.9 & 19980309.9
    PACT13
     PCT / DE00 / 01869
    PACT18
    10110530.4

    Claims (2)

    1. Method for operating a data processing device with a one-dimensional or multidimensional reconfigurable cell structure (PA),
      characterized in that,
      together with the configuration data, flags which are concomitantly transmitted are used to indicate
      whether cells (1701, 1702, 1703)
      can be newly or
      partially
      configured,
      a cell only accepting a configuration,
      which is recognized as being a new configuration by means of the flags,
      if it is in an unconfigured state,
      or
      the cell only accepting a configuration,
      which is recognized as being a partial configuration by means of the flags,
      if it is in a configured state.
    2. Method according to the preceding claim, characterized in that the cell (1701, 1702, 1703) is started in response to the arrival of a further flag.
    EP20010984500 2000-06-13 2001-06-13 Pipeline configuration unit protocols and communication Expired - Fee Related EP1342158B1 (en)

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    DE10028397 2000-06-13
    DE2000128397 DE10028397A1 (en) 2000-06-13 2000-06-13 Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
    DE10110530 2001-03-05
    DE10110530 2001-03-05
    PCT/EP2001/006703 WO2002013000A2 (en) 2000-06-13 2001-06-13 Pipeline configuration unit protocols and communication

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