WO1998020671A1 - Apparatus for capturing a frame of video data for sending to a printer - Google Patents

Apparatus for capturing a frame of video data for sending to a printer Download PDF

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Publication number
WO1998020671A1
WO1998020671A1 PCT/IE1997/000072 IE9700072W WO9820671A1 WO 1998020671 A1 WO1998020671 A1 WO 1998020671A1 IE 9700072 W IE9700072 W IE 9700072W WO 9820671 A1 WO9820671 A1 WO 9820671A1
Authority
WO
WIPO (PCT)
Prior art keywords
video signal
video
frame
random access
dynamic random
Prior art date
Application number
PCT/IE1997/000072
Other languages
French (fr)
Inventor
David Charles Yeomans
Gerard William O'grady
Original Assignee
Tangate Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tangate Limited filed Critical Tangate Limited
Priority to AU52342/98A priority Critical patent/AU5234298A/en
Publication of WO1998020671A1 publication Critical patent/WO1998020671A1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/00127—Connection or combination of a still picture apparatus with another apparatus, e.g. for storage, processing or transmission of still picture signals or of information associated with a still picture
    • H04N1/00281—Connection or combination of a still picture apparatus with another apparatus, e.g. for storage, processing or transmission of still picture signals or of information associated with a still picture with a telecommunication apparatus, e.g. a switched network of teleprinters for the distribution of text-based information, a selective call terminal
    • H04N1/00283—Connection or combination of a still picture apparatus with another apparatus, e.g. for storage, processing or transmission of still picture signals or of information associated with a still picture with a telecommunication apparatus, e.g. a switched network of teleprinters for the distribution of text-based information, a selective call terminal with a television apparatus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/32—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device
    • H04N1/32358—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device using picture signal storage, e.g. at transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/32—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device
    • H04N1/32358—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device using picture signal storage, e.g. at transmitter
    • H04N1/32491—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device using picture signal storage, e.g. at transmitter alternate storage in and retrieval from two parallel memories, e.g. using ping-pong buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2201/00—Indexing scheme relating to scanning, transmission or reproduction of documents or the like, and to details thereof
    • H04N2201/0077—Types of the still picture apparatus
    • H04N2201/0082—Image hardcopy reproducer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2201/00—Indexing scheme relating to scanning, transmission or reproduction of documents or the like, and to details thereof
    • H04N2201/0077—Types of the still picture apparatus
    • H04N2201/0084—Digital still camera
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2201/00—Indexing scheme relating to scanning, transmission or reproduction of documents or the like, and to details thereof
    • H04N2201/0077—Types of the still picture apparatus
    • H04N2201/0089—Image display device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2201/00—Indexing scheme relating to scanning, transmission or reproduction of documents or the like, and to details thereof
    • H04N2201/32—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device
    • H04N2201/3285—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device using picture signal storage, e.g. at transmitter
    • H04N2201/329—Storage of less than a complete document page or image frame
    • H04N2201/3291—Storage of less than a complete document page or image frame of less than a complete line of data

Definitions

  • the present invention relates to apparatus for capturing a frame of video data and for presenting the frame of video data in a form for sending to a printer.
  • the present invention is directed towards providing such apparatus.
  • apparatus for capturing a frame of video data and presenting the frame of video data in a form for sending to a printer
  • the apparatus comprising an input means for receiving an analogue video signal and for converting the video signal from analogue to digital form, a storing means for receiving the digital video signal from the input means and for storing the video signal, a first output means for receiving the digital video signal from the input means or the storing means, and for converting the digital video signal to analogue form for outputting to an analogue video signal receiver, a second output means for receiving a frame of the video signal in digital form for outputting to a printer for printing the frame, and a control means for controlling the operation of the apparatus
  • the storing means comprises a dynamic random access memory having a memory architecture such that there is a different number of storage locations per line in the storage means than there are pixels per line in the video signal, a pair of input buffer means being provided for storing respective alternate video pixels for providing time to allow a row address of the dynamic random access memory to
  • each buffer means comprises a latch.
  • a clock signal generating means for generating clock signals for controlling reading and writing between the dynamic random access memory and the respective input and output buffer means, the clock signals outputted by the clock signal generating means being derived from a clock signal in the analogue video signal.
  • each dynamic random access memory comprising a memory architecture of 256Kbytes x 16.
  • a video address generating means for generating frame and store addresses in the dynamic random access memory at which video pixels from the input means are stored or from which the video pixels are retrieved.
  • a refresh address generating means is provided for generating frame, store and row addresses at which refresh is to occur.
  • Fig. 1 is a block representation of apparatus according to the invention for capturing a frame of video data and for presenting the frame of video data in a form for sending to a printer
  • Fig. 2 is a block representation of a detail of the apparatus of Fig. 1.
  • the apparatus 1 for capturing a frame of video data and for presenting the frame of video data in a form for sending to a printer (not shown).
  • the apparatus 1 comprises an input means, namely, an input unit 2 having an input terminal 3 for continuously receiving an analogue video signal of the video data.
  • the input unit 2 comprises a digital to analogue converter (not shown) for converting the analogue video signal into digital form.
  • Outputs 4 from the input unit 2 continuously output the video signal in digital form.
  • a storing means namely, a storing unit 5 which is described in detail below with reference to Fig. 2 receives and stores the video signal one frame at a time in digital form.
  • a first output means namely, a first output unit 6 continuously receives the video signal in digital form from the input unit 3 or from the storing unit 5 on inputs 7.
  • the first output unit 6 comprises a digital to analogue converter (not shown) for converting the video signal in digital form into analogue form and for outputting the analogue form of the signal on an output 8 for transmission to an analogue video signal receiver, for example, a visual display unit, television monitor, or the like, none of which are shown.
  • a second output unit 10 receives a stored frame of the video signal from the storing unit 5 for relay to a printer (not shown) in digital form on an output 11.
  • a control means in this case a microprocessor 12 controls the operation of the apparatus 1, and in response to an external signal causes the storing unit 5 to output a stored frame of the video signal to the second output unit 10 for relay to the printer.
  • the video signal is routed through the storing unit 5 from the input unit 2 to the first output unit 6, and the video signal from the first output unit 6 is displayed on a video display unit. The user may then select any frame being displayed on the video display and on a command to the microprocessor 12, the storing unit 5 downloads the currently stored frame of the video signal to the second output unit 10.
  • DRAM dynamic random access memory
  • the memory architecture of the DRAM 15 is 256Kbytes x 16.
  • the number of pixels per line is between 640 and 738.
  • the row address must be changed in most if not all of the video lines.
  • the digital video signal from the input unit 2 is written into a pair of input buffers, namely, input latches 16 and 17 in such a way that alternate pixels in the digital video signal are written into the respective input latches 16 and 17.
  • a swapping circuit 20 controls the writing of the alternate pixels into the respective latches 16 and 17 by alternately routing strobe signals to the respective latches 16 and 17.
  • the swapping circuit 20 is controlled by the microprocessor 12, and derives its input signals from the clock signal in the video signal.
  • the pixels in the input latches 16 and 17 are alternately written to the DRAM 15 under the control of the microprocessor 12 and clock signals from the swapping circuit 20.
  • the video signal stored in the DRAM 15 is written from the DRAM 15 into output buffers, namely, output latches 22 and 23 in such a way that alternate pixels in the video signal are written into the respective output latches 22 and 23.
  • the pixels are alternately read by the first and second output units 6 and 10 from the output latches 22 and 23 under the control of the microprocessor 12 and under the control of the clock signals from the swapping circuit 20.
  • each pixel is stored in one of the input latches 16 and 17 for twice the time that it would normally be available to the DRAM 15, sufficient time is left for the DRAM row address to be changed during the middle of a video line.
  • the output latches 22 and 23 likewise provide sufficient time for reading the DRAM row address when the stored signal is being read from the DRAM 15 through the output latches 22 and 23 by either or both of the first and second output units 6 and 10.
  • a video address generating means is provided by a sub-module (not shown) which operates under the control of the microprocessor 12 for generating the frame store addresses at which the video signal is stored in the DRAM 15 or from which the video signal is retrieved for presentation to either of the first and second output units 6 and 10.
  • a refresh address generating means is also provided by a sub-module (not shown) which operates under the control of the microprocessor 12 for generating the frame store row addresses at which refresh is to occur.
  • the video signal under the control of the microprocessor 12 is read by the first output unit 6 directly from the input unit 2, and thus relayed to the video display unit by the first output unit 6.
  • the video signal is routed through the storing unit 5, and is read by the first output unit 6 and is relayed to a video display unit.
  • the second output unit 10 To capture a frame of the video signal which is displayed on the video display unit a signal is inputted to the apparatus 1, and under the control of the microprocessor 12 the second output unit 10 reads that frame from the DRAM 15 through the output latches 22 and 23, and in turn downloads the frame to the printer.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Human Computer Interaction (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

The apparatus (1) comprises an input unit (2) for receiving and converting an analogue video signal to digital form. A storing unit (5) stores the digital signal which is read by a first output unit (6) and relayed to a visual display unit (not shown); a second output unit (10) on command reads a stored video frame from the storing unit (5) and downloads the frame to a printer for printing. The storing unit (5) comprises a DRAM (15), and the digital video signal is written to the DRAM (15) alternately through input latches (16 and 17) for providing sufficient time to allow a DRAM row address to be changed in a line of the video signal.

Description

"Apparatus for capturing a frame of video data for sending to a printer"
The present invention relates to apparatus for capturing a frame of video data and for presenting the frame of video data in a form for sending to a printer.
Such apparatus are known. However, in general, they tend to be relatively expensive. One of the reasons for the relative expense of such known apparatus is that they tend to use relatively expensive memories.
There is therefore a need for an apparatus for capturing a frame of video data and for presenting the frame of video data in a form for sending to a printer which is relatively less expensive than those known heretofore.
The present invention is directed towards providing such apparatus.
According to the invention there is provided apparatus for capturing a frame of video data and presenting the frame of video data in a form for sending to a printer, the apparatus comprising an input means for receiving an analogue video signal and for converting the video signal from analogue to digital form, a storing means for receiving the digital video signal from the input means and for storing the video signal, a first output means for receiving the digital video signal from the input means or the storing means, and for converting the digital video signal to analogue form for outputting to an analogue video signal receiver, a second output means for receiving a frame of the video signal in digital form for outputting to a printer for printing the frame, and a control means for controlling the operation of the apparatus, wherein the storing means comprises a dynamic random access memory having a memory architecture such that there is a different number of storage locations per line in the storage means than there are pixels per line in the video signal, a pair of input buffer means being provided for storing respective alternate video pixels for providing time to allow a row address of the dynamic random access memory to be changed during the middle of a line of video pixels, the video pixels being alternately written to the dynamic random access memory from the respective input buffer means, and a pair of output buffer means into which alternate video pixels are written from the dynamic random access memory for transmission to the first or second output means.
Preferably, each buffer means comprises a latch.
In one embodiment of the invention a clock signal generating means is provided for generating clock signals for controlling reading and writing between the dynamic random access memory and the respective input and output buffer means, the clock signals outputted by the clock signal generating means being derived from a clock signal in the analogue video signal.
In another embodiment of the invention a plurality of dynamic random access memories are provided, each dynamic random access memory comprising a memory architecture of 256Kbytes x 16.
In a further embodiment of the invention a video address generating means is provided for generating frame and store addresses in the dynamic random access memory at which video pixels from the input means are stored or from which the video pixels are retrieved.
In a further embodiment of the invention a refresh address generating means is provided for generating frame, store and row addresses at which refresh is to occur.
The invention will be more clearly understood from the following description of a preferred embodiment thereof which is given by way of example only with reference to the accompanying drawings, in which:
Fig. 1 is a block representation of apparatus according to the invention for capturing a frame of video data and for presenting the frame of video data in a form for sending to a printer, and Fig. 2 is a block representation of a detail of the apparatus of Fig. 1.
Referring to the drawings there is illustrated apparatus according to the invention, which is indicated generally by the reference numeral 1 for capturing a frame of video data and for presenting the frame of video data in a form for sending to a printer (not shown). The apparatus 1 comprises an input means, namely, an input unit 2 having an input terminal 3 for continuously receiving an analogue video signal of the video data. The input unit 2 comprises a digital to analogue converter (not shown) for converting the analogue video signal into digital form. Outputs 4 from the input unit 2 continuously output the video signal in digital form. A storing means, namely, a storing unit 5 which is described in detail below with reference to Fig. 2 receives and stores the video signal one frame at a time in digital form. A first output means, namely, a first output unit 6 continuously receives the video signal in digital form from the input unit 3 or from the storing unit 5 on inputs 7. The first output unit 6 comprises a digital to analogue converter (not shown) for converting the video signal in digital form into analogue form and for outputting the analogue form of the signal on an output 8 for transmission to an analogue video signal receiver, for example, a visual display unit, television monitor, or the like, none of which are shown. A second output unit 10 receives a stored frame of the video signal from the storing unit 5 for relay to a printer (not shown) in digital form on an output 11.
A control means, in this case a microprocessor 12 controls the operation of the apparatus 1, and in response to an external signal causes the storing unit 5 to output a stored frame of the video signal to the second output unit 10 for relay to the printer. Typically, the video signal is routed through the storing unit 5 from the input unit 2 to the first output unit 6, and the video signal from the first output unit 6 is displayed on a video display unit. The user may then select any frame being displayed on the video display and on a command to the microprocessor 12, the storing unit 5 downloads the currently stored frame of the video signal to the second output unit 10. Turning now to Fig. 2 the storing unit 5 will now be described in detail. The storing unit 5 comprises a dynamic random access memory (DRAM) 15. In this embodiment of the invention the memory architecture of the DRAM 15 is 256Kbytes x 16. Thus, there are less memory locations per line in the DRAM 15 than there are pixels in a line of a video signal, since in a video signal the number of pixels per line is between 640 and 738. Thus, as the digital video signal is being written into the DRAM 15 the row address must be changed in most if not all of the video lines. In order to facilitate this, the digital video signal from the input unit 2 is written into a pair of input buffers, namely, input latches 16 and 17 in such a way that alternate pixels in the digital video signal are written into the respective input latches 16 and 17. In this way, each pixel in the digital video signal is retained in one of the latches 16 and 17 for twice its normal time. A swapping circuit 20 controls the writing of the alternate pixels into the respective latches 16 and 17 by alternately routing strobe signals to the respective latches 16 and 17. The swapping circuit 20 is controlled by the microprocessor 12, and derives its input signals from the clock signal in the video signal. The pixels in the input latches 16 and 17 are alternately written to the DRAM 15 under the control of the microprocessor 12 and clock signals from the swapping circuit 20. The video signal stored in the DRAM 15 is written from the DRAM 15 into output buffers, namely, output latches 22 and 23 in such a way that alternate pixels in the video signal are written into the respective output latches 22 and 23. The pixels are alternately read by the first and second output units 6 and 10 from the output latches 22 and 23 under the control of the microprocessor 12 and under the control of the clock signals from the swapping circuit 20.
Accordingly, by virtue of the fact that each pixel is stored in one of the input latches 16 and 17 for twice the time that it would normally be available to the DRAM 15, sufficient time is left for the DRAM row address to be changed during the middle of a video line. The output latches 22 and 23 likewise provide sufficient time for reading the DRAM row address when the stored signal is being read from the DRAM 15 through the output latches 22 and 23 by either or both of the first and second output units 6 and 10.
A video address generating means is provided by a sub-module (not shown) which operates under the control of the microprocessor 12 for generating the frame store addresses at which the video signal is stored in the DRAM 15 or from which the video signal is retrieved for presentation to either of the first and second output units 6 and 10. A refresh address generating means is also provided by a sub-module (not shown) which operates under the control of the microprocessor 12 for generating the frame store row addresses at which refresh is to occur.
In use, where it is desired to display a video signal directly on a visual display unit (not shown) the video signal under the control of the microprocessor 12 is read by the first output unit 6 directly from the input unit 2, and thus relayed to the video display unit by the first output unit 6. Where it is intended to capture one or more frames of the video signal and print in a printer (not shown), the video signal is routed through the storing unit 5, and is read by the first output unit 6 and is relayed to a video display unit. To capture a frame of the video signal which is displayed on the video display unit a signal is inputted to the apparatus 1, and under the control of the microprocessor 12 the second output unit 10 reads that frame from the DRAM 15 through the output latches 22 and 23, and in turn downloads the frame to the printer.

Claims

1. Apparatus for capturing a frame of video data and presenting the frame of video data in a form for sending to a printer, the apparatus comprising: an input means (2) for receiving an analogue video signal and for converting the video signal from analogue to digital form, a storing means (5) for receiving the digital video signal from the input means (2) and for storing the video signal, a first output means (6) for receiving the digital video signal from the input means (2) or the storing means (5), and for converting the digital video signal to analogue form for outputting to an analogue video signal receiver, a second output means (10) for receiving a frame of the video signal in digital form for outputting to a printer for printing the frame, and a control means (12) for controlling the operation of the apparatus, characterised in that the storing means (5) comprises a dynamic random access memory (5) having a memory architecture such that there is a different number of storage locations per line in the storage means than there are pixels per line in the video signal, a pair of input buffer means (16,17) is provided for temporarily storing respective alternate video pixels received from the input means (2) for providing time to allow a row address of the dynamic random access memory (5) to be changed during the middle of a line of video pixels, the video pixels being alternately written to the dynamic random access memory (5) from the respective input buffer means (16,17), and a pair of output buffer means (22,23) into which alternate video pixels are written from the dynamic random access memory (5) for transmission to the first or second output means (6,10).
2. Apparatus as claimed in Claim 1 characterised in that each buffer means (16,17,22,23) comprises a latch.
3. Apparatus as claimed in Claim 1 or 2 characterised in that a clock signal generating means is provided for generating clock signals for controlling reading and writing between the dynamic random access memory (5) and the respective input and output buffer means (16,17,22,23), the clock signals outputted by the clock signal generating means being derived from a clock signal in the analogue video signal.
4. Apparatus as claimed in any preceding claim characterised in that a plurality of dynamic random access memories (5) are provided, each dynamic random access memory (5) comprising a memory architecture of 256Kbytes x 16.
5. Apparatus as claimed in any preceding claim characterised in that a video address generating means is provided for generating frame and store addresses in the dynamic random access memory (5) at which video pixels from the input means (2) are stored or from which the video pixels are retrieved.
6. Apparatus as claimed in any preceding claim characterised in that a refresh address generating means is provided for generating frame, store and row addresses at which refresh is to occur.
PCT/IE1997/000072 1996-11-06 1997-11-04 Apparatus for capturing a frame of video data for sending to a printer WO1998020671A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU52342/98A AU5234298A (en) 1996-11-06 1997-11-04 Apparatus for capturing a frame of video data for sending to a printer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IES960777 IES72079B2 (en) 1996-11-06 1996-11-06 Apparatus for capturing a frame of video data for sending to a printer
IES960777 1996-11-06

Publications (1)

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WO1998020671A1 true WO1998020671A1 (en) 1998-05-14

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IE (1) IES72079B2 (en)
WO (1) WO1998020671A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0675634A2 (en) * 1994-04-01 1995-10-04 Xerox Corporation System for transferring digital data between an image input terminal and a host terminal
DE19511413A1 (en) * 1994-03-29 1995-10-05 Mitsubishi Electric Corp Image processing system for use in digital copier, scanner, printer, display

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19511413A1 (en) * 1994-03-29 1995-10-05 Mitsubishi Electric Corp Image processing system for use in digital copier, scanner, printer, display
EP0675634A2 (en) * 1994-04-01 1995-10-04 Xerox Corporation System for transferring digital data between an image input terminal and a host terminal

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Publication number Publication date
AU5234298A (en) 1998-05-29
IES72079B2 (en) 1997-03-12

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