WO1998019464A1

WO1998019464A1 - System using signal processor for vtr

Info

Publication number: WO1998019464A1
Application number: PCT/JP1996/003144
Authority: WO
Inventors: Makoto Furihata; Kenya Yamauchi
Original assignee: Hitachi, Ltd.; Hitachi Tohbu Semiconductor, Ltd.
Priority date: 1996-10-28
Filing date: 1996-10-28
Publication date: 1998-05-07

Abstract

In a VTR system, a first frequency converting circuit converts a first reproduced color-under signal of the PAL format into a first standard color signal, a delay circuit generates a second color-under signal by delaying the first color-under signal by one horizontal period, a second frequency converting circuit converts the second color-under signal into a second standard color signal, an oscillation circuit generates a frequency signal of a frequency which is 2n times as high as the carrier frequency required for the above-mentioned frequency conversion, the frequency of the frequency signal is divided into the carrier frequency, four carriers having 0°, 90°, 180°, and 270° phases are generated, one of the carriers is selected so that the phases of the crosstalks contained in the first and second standard color signals may be the same or opposite to each other, the phase of the first or second standard color signal is inverted by a phase-axis inverting circuit, and the first standard color signal is subtracted from the second one or added to the second one so as to offset the color crosstalks.

Description

Details

Technical field using VTR signal processor

The present invention relates to a system using a signal processing device for a VTR (Video's Tape Recorder, the same applies hereinafter). The present invention relates to a playback underlay signal of a PAL format by a VHS system, an S-VHS system or an 8 mm system. It relates to technology that is effective when used in frequency conversion technology for converting to standard power signals. Background art

In a home VTR system, color video signals are recorded using the power-under method. In this color-under method, the luminance signal is frequency-modulated, and the color signal is frequency-converted to a lower frequency band than the frequency-modulated luminance signal, and recorded on the inclined track of the magnetic tape by the rotating video head. .

Recent VTR systems use a guard-bandless method to increase the density, and it is essential to eliminate the crosstalk caused by this. This crosstalk elimination is performed by applying an azimuth angle to the video head.The effect of the azimuth angle is effective for high-frequency signals, but is effective for low-frequency signals. Less effective. That is, the azimuth angle has little effect of removing crosstalk for a single signal, and a method such as a phase shift method (PS method) or a phase invert method (PI method) is adopted.

VH S Method This is explained using NTSC format. The video recording track is recorded by alternately repeating two channels, channel 1 and channel 2. In the VHS NTSC format, the color under frequency is 40 times the horizontal scanning frequency (40 fH). Therefore, the subcarrier frequency of 3.57955 5 MHz of the standard color signal is converted into a frequency of 40 fH and approximately 629 KHz and recorded. At this time, the phase is changed every one horizontal period. Channel 1 advances by 90 ° and channel 2 delays by 90 °. This is because when the signal of 629 KHz is converted back to 3.5795 45 MHz (and the phase is also restored) during playback, a delay element for one horizontal period is used to delay the signal. This is because the cross component can be removed by adding the color signal delayed by one horizontal period using the color signal and the delay element. Examples of the above-described frequency conversion technology include Japanese Patent Application Laid-Open No. 63-257394, and Japanese Utility Model Application Laid-Open No. Heisei 2-519489.

The PAL system is an improvement over the NTSC system in terms of non-linearity of the transmission system, so that image quality degradation is reduced. In the PAL system, (R−Y) and (B−Y) are used as color difference signals. The color subcarrier is carrier-suppressed and amplitude-modulated by the color difference signal, but the phase of the subcarrier of the (R-Y) signal is inverted by 180 ° for each scanning line. The color burst phase also switches between +135 degrees and -135 degrees for each scan line.

In the VSH PAL format, the color under frequency is 40.125 times the horizontal scanning frequency (40.125 fH). Therefore, the power required to convert the subcarrier frequency of the standard color signal from 4.4.33.19 MHz to 40.125 fH (approximately 627 KHz) and record it \ At this time, the phase is not shifted in channel 1 for each horizontal period (scanning line), but is delayed by 90 ° in channel 2. In order to remove the crosstalk in the reproduced color under signal of the PAL format, a delay element (CCD) for two horizontal periods is used as shown in FIG. By calculating the color signal delayed by two horizontal periods using the signal and the delay element, the crosstalk component is calculated as shown in the phase shift diagram shown in Fig. 13 (B) and the phase shift diagram shown in Fig. 13. Removal is in progress.

In other words, in the PAL format, as shown in FIGS. 12 (B) and 13, the frequency conversion section (Main Conv.) Is used for channel 1 (CH 1) and channel 2 (CH 2). The signal (c) = (a) + (b), which is the sum of the signal (b) obtained by delaying the output signal (a) by 2H and the signal (a) converted 2H later, is The crosstalk components indicated by the dotted lines in the signals (a) and (b) have phases opposite to each other, and can be canceled by the above addition.

As described above, since the PAL format uses a delay signal of two horizontal periods, a mode in which a head is mounted at the time of transition to special playback (at the time of transition to a mode such as search or still). The response of the evening (cylinder motor) takes time, causing the color signal to disappear instantaneously and the color to disappear. This is because the CCD (Charge Transfer Device), which forms the delay signal for the two horizontal periods, uses the signal of the crystal oscillator as the clock, and has a fixed amount, and the horizontal level changes according to the change in the motor rotation speed. This is because the relative deviation from time increases. In particular, in the case of using a two-horizontal delay signal such as the PAL format, as shown in Fig. 14 (A), in the case of normal reproduction, the reproduced color under signal is delayed by two horizontal periods. 40. 1 25 f HX 2 = 80. 25 f H, i.e. becomes遲延of 80.25 cycles, a delay of 90 ° with respect to the delay before the signal (in the case of channel 1). However, as shown in Fig. 14 (B), the response of the head mounted cylinder motor is slow during transition to special playback such as search and still, and the signal to be played back may be extended or shrunk in time. Yes (during special playback, the rotation of the cylinder motor is compensated so that the horizontal frequency becomes normal). In this case, since the delay of the two horizontal periods is fixed by the clock of the crystal oscillator, the phase may be inverted with respect to the normal phase. If the phase is inverted as described above, the signal component is canceled by the above addition, and the color component disappears.

In addition to the above-mentioned special reproduction, the PAL format uses a signal delayed by two horizontal periods as described above. Since the television receiver performs interlaced scanning (interlaced scanning), the signal 2H before is essentially the video signal of the scanning line 4 lines before. Therefore, in a video in which the condition that the scanning line signal, which is the premise of the crosstalk principle, is not satisfied, does not hold, the signal delayed by two horizontal periods as described above is added to form a color signal. However, there is a problem that the correspondence with the luminance signal is displaced and the image is double-viewed. For example, if a video with a pattern consisting of a large number of colored points, such as a fireworks display, is recorded and played back, the above-mentioned problems will become prominent.

As described above, the NTSC format uses a delay of one horizontal period, and the PAL format requires a delay of two horizontal periods. By switching each frequency, the above NTSC system and PAL system can perform frequency conversion with substantially the same circuit. However, since the delay time of the delay circuit for removing crosstalk is different as described above, each delay circuit must be prepared, which increases the set price of the VTR system. For example, in a set of VTR systems that can be applied to both NTSC and PAL systems, such as VTRs for Latin America, 2 Different types of delay circuits are required, which increases the set price. In addition, if a delay circuit such as the CCD described above is to be incorporated in an LSI for signal processing, the difference in the delay time is a major bottleneck.

Therefore, the present invention provides a VTR signal processing device that enables reproduction frequency conversion of a PAL-formatted color under signal by removing a color crosstalk using a one horizontal period delay circuit. The purpose is to provide the system used. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

According to the present invention, a first reproduced color under signal of a PAL format is converted into a first standard color signal by a first frequency conversion circuit, and the first reproduced color under signal is delayed by one horizontal period by a delay circuit. Then, the signal is converted into a second standard power signal by a second frequency conversion circuit as a second power line under signal, and 2 n times the carrier frequency required for the above frequency conversion operation by an oscillation circuit. A frequency signal is formed, and this frequency signal is divided into the carrier frequency, and a four-phase carrier having a phase of 0 °, 90 °, 180 °, and 270 ° is formed. The above four-phase carrier is selected so that the power crosstalk included in the first and second standard power signals becomes in-phase or out-of-phase, and the phase of the first or second standard color signal is selected. To the phase axis inversion circuit And by, by subtracting or adding the two standard force La first signal to cancel the force La first cross-talk by the calculation circuit. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a block diagram showing an embodiment of a frequency converter included in a VTR signal processing device used in the present invention.

FIG. 2 is a main block diagram showing another embodiment of the frequency converter included in the VTR signal processing device used in the present invention.

FIG. 3 is a schematic configuration diagram showing one embodiment of an arithmetic circuit provided in a VTR signal processing circuit used in the present invention.

FIG. 4 is a circuit diagram showing one embodiment of a frequency dividing circuit provided in the VTR signal processing circuit used in the present invention.

FIG. 5 is a waveform diagram for explaining the operation of the frequency dividing circuit, and FIG. 6 is a schematic configuration diagram for explaining a phase inverting circuit provided in the VTR signal processing circuit used in the present invention. And

FIG. 7 is a schematic block diagram for explaining the present invention, and FIG. 8 is a phase shift diagram corresponding to one channel for explaining the operation of the VTR signal processing circuit used in the present invention. ,

FIG. 9 is a phase shift diagram corresponding to two channels for explaining the operation of the VTR signal processing circuit used in the present invention.

FIG. 10 is a main block diagram showing another embodiment of the frequency converter included in the VTR signal processing device used in the present invention.

FIG. 11 is a block diagram showing an embodiment of a VTR system using the VTR signal processing device according to the present invention.

FIG. 12 is a block diagram for explaining conventional VTR signal processing for the PAL format.

FIG. 13 is a phase shift diagram for explaining a signal processing operation for a VTR for a conventional PAL format.

FIG. 14 is a schematic waveform diagram for explaining a conventional VAL signal processing operation for the PAL format. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a block diagram of an embodiment of a frequency conversion unit in a VTR signal processing device used in the present invention. The circuit block shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique together with other circuit blocks constituting a VTR signal processing circuit.

In the figure, reference numeral 1 denotes a low-pass filter (LPF) for extracting a color signal from a reproduced video signal. The low-pass filter 1 reproduces signals from the two magnetic heads (channel 1 and channel 2) provided on the rotating head mounted on the cylinder motor by the amplifier circuit AMP. Is supplied.

Reference numeral 2 denotes a delay circuit for one horizontal period. The delay circuit 2 is not particularly limited, but may include a CCD (charge transfer device), an input section for analog / digital conversion, a shift device for delaying the input section, and an analog signal for converting the shifted digital signal. It may be composed of a digital Z-analog conversion circuit for returning to a signal. 4 is a second frequency conversion circuit that converts a delayed under color signal into a standard color frequency, a so-called main converter. 3 is a first frequency conversion circuit that converts a color signal before delay into a standard color frequency. Circuit. Reference numeral 5 denotes a phase axis inverting circuit for inverting the phase axis of the standard color frequency signal converted by the main converter 4. The output signal (B signal) of the phase axis inverting circuit and the output signal (A signal) of the second frequency conversion circuit 3 are supplied to the arithmetic circuit 6 to remove the crosstalk. Then, the standard force signal is output through the band pass filter (BPF) 7.

The reproduction color under signal from the amplifier AMP includes a luminance signal and color Although the signal is included, only the color signal which is separated from the luminance signal by the above-mentioned one-pass filter 1 and frequency-converted to a low frequency is extracted. The one color under signal is delayed by 1 H by the delay circuit 2 which is a delay circuit on one side as described above, and though not shown, passes through a gain control circuit (GCA) and the second frequency conversion circuit (GCA). Ma in Conv 2) Guided to 2 inputs. The reproduced color under signal passed through the low-pass filter 1 is directly guided to the first frequency conversion circuit (Main Conve 1) 3.

The signal converted to the standard frequency signal by the first and second frequency conversion circuits 3 and 4 as described above is applied to an arithmetic circuit 6 for removing crosstalk. Here, by further providing the bandpass filter (BPF) 7, unnecessary frequency components generated by the first and second frequency conversion circuits 3 and 4 and the phase axis inversion circuit 6 can be removed, and It is intended to obtain a proper standard force signal.

The frequency conversion subcarrier is not particularly limited, but is twice as large as the subcarrier, that is, in the PAL format, an oscillation circuit oscillating at approximately 5.06 MHz X 2-10.2 MHz. fc VCO) The output signal of 8 is obtained by dividing the output signal by 1Z2 by the divider circuit 9 and the corresponding second and first frequency converters are passed through the 4-phase SW (switch) 11 and 12 which are the switching circuit Added to circuits 4 and 3.

The reproduction power under signal input to the first frequency conversion circuit 3 and the reproduction color under signal delayed by 1 H input to the second frequency conversion circuit 4 have the same amplitude level. Input to demodulation circuit. In these demodulation circuits, a baseband demodulated signal can be obtained by using subcarriers that are frequency-synchronized with the burst signal of the reproduced color signal. Arithmetic operation to obtain the demodulated baseband amplitude difference After passing through the circuit, it is converted to a DC voltage by a single-pass filter, and the gain control circuit (GCA) is controlled, so that the reproduced color under signal input to the first frequency conversion circuit 3 and the second frequency conversion The input amplitude of the reproduced color under signal delayed by 1 H input to the circuit 4 is made equal. In particular, when a CCD is used as the delay circuit, the voltage signal is converted into a charge signal and returned to a voltage signal again, and the level change there is relatively large. Is required.

Such a two-frequency conversion circuit and a signal processing circuit for VTR having the above-mentioned level adjustment function have been previously proposed by the applicant of the present invention in Japanese Patent Application Laid-Open No. Hei 7-99671. Technology is used.

The oscillation circuit 8 is an oscillator that oscillates at a frequency of 2 n X fc (fc is a subcarrier frequency) for generating a subcarrier for frequency conversion. The frequency divider circuit 12 is not particularly limited, but as described later, At the same time as dividing the frequency of 11 into the frequency of the subcarrier, it is 0 °, 90 °, and 180 °. , And 270 ° four-phase subcarriers are generated. In other words, the oscillation circuit 8 only needs to be 2 n (n is a natural number) of the subcarrier ίc, and divides the frequency dividing circuit by 1/2 n, and sets 0 as described above. , 90 °, 180 °, and 270 ° should be formed.

A crystal oscillation circuit 12 is provided for the operation of the phase axis inverting circuit. The crystal oscillation circuit 12 oscillates at the reference frequency fsc2 of the reproduction standard color signal. Based on this reference frequency signal, the reproduction power signal is frequency- and phase-locked so as to be the standard power signal frequency. The reference frequency signal obtained from the crystal oscillator circuit 12 is doubled in frequency by a doubler circuit 13 and applied to a phase axis inverting circuit 5. Fig. 2 shows the frequency conversion of the VTR signal processing circuit used in the present invention. A block diagram of one embodiment of the unit is shown. In this embodiment, a control circuit of the oscillation circuit (2 fc VCO) 8 is shown.

The oscillation circuit 8 is composed of a voltage-controlled oscillator (VCO) and is not particularly limited, but has a free-run frequency almost corresponding to a frequency 2 (fsc + 40.125H) twice as high as the carrier signal fc. To be. The output of the oscillating circuit 8 is frequency-divided by 1/2 by the frequency dividing circuit 9 to form a 4-phase signal.

The frequency dividing and phase shifting operations are performed by the frequency dividing circuit 9, and the four carrier signals (5.0 6 MHz) are controlled by switch circuits 11 and 10, which are switch-controlled by a head switching signal and a horizontal synchronizing signal. One is selected by a rule to be supplied to the frequency conversion circuits 4 and 3. The frequency conversion circuits 4 and 3 use the 5.0 MHz carrier signal

The signal is synthesized with a reproduced color under signal of 627 KHz, and the frequency is converted to about 4.433 MHz corresponding to the difference. A color subcarrier component is extracted from the band-converted color signal through the band pass 14 and supplied to one input of the phase detection circuit 15.

The other input of the phase detection circuit 15 is supplied with a 4.433 MHz reference frequency signal formed by the crystal oscillation circuit 12. The phase detection circuit 15 performs a phase comparison operation of the two signals, and forms a detection signal corresponding to the phase difference (frequency difference). This phase detection output is converted to a direct current by an APC filter (one-pass filter) 16 and the oscillation circuit (V

CO) forms a control voltage of 8. With such a PLL loop, an oscillation signal of 2 × (fsc + 40.125 fH) accurately synchronized with the reference frequency signal generated by the crystal oscillation circuit 12 can be formed.

FIG. 3 shows a schematic configuration diagram of an embodiment of the arithmetic circuit 6 for removing the color crosstalk. In the same figure (A), the first and second The case where the A signal and the B signal output from the wave number conversion circuits 3 and 4 have the same phase is shown. In the phase axis inverting circuit 5, the color signal is converted into the components of fsc and 3 fsc by the carrier of 2 fsc, and the phase of the fsc component is inverted, and at the same time, the signal level is halved. For this reason, the arithmetic circuit 6 amplifies the level of the B signal obtained from the output of the phase axis inverting circuit 5 by twice (+6 dB), and the A signal obtained from the output of the frequency converting circuit 3 to add. Thereby, the crosstalk component of the opposite phase is removed. FIG. 3B shows a case where the A signal and the B signal output from the first and second frequency conversion circuits 3 and 4 have opposite phases. Similarly to the above, the phase of the fsc component is inverted by the phase axis inverting circuit 5, and at the same time, the signal level is halved. Therefore, the level of the B signal is doubled (+6 dB). By subtracting the A signal obtained from the output of the frequency conversion circuit 3, the cross-talk component having the opposite phase is removed.

FIG. 4 shows a specific circuit diagram of one embodiment of the frequency divider 9 for forming the 1Z2 frequency dividing operation and the four-phase signal. In this embodiment, the two through latch circuits FF 1 and FF 2 having the ECL configuration are used to perform a 1/2 frequency dividing operation and generate a four-phase output signal.

Transistors Q 6 and Q 7 whose collector and base are cross-connected form a latch circuit. Human differential transistors Q5 and Q8 are provided in which the collectors and collectors of these differential transistors Q6 and Q7 are connected in common. Load resistances Rl and R2 are provided in the above-mentioned common collector, respectively. The common emitter of each of the latch type differential transistors Q 6 and Q 7 and the input differential transistors Q 5 and Q 8 has a constant current source I 0 via a differential transistor Q 1 and Q 2. Is provided. Such a circuit constitutes the first through latch circuit FF1.

Similar to the first through latch circuit FF1, the latch type differential P TJP9 144 Transistors Q10, Q11, input differential transistors Q9, Q12, collector Load resistors R3, R4 and constant current source I0 and their switching differential transistors Q3, Q4 Thus, a second through latch circuit FF2 is formed. The bases of the input differential transistors Q5, Q8, Q9, and Q12 of these two through latch circuits FF1 and FF2 are supplied with the output signals of the other through latch circuits FF2 and FF1 in an intersecting manner. You. The input signals to be frequency-divided are input to the bases of the differential transistors Q and Q2, Q3, and Q4 that perform the current switching operation so that the phases of the divided input signals are opposite to each other.

That is, the input terminal IN 1 is connected to the base of the transistor Q 1 that performs the through input operation to the first through latch circuit FF 1, and performs the latch operation to the second through latch circuit FF 2 Connected Transistor Q Connected to base of Q3. The input terminal IN2 is connected to the base of a transistor Q2 that performs a latch operation on the first through latch circuit FF1, and a transistor that performs a single input operation on the second through latch circuit FF2 Connected to Q4 base.

The input signals to be divided are supplied to the input terminals IN 1 and IN 2. When the oscillation output signal is in the double-ended output mode, input signals having phases opposite to each other are supplied to the input terminals IN 1 and IN 2 .When the oscillation output signal is in the single-ended output mode, the input terminal IN 1 (or IN 2) is supplied with the oscillation output, and the input terminal IN 2 (or IN 1) is supplied with the midpoint potential of the oscillation output signal.

In this embodiment, the four signals formed by the load resistors R1 to R4 provided in the two through latch circuits FF1 and FF2 are four-phase signals having a phase difference of 90 ° from each other. It is output through an emitter follower circuit consisting of 13 to Q16 and a constant current source Io. In the same figure, the circuit symbol I 0 of the constant current source has a limited meaning that the same constant current flows. Note that it represents a constant current source, not a TJ flavor. The operation of the frequency divider 9 will be described with reference to the operation waveform diagram shown in FIG. In the figure, a single-ended oscillation signal is supplied to an input terminal IN1, and a midpoint potential is supplied to an input terminal IN2 as a reference voltage. Transistors Q2 and Q4 are turned on during the period when the oscillation signal supplied to input terminal IN1 is at the level of the reference midpoint voltage. In the first through-latch circuit FF1, the constant current of the constant current source I0 flows through the latch-type differential transistors Q6 and Q7 due to the ON state of the transistor Q2, and the input signal captured before that time. Holding. For example, if the transistor Q6 is on, a constant current flows through the load resistor R1, and the corresponding output terminal OUT4 goes low. When the transistor Q7 is off, the corresponding output terminal OUT1 is at a high level. By the ON state of the transistor Q4, the input differential transistors Q9 and Q12 are activated in the second through latch circuit FF2. As described above, the input transistor Q9 that receives the high-level output signal corresponding to the off state of the transistor Q7 of the first through latch circuit FF1 is turned on, and corresponds to the on state of the transistor Q6. The input transistor Q12 that receives the low-level output signal is off. As a result, a constant current flows through the load resistor R3, and a low-level output signal is formed. Since a constant current does not flow through the load resistor R4, a high level such as the power supply voltage Vcc is formed. Therefore, the output signal of the output terminal OUT 2 is at the mouth level, and the output terminal OUT 3 is at the high level.

When the oscillation signal supplied to input terminal IN1 changes to a high level with respect to the reference midpoint voltage, transistors Q2 and Q4 are turned off, and transistors Q1 and Q3 are turned on. Due to the ON state of the transistor Q3, the difference between the latch forms in the second through latch circuit FF2 The constant current of the constant current source I 0 flows through the active transistors Q 10 and Q 11, and the input signal acquired before that is held. That is, the transistor Q10 is turned on in accordance with the on state of the input transistor Q9, and the transistor Q11 is turned off in accordance with the off state of the input transistor Q12. As a result, the output terminal OUT2 is maintained at the low level, and the output terminal OUT3 is maintained at the high level.

By the ON state of the transistor Q1, the input differential transistors Q5 and Q6 are activated in the first through latch circuit FF1. As described above, in the second through-latch circuit FF2, the input transistor Q8 receiving the high-level output signal corresponding to the off state of the transistor Q11 is turned on, and corresponds to the on state of the transistor Q10. The input transistor Q5 that receives the output signal of the closed mouth level is turned off. As a result, a constant current flows through the load resistor R2 instead of the load resistor R1, and the above holding signal is inverted. That is, the output signal of the output terminal OUT4 changes from the low level to the high level, and the output terminal OUT1 changes from the high level to the low level.

When the oscillation signal supplied to the input terminal IN1 changes to low level again with respect to the reference midpoint voltage, the transistors Q1 and Q3 are turned off and the transistors Q2 and Q4 are turned on. By the ON state of the transistor Q2, in the first through latch circuit FF1, the constant current of the constant current source I0 flows through the latch-type differential transistors Q6 and Q7, and the input signal captured before that is input. Hold. That is, the transistor Q7 is latched on according to the on state of the input transistor Q8, and the transistor Q6 is latched off according to the off state of the human transistor Q5. As a result, the output terminal OUT4 is maintained at the low level, and the output terminal OUT1 is maintained at the high level. By the ON state of the transistor Q3, in the second through latch circuit FF2, the input differential transistors Q9 and Q10 are brought into an operating state. As described above, in the first through latch circuit FF1, the input transistor Q12 that receives the high-level output signal corresponding to the off state of the transistor Q6 is turned on, and the transistor Q7 is turned on. The input transistor Q9 that receives the output signal of the mouth level is turned off. As a result, a constant current flows through the load resistor R4 instead of the load resistor R3, and the above holding signal is inverted. That is, the output signal of the output terminal OUT2 changes from low level to high level, and the output terminal OUT3 changes from high level to low level.

Hereinafter, by repeating the same operation, it is possible to form the output signals OUTl to OUT4 having a period twice as long as the oscillation frequency of the input signal IN1, that is, 1Z2 frequency-divided. Also, as is clear from the figure, when the four output signals of the two through latch circuits FF 1 and FF 2 rise, the phase of OUT 2 is delayed by 90 ° with respect to OUT 4, and this OUT 2 The phase of OUT1 is delayed by 90 ° with respect to this, and the phase of OUT3 is 90 with respect to OUT1. Four output signals that are delayed can be formed. By using a frequency dividing circuit composed of a through latch circuit having such an ECL configuration, it is possible to realize a multifunction circuit having both a frequency dividing operation and a phase shift operation with a simple configuration.

Four signals with phases delayed by 90 ° can be formed by the frequency divider circuit as described above, and the signals can be selectively converted to two frequency conversion circuits 3 according to the input reproduction color under signal. 4, the output signals A and B can be phase-adjusted. Therefore, the color axis under signal of the PAL format also uses the above-described 1H delay signal and the phase axis described below. The above arithmetic circuit 5 enables the removal of the crosstalk component.

FIG. 6 (A) shows a schematic configuration diagram of an embodiment of the phase axis inverting circuit used in the present invention. In this embodiment, a known multiplication circuit is used. That is, the reproduced color signal converted to the standard color frequency ίc by the second frequency conversion circuit 4 is input to one input of the multiplication circuit, and the crystal input is input to the other input of the multiplication circuit. A signal obtained by multiplying the reference frequency signal of the standard color signal formed by the oscillator circuit 12 by the doubler circuit 13 is supplied.

The reproduced color signal converted to the standard frequency f c by the second frequency conversion circuit 4 can be described as Axs in (f c + ø). Here, A represents the amplitude of the color signal, that is, the color saturation (color density), and ø represents the phase of the color signal, that is, the hue. Since the signal of 2fc obtained from the above-mentioned double multiplier 13 is a continuous wave, it can be expressed as sin (2fc).

When the above two signals are multiplied by a multiplication circuit, the output signal Vout can be expressed by the following equation (1).

Vout = As i n (f c + 0) xs i n (2 f c)

= -A / 2 {s in (3 f c + ø) -s in (f c-ø)}

(1) The output signal Vout has a 3 fc component and a: fc component. Looking at the fc component, it is — lZ2xAs in (fc— ø). Compared with the input color signal A xs in (fc + 0), the amplitude is attenuated to 1Z2, and the phase component is changed from plus to minus. It turns out that it is reversed. This characteristic is the function of the phase axis inversion circuit 5. Here, the remaining 3 fc component is not considered because it is removed by the band-pass filter 7 after the calculation. FIG. 6 (B) is a vector diagram for explaining the signal conversion characteristics of the phase axis conversion circuit 5. In other words, in the vector diagram at the frequency fsc, if the above conversion characteristics are expressed, for the input reproduction color signal As in (fc + ø), the signal of 2 fc will be on one axis (horizontal axis in the figure). expressed. Then, with respect to this horizontal axis, a signal whose phase component is inverted and whose signal level is attenuated to 1Z2 is obtained as an output signal 1Z2XAS in (fsc-ø).

FIG. 7 is a block diagram for explaining the principle of frequency conversion in the VHS PAL format. In the figure, for the understanding of the invention, (A) shows a conventional frequency conversion method, and (B) shows the method of the present application.

In other words, in the case of using the conventional one frequency conversion circuit shown in (A), the subcarrier 1 as described later is input to the frequency conversion circuit (Main Conv) to obtain the standard color signal (a). Yes, in order to remove color crosstalk in PAL format, extra signal components are removed by a bandpass filter, and a two-horizontal period is delayed by a glass delay line or CCD. The output of the evening is added.

In the method of the present invention (B), two frequency conversion circuits (Main Conv 1 and 2) are used as described above, and the reproduction color under signal is delayed by one horizontal period despite the PAL format. The signal delayed by the CCD (CCD) is supplied to one frequency conversion circuit (Main Conv 2), and the subcarriers that have been phase-shifted in four ways as described above are those that have a phase relationship as described later. And supplies it to the above two frequency conversion circuits (Main Conv. 1 and 2) to perform phase control of the frequency-converted standard color signals (b) and (c) in each of them, and to output a standard color signal ( c ), The signal level is inverted by the above-mentioned phase axis inverting circuit, the signal level of the inverted signal is doubled, added to the above signal (b) by the adding circuit, and the color crosstalk is removed. is there.

FIG. 8 is a phase shift diagram corresponding to channel 1 for explaining the frequency conversion operation according to the method of the present invention. In the figure, the solid vector represents the signal component, and the dotted vector represents the crosstalk component. The short vector represents the burst signal, and the long vector represents the chroma signal. In the figure, in order to understand the present invention, in other words, in order to understand the phase shift in the PAL format, in FIG. 7A, the standard color signal in the conventional method shown in FIG. 7A is used. Is shown.

As is well known, in the PAL color signal, a burst signal and a chrominance signal, which are phase-shifted by ± 45 degrees every one horizontal period, alternate around the B-Y axis. For this reason, as shown in (a), the phase of the subcarrier 1 is selected so that the frequency-converted signal alternates. That is, in the channel 1 in the figure, there is no phase shift at the time of recording, and in the channel 2 shown in FIG. 9 described below, the phase is delayed by 90 ° every one horizontal period. The subcarrier phase is selected by the four-phase switch so that is canceled.

FIGS. 8 (b), (c), (d) and (e) show the phases of the respective parts at the time of frequency conversion and crosstalk removal according to the method of the present invention. (B) shows a color phase in which the reproduced color under signal is converted into a standard color frequency signal by the frequency conversion circuit 3. Here, when compared with the conventional color phase (a), they are 0 °, 90 ° (advancing 90 °), 0 °, and 190 ° every horizontal period. (C) is a signal (1 HDL) obtained by delaying the reproduced color under signal by one horizontal period, and standardized by the frequency conversion circuit 4 above. The color phase converted to the color frequency is shown. Here, when compared with the conventional color phase (a) before one horizontal period delay, +90 for each horizontal period. (90 ° delay), 0 °, + 90 °, 0 °.

The color signal of (c) is inverted by the B-Y axis by the phase axis inversion circuit 5, and the signal level is doubled (d). The phase of the color crosstalk component included in the color signal of (d) is opposite in phase to the color crosstalk component of (b) obtained from the frequency conversion circuit 3, and the level is also equal. . Therefore, when the two are added by the arithmetic circuit 6, the color crosstalk is canceled as shown in (e), and the first signal component is obtained in a vector-added form.

Comparing the color signal components of (a) and (e) above, (e) leads 45 ° both the burst signal and the chroma signal to (a), but the phase of the burst signal and the chroma signal It can be seen that the relationship is maintained and that the alternation characteristics are also maintained.

FIG. 9 shows a phase shift diagram corresponding to channel 2 for explaining the frequency conversion operation according to the method of the present invention. In the same way as above, in order to understand the phase shift in the PAL format, (a) shows the standard color signal in the conventional system of FIG. 7 (A).

Fig. 9 (b), (c), (d) and (e) show the phase of each part at the time of frequency conversion and crosstalk removal according to the method of the present invention, similarly to the above. That is, (b) shows the color phase obtained by converting the reproduced color under signal into the standard color single frequency signal by the frequency conversion circuit 3. here

Compared with the conventional color phase (a), they are set to —90 ° (90 ° advance), 0 °, —90 °, 0 ° every horizontal period. (C) shows a color phase obtained by delaying the reproduced color standard signal by one horizontal period (1 HDL) and then converting the signal to the standard frequency by the frequency conversion circuit 4. Here, in comparison with the conventional color phase (a) before one horizontal period delay, + 0 °, + 90 ° (90. delay), 0 every one horizontal period. , +90. It is.

(D) is that the color signal of (c) is inverted by the B-Y axis by the phase axis inverting circuit 5 and the signal level is doubled. The phase of the color crosstalk component included in the color signal of (d) is opposite in phase to the color crosstalk component of (b) obtained from the frequency conversion circuit 3 and has the same level. Become. Therefore, when the two are added by the arithmetic circuit 6, the color crosstalk is canceled as shown in (e), and the color signal component is obtained in a vector-added form.

Comparing the single signal components of (a) and (e) above, (e) is 45 for both burst and chroma signals for (a). It can be seen that the phase relationship between the burst signal and the chroma signal is maintained, and that the alternating characteristics are also maintained.

As described above, in the present invention, both the channels 1 and 2 perform a frequency conversion operation in which continuity is maintained and adjacent color crosstalk is removed, although the phase is advanced by 45 ° from the conventional reproduced color signal. It can be done.

FIG. 10 is a main block diagram showing another embodiment of the frequency converter included in the VTR signal processing device used in the present invention. In this embodiment, the phase axis inversion circuit 5 is provided on the output side of the first frequency conversion circuit 3. As described above, in this embodiment, two frequency conversion circuits are used, the relative phase shift control thereof is combined with the phase inversion operation by the phase axis inversion circuit, and the color crosstalk component is reduced as in the above embodiment. You should choose something that will be removed (reverse or in-phase). In other words, if the color crosstalk is in opposite phase, The arithmetic circuit adds and cancels, and if the color crosstalk has the same phase, the arithmetic circuit may subtract and cancel. Further, the phase axis inverting circuit may be provided before the frequency converting circuit or before the delay circuit.

FIG. 11 is a block diagram of one embodiment of a VTR system using the VTR signal processing device according to the present invention. The VTR system of this embodiment is roughly divided into a tuner section, a VTR recording Z playback signal processing section, a recording / playback amplifier, a head section, a mechanical section, a system control section, a timer circuit, and operation switches 1 and 2. Consists of Such a rough system configuration is the same as that of a known VTR system, and a detailed description thereof will be omitted.

The VTR signal processing device according to the present invention is provided in the VTR recording / reproducing signal processing unit, and the overall outline thereof is as follows. The following circuit is provided as a luminance system video circuit. The video input is provided to an automatic gain circuit. The video input signal is output as it is as a video output for monitoring through a video output amplifier circuit. On the other hand, the output signal of the automatic gain amplifier is supplied to a low pass filter for luminance. The output signal of this low-pass filter is supplied to the main enhancer through an external capacitor. The output signal of the enhancer is FM-modulated by an FM modulation circuit and transmitted to an external recording pump as a recording FM output. The playback FM input output from the external playback amplifier is supplied to the limiter. The output signal of the limiter is supplied to an FM demodulation circuit to perform FM demodulation. Then, a main de-emphasis process corresponding to the main re-energy is performed by the main re-enhancer.

The luminance signal subjected to the FM demodulation and de-emphasis processing is supplied to a low-pass filter used for color separation. The mixed high frequency components are removed and input to the noise canceller and peak value control. Further, the synchronization signal is separated by the synchronization separation circuit. The output signal of the noise canceller is combined with a color signal reproduced by a power line video circuit by a mixer included in the video output amplifier circuit and output.

The following circuit is provided as a color video signal circuit. The output signal of the automatic gain amplifying circuit of the luminance video circuit is supplied to an auto chroma level controller. The output signal of the auto-chroma level controller is supplied to the band-pass filter. The output signal of this bandpass filter is subjected to low-frequency conversion by a frequency conversion circuit. The frequency-converted color signal is output as a recording signal through a color killer amplifier that also operates as a recording pump.

The reproduced color input is separated from the luminance signal through a low-pass filter and captured. This output signal is subjected to frequency conversion by the above-described frequency conversion unit and removal of the color crosstalk, and is output through the bandpass filter and the noise canceller. The video signal is input through an external capacitor, is combined with the luminance signal by a mixer included in the video output amplifier circuit, and is output.

According to the present invention, in a color-under-type VTR system, a component having a large actual phase area such as a glass delay line or a CCD having a high clock frequency is not used, and a color signal path and a subcarrier path are not used. It is possible to obtain a VTR system that eliminates crosstalk with high accuracy using a low clock frequency or CCD or line memory without adding a phase correction circuit. Also, in the PAL format, since a delay signal of one horizontal period is used, a VTR system in which color crosstalk is eliminated with high accuracy is possible. In other words, the neighbor corresponding to interlaced scanning In the tangential scanning line, the approximation of the signal is maintained because the scanning line is only two lines apart from each other, and the difference between the luminance signal and the chrominance signal is small even in the image such as the fireworks shown above. Can be done. Then, with the development of semiconductor technology, the above-mentioned delay circuit will also enable a VTR system composed of a semiconductor integrated circuit integrally with a VTR signal processing circuit.

The operational effects obtained from the above embodiment are as follows.

(1) The first reproduced color under signal in the PAL format is converted into the first standard color signal by the first frequency conversion circuit, and the first reproduced color under signal is converted into one horizontal period by the delay circuit. The signal is delayed and converted to a second color signal as an under-signal by the second frequency conversion circuit to the second standard power signal, and the oscillation circuit requires 2 n times the carrier frequency required for the frequency conversion operation. The above frequency signal is divided into the above carrier frequency, and a four-phase carrier having phases of 0 °, 90 °, 180 °, and 270 ° is formed. Selection of the four-phase carrier so that the power crosstalk included in the first and second standard force signals is in phase or in opposite phase, and the phase of the first or second standard force signal Is inverted by the phase axis inversion circuit. As a result, an effect is obtained that a VTR system in which the above-mentioned power crosstalk is canceled out by subtracting or adding the two standard power signals by the arithmetic circuit as in the NTSC method. (2) Due to the above (1), the PAL format also uses a delay signal for one horizontal period, so the special playback transition due to the response delay of the head mounted mode is the same as the NTSC format, as in the NTSC format. This has the effect of reducing color erasure at the time of scanning and achieving a VTR system that maintains the approximation of the signal because the scanning line is only two lines apart from each other even in interlaced scanning, and reduces the deviation between the luminance signal and the color signal. can get.

(3) The above oscillation circuit is composed of a voltage controlled oscillation circuit, and a crystal oscillation circuit The phase difference between the reference frequency of the formed standard color signal and the color sub-carrier component extracted from the standard power signal output from the first or second frequency conversion circuit is calculated by a phase detection circuit. Detecting and controlling the oscillation frequency with a control voltage obtained by converting the phase detection output into a direct current, and multiplying the reference frequency signal formed by the crystal oscillation circuit by 2 and supplying the same to the phase axis inversion circuit As a result, it is possible to simplify the circuit for forming the frequency signal for performing the subcarrier and phase axis inversion required for the above-described frequency conversion operation and color crosstalk elimination, and to achieve a VTR system capable of performing high-quality signal processing.

(4) The oscillation circuit outputs an oscillation signal having a carrier frequency that is twice as high as that of the oscillation circuit. The input and output of the two through-latch circuits of the ECL configuration serve as a frequency dividing circuit for dividing the oscillation signal. By cross-connecting the configuration, it is possible to easily obtain the 1Z2 frequency division operation and obtain 4-phase signals that differ by 90 ° from each pair of output terminals of the two through latches. The effect that can be obtained is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, the oscillating circuit 8 may be 2 n times i c and divide it by 1/2 n to form the four-phase subcarrier signal. The delay circuit may comprise a CCD or an analog / digital conversion circuit, a shift register and a digital Z / analog conversion circuit, and may be formed by the same semiconductor integrated circuit device as the VTR signal processing circuit.

Industrial applicability

As described above, the present invention is applied to the VHS system, S-VHS system or 8 mm It can be widely used in systems that use VTR signal processors that support the PAL format.

Claims

The scope of the claims

1. A cylinder motor equipped with a magnetic head,

A VTR signal processing device for processing a signal read from the magnetic head,

The above VTR signal processing device

A first frequency conversion circuit for receiving a first playback color under signal in a PAL format among the signals read from the magnetic head and converting the frequency into a first standard color signal;

A delay circuit for delaying the first reproduced color under signal by one horizontal period;

A second frequency conversion circuit that receives the delay signal of the delay circuit and frequency-converts the signal into a second standard power signal;

An oscillation circuit that forms a frequency signal of 2 n times the carrier frequency required for the frequency conversion operation;

A frequency divider that divides the frequency signal formed by the oscillation circuit into the carrier frequency and forms a four-phase carrier having phases of 0 °, 90 °, 180 °, and 270 °,

A switch circuit for selecting the four-phase frequency-divided signal formed by the frequency divider and supplying the selected signal to the first and second frequency converters;

A phase axis inverting circuit for inverting the phase of the second standard force signal;

An arithmetic circuit for receiving the output signal of the phase axis inverting circuit and the first standard color signal;

A band-pass filter that receives only the output signal of the arithmetic circuit and extracts only the standard force signal component; By combining the phase shift amount of the standard force of the carrier selected by controlling the switch circuit and the phase axis inverting output, the force crosstalk included in the two standard force signal components is in opposite phase or in phase. A system using a VTR signal processing device, characterized in that the arithmetic circuit adds or subtracts the two standard power signals to cancel the power crosstalk.

2. The phase axis inverting circuit comprises a multiplying circuit for multiplying the second standard color signal by a frequency twice the reference frequency of the standard color signal formed by the crystal oscillation circuit. 2. The system using the signal processing device for a VTR according to claim 1, wherein an output signal level of the multiplying circuit is doubled and input to the circuit.

3. The oscillating circuit is a voltage controlled oscillating circuit, and is based on the reference frequency of the standard color signal formed by the crystal oscillating circuit and the standard power signal output from the first or second frequency conversion circuit. 2. The phase detection circuit according to claim 1, wherein the phase detection circuit receives the extracted color subcarrier component, and the oscillation frequency is controlled by a control voltage obtained by converting the phase detection signal into a direct current. A system using a VTR signal processor.

4. The oscillation circuit is a voltage-controlled oscillation circuit, and includes a reference frequency of the standard color signal formed by the crystal oscillation circuit, and a standard power output from the first or second frequency conversion circuit. A phase difference between the phase detection circuit and the chrominance subcarrier component extracted from the signal is detected by a phase detection circuit, and the oscillation frequency is controlled by a control voltage obtained by converting the phase detection output into a direct current. A system using the signal processing device for a VTR according to claim 3.

5. The above oscillation circuit outputs an oscillation signal with a carrier frequency that is twice as high, and the frequency divider circuit is composed of two through latch circuits of ECL configuration. The input and output are connected crosswise to perform a 1/2 frequency dividing operation, and form a fourth-order signal that differs by 90 ° from each pair of output terminals of the two through latches. 5. A system using the signal processing device for VTR according to claim 4.

6. The signal processing device for a VTR according to claim 1, wherein the delay circuit is configured by a CCD: