WO1998016005A1 - Detecteur de phase a remise a zero asynchrone explicite - Google Patents

Detecteur de phase a remise a zero asynchrone explicite Download PDF

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Publication number
WO1998016005A1
WO1998016005A1 PCT/US1997/017173 US9717173W WO9816005A1 WO 1998016005 A1 WO1998016005 A1 WO 1998016005A1 US 9717173 W US9717173 W US 9717173W WO 9816005 A1 WO9816005 A1 WO 9816005A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
reset
flip
output signal
phase
Prior art date
Application number
PCT/US1997/017173
Other languages
English (en)
Inventor
David R. Staab
Original Assignee
Peregrine Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peregrine Semiconductor Corporation filed Critical Peregrine Semiconductor Corporation
Publication of WO1998016005A1 publication Critical patent/WO1998016005A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

L'une des variantes de la présente invention comporte un détecteur (404) de phase muni d'un noeud (408) d'activation accessible de l'extérieur. Dans cette variante, le détecteur de phase comprend un circuit comparateur comparant un signal de référence (FR) à un signal de rétroaction (FV) et produit un signal de sortie représentant au moins l'écart de phase ou l'écart de fréquence entre le signal de référence et le signal de rétroaction. Dans cette même variante, le circuit comparateur comporte une mémoire fournissant le signal de sortie et se composant d'une première bascule (202A) et d'une deuxième bascule (202B). Il en résulte que le signal de sortie correspond aux signaux sortie de la première bascule et de la deuxième bascule. Le signal de sortie est relié à un circuit (402, 406) de remise à zéro renvoyé sur l'entrée (212A, 212B) de remise à zéro du circuit comparateur pour le remettre à zéro en réponse à un signal de sortie prédéterminé. Le noeud d'activation accessible de l'extérieur est également relié à l'entrée de remise à zéro du circuit comparateur de manière à permettre d'y accéder depuis l'extérieur du détecteur de phase. Le noeud d'activation en fournissant cet accès extérieur facilite la simulation logique, la vérification et/ou la gradation des erreurs des circuits contenant cette variante du détecteur de phase.
PCT/US1997/017173 1996-10-07 1997-09-25 Detecteur de phase a remise a zero asynchrone explicite WO1998016005A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72243596A 1996-10-07 1996-10-07
US08/722,435 1996-10-07

Publications (1)

Publication Number Publication Date
WO1998016005A1 true WO1998016005A1 (fr) 1998-04-16

Family

ID=24901825

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/017173 WO1998016005A1 (fr) 1996-10-07 1997-09-25 Detecteur de phase a remise a zero asynchrone explicite

Country Status (1)

Country Link
WO (1) WO1998016005A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103718463A (zh) * 2012-05-07 2014-04-09 旭化成微电子株式会社 高线性相位频率检测器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4291274A (en) * 1978-11-22 1981-09-22 Tokyo Shibaura Denki Kabushiki Kaisha Phase detector circuit using logic gates
JPS6411420A (en) * 1987-07-03 1989-01-17 Nec Corp Phase-locked loop integrated circuit
US4817199A (en) * 1987-07-17 1989-03-28 Rockwell International Corporation Phase locked loop having reduced response time
EP0402736A2 (fr) * 1989-06-14 1990-12-19 Fujitsu Limited Circuit détecteur de différence de phase
US5307028A (en) * 1992-10-16 1994-04-26 Ncr Corporation Phase-and-frequency mode/phase mode detector with the same gain in both modes
US5359297A (en) * 1993-10-28 1994-10-25 Motorola, Inc. VCO power-up circuit for PLL and method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4291274A (en) * 1978-11-22 1981-09-22 Tokyo Shibaura Denki Kabushiki Kaisha Phase detector circuit using logic gates
JPS6411420A (en) * 1987-07-03 1989-01-17 Nec Corp Phase-locked loop integrated circuit
US4817199A (en) * 1987-07-17 1989-03-28 Rockwell International Corporation Phase locked loop having reduced response time
EP0402736A2 (fr) * 1989-06-14 1990-12-19 Fujitsu Limited Circuit détecteur de différence de phase
US5307028A (en) * 1992-10-16 1994-04-26 Ncr Corporation Phase-and-frequency mode/phase mode detector with the same gain in both modes
US5359297A (en) * 1993-10-28 1994-10-25 Motorola, Inc. VCO power-up circuit for PLL and method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 013, no. 186 (E - 752) 2 May 1989 (1989-05-02) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103718463A (zh) * 2012-05-07 2014-04-09 旭化成微电子株式会社 高线性相位频率检测器

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