WO1998011602A1 - Procede de production de circuits integres cmos ou de transducteurs contenant ces circuits - Google Patents

Procede de production de circuits integres cmos ou de transducteurs contenant ces circuits Download PDF

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Publication number
WO1998011602A1
WO1998011602A1 PCT/EP1997/004931 EP9704931W WO9811602A1 WO 1998011602 A1 WO1998011602 A1 WO 1998011602A1 EP 9704931 W EP9704931 W EP 9704931W WO 9811602 A1 WO9811602 A1 WO 9811602A1
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WIPO (PCT)
Prior art keywords
substrate
well
secondary substrate
bulk
etching
Prior art date
Application number
PCT/EP1997/004931
Other languages
English (en)
Inventor
Andreas Haeberli
Mark Hornung
Thomas Mueller
Michael Schneider
Original Assignee
Physical Electronics Laboratory
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Physical Electronics Laboratory filed Critical Physical Electronics Laboratory
Publication of WO1998011602A1 publication Critical patent/WO1998011602A1/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • C25F3/12—Etching of semiconducting materials
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
    • G01L9/0042—Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/0802—Details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0728—Pre-CMOS, i.e. forming the micromechanical structure before the CMOS circuit
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/075—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure the electronic processing unit being integrated into an element of the micromechanical structure

Definitions

  • the invention is in the field of integrated circuitry and transducers in particular of complementary metal oxide silicon application specific integrated circuits (CMOS ASIC and its derivatives) and integrated micro electro mechanical devices and systems (iMEMS), in particular transducers containing CMOS circuitry.
  • CMOS ASIC and its derivatives complementary metal oxide silicon application specific integrated circuits
  • iMEMS integrated micro electro mechanical devices and systems
  • CMOS is the most used technology for very large scale integrated circuits (VLSI circuits).
  • Micro electro mechanical devices (MEMS) applies to a broad family of micro-machined transducers, sensors, actuators and systems with coupled electrical, mechanical, radiant, thermal, and chemical effects.
  • MEMS Micro electro mechanical devices
  • the term iMEMS refers to silicon integrated MEMS based on IC technology combined with micro-machining, film deposition or electroplating [1]. Interference of electrical signals in integrated circuits can substantially limit the accuracy. Thermal effects caused by on-chip temperature gradients or variation of the environmental temperature may cause problems in analog circuitry or transducers. Packaging and intrinsic stress of CMOS devices and transducers affect the properties of active (e.g. transistors) and passive (e.g. resistor) devices.
  • Sophisticated layout and compensation techniques are applied to reduce these effects.
  • these are e.g. fully differential architecture for signal conditioning circuits (reduces electrical interference), low stress packages (reduces packaging stress) or heating of the complete chip to a fixed temperature (reduces temperature related effects).
  • the noise sensitive part of a circuit can be separated from the noisy part of it by narrow grooves or trenches etched into the substrate from the back of the wafer by anisotropic etching. For stability reasons such grooves cannot surround the sensitive part completely and therefore the decoupling effect is not satisfactory in many cases.
  • anisotropic etching from the back of the wafer is applied to a wafer with an n- epitaxial layer, an electro-chemical etch stop acting on the junction between substrate and epitaxial layer. As this junction extends uniformly over the whole wafer, etching is restricted to one depth. Wafers with epitaxial layers are substantially more expensive than wafers without an epitaxial layer. No CMOS circuitry is available in this technology.
  • the object of the invention is to overcome the restrictions imposed by the above mentioned methods, i.e. the object of the invention is to create a method for producing on a chip micro-structures with a non limited circuitry, in particular with CMOS-circuitry (digital or analog), whereby it is to be possible to decouple the micro-structures (electric, thermal, and mechanical decoupling) from the rest of the chip in a manner suitable to any specific application.
  • CMOS-circuitry digital or analog
  • CMOS circuit is decoupled from the bulk of the substrate by positioning this at least part of the CMOS circuit on a secondary substrate with considerably less bulk than the original substrate and by decoupling the secondary substrate at least partly from the original substrate.
  • This is realized by a combination of multi-well technology and etching with electro-chemical etch stop either from the back or from the front of the wafer (e.g. anisotropic etching).
  • a multi-well is a region consisting of a well diffusion (p- or n-doped) which at least partially contains at least one further well diffusion.
  • the inventive method comprises the following steps:
  • the multi-well structure comprising a deep well with a further well positioned inside it or with a further multi-well structure positioned inside the deep well, whereby the further multi-well structure comprises a further deep well and so on.
  • the deep well or one of the further deep wells of the multi-well structure is designed for the function of the secondary substrate.
  • An integrated CMOS circuit with at least parts to be decoupled is produced such that the parts to be decoupled are positioned on the at least one multi-well structure.
  • the secondary substrate is then decoupled from the substrate by removing by etching at least parts of the substrate below the deep well of the multi-well structure or by removing the well below the one well of a further multi-well structure which has been designed as secondary substrate. Thereby, an electro chemical etch stop is used.
  • Such electro chemical etch stop works on any p-n-junction, i.e. between the substrate and the deepest well of the multi-well structure or on any junction between wells inside the multi-well structure. This means that the shape of the multi-well structure is determined not only by the circuitry to be realized but also by the decoupling effects to be achieved for the micro-structure to be realized. In the etching step at least part of the secondary substrate is decoupled from the rest of the chip.
  • Multi-well structures are per se known from high voltage CMOS processes [7].
  • source and/or drain diffusion (p- or n- doped) of CMOS transistors are placed in additional wells with opposite doping.
  • p- or n- doped source and/or drain diffusion (p- or n- doped) of CMOS transistors are placed in additional wells with opposite doping.
  • p-doped substrate In order to produce symmetrical pMOS and nMOS high voltage transistors on e.g. a p-doped substrate a p-doped well inside a n-doped well is needed.
  • This special feature of a high voltage CMOS process is according to the invention used for being able to realize electrical, thermal and stress decoupling low voltage CMOS circuits.
  • a wafer is fabricated which contains at least one area with a multi-well structure, which area may contain CMOS or bipolar circuitry or transducers and which area represents the area to be decoupled from the rest of the chip or to be micro-machined.
  • the chip or wafer is etched from the front or from the back in order to at least partly free the part of the multi-well structure designed as secondary substrate from the rest of the substrate such effecting the decoupling or realization of the desired structure.
  • the part of the silicon to be removed is basically defined by the multi-well (p/n-junctions), by the crystal orientation of the wafer (e.g. 100 orientation), by the etchant (e.g.
  • All wells of the multi-well structure can be arbitrarily shaped.
  • the multi-well can be considered e.g. as a substrate for a CMOS process which may contain n-MOS devices based on n + and p + diffusions in a p-well and p-MOS devices of p + and n + diffusions in an n-well.
  • the inventive method makes it possible to at least partially electrically, mechanically and thermally decouple CMOS and/or bipolar circuitry and/or transducers on micro-structures from the bulk of the substrate.
  • CMOS devices open or closed micro-structures
  • Figure 1 shows a cross section of an exemplified CMOS-chip with a multi- well structure (product of the first step of the inventive method);
  • Figure 2 shows an exemplified setup for electro chemical etching (second step of the inventive method);
  • Figures 3 to 7 show examples of micro-structures produced with the inventive method;
  • Figures 8 and 9 show examples of micro-structures produced with the inventive method comprising removed wells
  • Figure 10 shoes a simplified schematic of a magnetic sensor which is positioned on a secondary substrate being thermally, electrically and mechanically decoupled from the bulk of the substrate.
  • Figure 1 shows an exemplified cross section of a CMOS chip (product of the first step of the inventive method).
  • This chip comprises e.g. a p-substrate 1 and a multi-well structure consisting of wells 2 (n-doped), 2a (p-doped), 2b (n- doped) and 3 (p-doped).
  • wells 2, 2a and 2b may be designed to take over the function of the secondary substrate i.e. to be freed at least partially from the bulk of the substrate by removing by etching the substrate and/or the well below.
  • P-wells and/or n-wells of the chip according to Figure 1 may contain p + and/- or n + regions 4 (contact diffusions). Together with additional layers 5 (e.g. gate oxide, polysilicon, metal) n-MOS and p-MOS transistors are fabricated in the multi-well.
  • additional layers 5 e.g. gate oxide, polysilicon, metal
  • n-MOS and p-MOS transistors are fabricated in the multi-well.
  • the back of the wafer is prepared by an etch mask 6 (e.g. Si 3 N 4 ) for subsequent etching from the back.
  • a setup similar to the one shown in Fig. 2 is used to produce micro-structures by etching from the back of the wafer (second step of the inventive method).
  • the chip or wafer surface is mechanically protected from the etchant 8 (e.g. KOH) by a chip holder or wafer holder 7.
  • a potentiostat 9 controls the potential of the multi-well (2,3) and the bulk 1 of the chip or wafer relative to the etchant by means of a Pt-counter-electrode 10 and an Ag/AgCl reference electrode 11.
  • Figure 3 shows a multi-well 2, 3 freed from the back of the chip by removing parts of the substrate 1. Bulk silicon is removed not only below but also beside or around the multi-well whereby the etching is stopped at the lowest CMOS layer 18 (e.g. Si0 2 ). This enables thermal electrical and mechanical decoupling from the bulk substrate 1. When suspending the secondary substrate on the dielectric layers 18/19 only, it is adviseable to produce these layers such that they have low internal stress. A method for producing such layers is described in [9].
  • Figure 4 shows a micro-structure etched from the front. Etching starts through an arbitrarily shaped hole 12 in the dielectric layers. In Figure 5 the multi-well 2/3 is only partially freed by the etching step. This leads to a membrane consisting of the multi-well 2/3 (secondary substrate).
  • Figure 6 shows a multi-well 2/2a/2b/3 structure according to Figure 1 in which the well 2a is designed as secondary substrate. Again, the secondary substrate is only partially freed by the etch step, whereby the etch stop is performed not at the deepest well but at the junction between wells 2 and 2a within the multi-well structure. This leads to a membrane consisting of the multi-well 2a/2b/3.
  • Figure 7 shows a cantilever beam formed by a secondary substrate 2/3 which cantilever beam is produced by etching from the front.
  • the opening 12 where the dielectric layers (18, 19) are interrupted also, surrounds the most part of the beam.
  • Figs. 3 to 7 may be different cross sections of one single micro-structure. All wells and substrates in the drawings are assumed to be connected by p + and/or n + regions 4 and metal lines to the outer world.
  • Parts of integrated circuits may be decoupled for active or passive functions and may serve the following purposes:
  • Examples for passive function of the decoupling electrical decoupling of circuitry or transducers for reducing electrical interference affecting their performance;
  • thermal decoupling for decoupling circuitry or transducers from on-chip temperature gradients
  • thermal decoupling for keeping decoupled circuitry or transducer at a constant temperature by means of a heater
  • the multi-well e.g. consists of an n-well 2 which contains p-wells 3. After etching away part of the substrate 1 and one of the p-wells there is the n-well 2 serving as secondary substrate and a tunnel 13 between the CMOS layers 5 and the n-well 2.
  • Figure 9 shows a further chip produced according to the inventive method. Before etching it comprised a multi-well structure with three wells (2, 2a, 3), whereby the deepest well was designed to be etched away and the well 2a just above the deepest well was designed as secondary substrate. Etching from the front side of the chip results in a tunnel 13 below the secondary substrate. The bulk of the substrate 1 is left untouched.
  • FIG. 9 An example of an electrically, thermally and mechanically decoupled micro- structure is given in Figure 9. It is a magnetic sensor 14 (Magnetotransistor [8]) which is realized on secondary substrate 2 freed by anisotropic etching using an electro chemical etch stop.
  • Magnetic sensor 14 Magnetictotransistor [8]
  • On-chip circuitry 17 may be realized on-chip. References

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Analytical Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Selon l'invention, on a découplé de la masse d'un substrat au moins une partie d'un circuit CMOS, en plaçant au moins cette partie sur un second substrat (2) considérablement moins volumineux que le substrat original (1), et en découplant ce second substrat (2) au moins partiellement du substrat (1). On réalise cette opération en combinant une technologie de puits multiple et une technique d'attaque chimique à l'aide d'une couche d'arrêt d'attaque électrochimique (par exemple une gravure anisotrope), soit à partir de l'arrière, soit à partir de l'avant de la plaquette. Un puits multiple est une région consistant en une diffusion de puits (à dopage P ou N) (2), cette diffusion contenant au moins une autre diffusion de puits (3); grâce à cet agencement, le puits le plus profond (2), ou un autre puits de la structure à puits multiple, est conçu pour fonctionner en tant que second substrat.
PCT/EP1997/004931 1996-09-12 1997-09-09 Procede de production de circuits integres cmos ou de transducteurs contenant ces circuits WO1998011602A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2617596P 1996-09-12 1996-09-12
US60/026,175 1996-09-12

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WO1998011602A1 true WO1998011602A1 (fr) 1998-03-19

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2778742A1 (fr) * 1998-05-18 1999-11-19 Schneider Electric Sa Capteur thermoelectrique notamment pour appareils electriques
US9184138B2 (en) 2011-12-29 2015-11-10 Stmicroelectronics (Grenoble 2) Sas Semiconductor integrated device with mechanically decoupled active area and related manufacturing process
US9663354B2 (en) 2014-05-14 2017-05-30 Infineon Technologies Ag Mechanical stress-decoupling in semiconductor device

Citations (3)

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Publication number Priority date Publication date Assignee Title
US5493248A (en) * 1990-09-04 1996-02-20 Motorola, Inc. Integrated circuit for sensing an environmental condition and producing a high power circuit
EP0702221A2 (fr) * 1994-09-14 1996-03-20 Delco Electronics Corporation Capteur intégré sur puce unique
US5600174A (en) * 1994-10-11 1997-02-04 The Board Of Trustees Of The Leeland Stanford Junior University Suspended single crystal silicon structures and method of making same

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US5493248A (en) * 1990-09-04 1996-02-20 Motorola, Inc. Integrated circuit for sensing an environmental condition and producing a high power circuit
EP0702221A2 (fr) * 1994-09-14 1996-03-20 Delco Electronics Corporation Capteur intégré sur puce unique
US5600174A (en) * 1994-10-11 1997-02-04 The Board Of Trustees Of The Leeland Stanford Junior University Suspended single crystal silicon structures and method of making same

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Title
E.H. KLAASEN ET AL.: "Micromachined thermally isolated circuits", SENSORS AND ACTUATORS A, vol. a58, no. 1, January 1997 (1997-01-01), pages 43 - 50, XP004089068 *
KLOECK B ET AL: "STUDY OF ELECTROCHEMICAL ETCH-STOP FOR HIGH-PRECISION THICKNESS CONTROL OF SILICON MEMBRANES", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 36, no. 4, April 1989 (1989-04-01), pages 663 - 669, XP000039394 *
M. SCHNEIDER ET AL.: "Integrated micromachined decoupled cmos chip on chip.", PROCEEDINGS IEEE, THE TENTH ANNUAL INTERNATIONAL WORKSHOP ON MICRO ELECTRO MECHANICAL SYSTEMS. AN INVESTIGATION ON MICROSTRUCTURES, SENSORS, ACTUATORS, MACHINES ANS ROBOTS, 26 January 1997 (1997-01-26) - 30 January 1997 (1997-01-30), NAGOYA, JP., pages 512 - 517, XP002050242 *
R. LENGGENHAGER ET AL.: "Thermoelectric Infrared Sensors by CMOS technology", IEEE ELECTRON DEVICE LETTERS., vol. 13, no. 9, September 1992 (1992-09-01), NEW YORK US, pages 454 - 456, XP000369683 *
REAY R J ET AL: "A MICROMACHINED LOW-POWER TEMPERATURE-REGULATED BANDGAP VOLTAGE REFERENCE", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 30, no. 12, 1 December 1995 (1995-12-01), pages 1374 - 1381, XP000557242 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2778742A1 (fr) * 1998-05-18 1999-11-19 Schneider Electric Sa Capteur thermoelectrique notamment pour appareils electriques
US9184138B2 (en) 2011-12-29 2015-11-10 Stmicroelectronics (Grenoble 2) Sas Semiconductor integrated device with mechanically decoupled active area and related manufacturing process
US9663354B2 (en) 2014-05-14 2017-05-30 Infineon Technologies Ag Mechanical stress-decoupling in semiconductor device
US9991340B2 (en) 2014-05-14 2018-06-05 Infineon Technologies Ag Mechanical stress-decoupling in semiconductor device

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