MONOLITHIC INTEGRATED CIRCUIT INCLUDING BIPOLAR TRANSISTORS HAVING NONUNIFORMLY DOPED COLLECTOR BASE
JUNCTION
An important device in electronics is the bipolar device, for example the silicon based bipolar junction transistor ("BJT") and the gallium arsenide based heterojunction bipolar transistor ("HBT"). Transistors are used in many applications including general amplification, wireless communications, and signal sources, such as voltage controlled oscillators. Desirable electrical characteristics and performance parameters differ depending upon the application. As an example, linearity is important in a transistor used for amplification. In an ideal transistor used for amplification, the output power as a function of input power varies linearly and the output phase differential is zero. In known bipolar devices, the output power is a nonlinear function of input power at certain values in the operating range of the device which is commonly referred to as amplitude to amplitude distortion. In addition, output phase relative to the input phase also varies over the operating range and is commonly referred to as amplitude to phase distortion. As a practical matter, these nonlinearities are more prevalent as input power increases for a given operating frequency. It is desirable to improve linearity of a device because as the linearity of the device improves, there is less distortion and therefore improved output signal quality. Improved output signal quality increases the usable signal power in the communication frequency band and minimizes power output for frequencies outside of the communication frequency band. Improved linearity, therefore, improves the efficiency of the device when it is used in a communications application.
Conventionally, compensation for the nonlinearity of a device may be done in a circuit . For example a feed forward amplifier is arranged to compensate for amplitude to phase distortion and amplitude to amplitude distortion wherein dual amplifier paths are added out of phase with each other in an attempt to cancel nonlinearities that are present. The circuit solution is imperfect and requires additional space to accommodate two amplifiers. There is a need, therefore, to improve the amplitude to phase linearity of the device itself to obviate the need to use compensating circuitry.
It has been noted that heterojunction bipolar transistors exhibit unusually low intermodulation distortion. In examining a proposed small signal model of the device, it has been suggested that for small signals, capacitive and reaction nonlinearities in the base-emitter junction operate on second-order intermodulation products to cancel each other out and achieve the unusually good intermodulation distortion performance. The analysis and model assumes weak nonlinearities and accounts for small signal operation. There remains a need, therefore, to achieve improved linearity for larger signal operation where the nonlinearities are stronger.
Conventional HBTs have a uniformly doped collector region. Based on the device materials and doping concentrations, a conventional Gummel-Poon model can be used to predict device performance. Efforts have been made to reduce the value of parasitic elements in practical devices in order to improve linearity, but nonlinearities remain in the device.
A BJT having a retrograde collector doping profile is known. The retrograde doping profile comprises a collector region wherein the doping increases as a function of distance from the collector base junction.
The retrograde collector region doping profile is used to increase the critical current density while limiting the zero bias collector-emitter junction breakdown voltage. It is not known how the retrograde collector region doping profile would affect the large signal linearity of the device.
There is a need, therefore, for a bipolar junction device having improved linearity over prior art devices . In a conventional signal source application, a transistor is combined with a varactor diode to form a voltage controlled oscillator ("VCO") circuit. It is desirable for a transistor in a VCO circuit to have a relatively high gain. It is also desirable for a varactor diode to exhibit a strongly nonlinear capacitance voltage relationship and a relatively high quality factor when reverse biased. In the interest of miniaturization and manufacturing cost reduction, it is further desirable to integrate the transistor and the varactor on the same die. Monolithic circuits benefit from physical miniaturization and short electrical lengths that result from the close physical proximity of one device to another. Some circuits, however, require the beneficial electrical characteristics from different devices having incompatible fabrication processes. In these cases, a common alternative to a monolithic circuit, is fabrication of the constituent devices in separate processes, singulation of the device dies, and mounting and interconnecting the devices on a printed circuit board ("PCB") or glass substrate. The PCB implementation is acceptably low in cost at the expense of larger size as compared to the smaller, but more expensive glass substrate implementation.
By way of example, the conventional VCO circuit uses a transistor amplifier, a resonator, and a varactor to define the operating frequency range. The frequency of the VCO is varied by applying a varying bias to the
varactor thereby changing its capacitance. A hyperabrupt junction diode has electrical characteristics beneficial to a VCO circuit because it exhibits a more nonlinear capacitance-voltage relationship than a conventional diode having a uniform doping junction profile. A hyperabrupt diode, however, uses a different fabrication process than a conventional high gain transistor that is desirable for use in a high performance VCO circuits. Accordingly, the diode and the transistor are conventionally fabricated as discrete elements.
There is a need therefore, for an integrated transistor and varactor suitable for use in a high performance VCO circuit .
It is an object of an embodiment of the present invention to improve the linearity in a bipolar junction device .
It is an object of an embodiment of the present invention to provide an integrated circuit suitable for use in a high performance VCO. A bipolar transistor comprises an emitter region, a base region, a collector region, and a collector base junction. The improvement comprises a nonuniform doping profile in the collector region. The doping concentration in the collector region varies in inverse proportion to a distance from the collector base junction.
It is a feature of an embodiment of the present invention, that a bipolar junction device has a collector region with a nonuniform doping profile. It is an feature of an embodiment of the present invention that a transistor and high quality diode can be fabricated using the same process.
It is an advantage of a bipolar junction device according to the teachings of the present invention that a the device exhibits improved linearity over prior art devices .
It is an advantage of a circuit according to the teachings of the present invention that a greater level of integration may be achieved for a high performance VCO. It is an advantage of a device according to the teachings of the present invention that a transistor device having relatively high gain may be monolithically fabricated with a diode having a capacitance that varies strongly as a function of applied voltage. Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:
Figure 1 is a graph illustrating the transfer function of a conventional bipolar transistor showing the deviation in performance from an ideal device.
Figure 2 is a conceptual model used to illustrate a device according to the teachings of the present invention .
Figures 3 - 5 are graphs showing simulated results for modeled devices, each graph showing results of a single term defined by a collector region doping profile that was varied over a range .
Figure 6 is a graph illustrating a doping profile for a conventional uniformly doped HBT as compared to an embodiment of a HBT according to the teachings of the present invention.
Figure 7 is a graph illustrating the relationship between the collector base voltage and the collector base capacitance for a conventional HBT and for an embodiment of an HBT according to the teachings of the present invention.
Figure 8 is a graph comparing the output signal to input signal amplitude and phase transfer functions and relative gain respectively exhibited by a conventional HBT as compared to the same transfer function exhibited by a simulated device according to the teachings of the present invention.
Figure 9 is a graph of the inverse of the capacitance of a reverse biased diode according to the teachings of the present invention as a function of applied reverse bias voltage. Figure 10 is a cross sectional view of an integrated bipolar transistor device and diode according to the teachings of the present invention.
Figure 11 is a schematic of a VCO circuit according to the teachings of the present invention. Figure 12 is an assembly schematic of a VCO circuit according to the teachings of the present invention.
With specific reference to Figures 1 and 2 of the drawings, an equivalent circuit model that can model large signal behavior for a bipolar device comprises a conventional Gummel-Poon model also referred to as an extended Ebers-Moll model. The model has a base (100) an emitter (200) , and a collector (300) and equivalent circuit parameters interconnecting these points on the device that simulate device performance. A conceptual simplification of the conventional model (1) is shown in Figure 2 of the drawings and comprises a base-emitter diode junction modeled as a base-emitter impedance element (11) comprising parallel emitter resistive (3) and emitter capacitive (4) components. The emitter resistor (3) and emitter capacitor (4) are connected between a common point (5) internal to the device and reference potential (6) . In Figure 2, reference potential is shown as a ground connection. In the conceptual model (1) , the emitter resistor (3) and the emitter capacitor (4) vary as a function of base-emitter voltage. The conceptual module (1) further includes a base-collector junction capacitive element (10) between the collector (300) and the base (100) that varies as a function of collector-base voltage. The conceptual model (1) further includes a base resistor (7) between the base (100) and the common point (5) and a current source element (8) reflecting a gain, α, over a current (Ie) flowing through the emitter junction.
It has been determined that a significant mechanism generating amplitude-to-phase distortion is the base emitter impedance element (11) . It has further been found that the amplitude to phase distortion contributed by the emitter impedance element (11) can be canceled by amplitude to phase distortion contributed by the base collector junction conceptually modeled as the base- collector junction capacitive element (10) . It is believed that the distortion cancellation occurs primarily due to the fact that the base collector
capacitance (10) is in a feedback path that controls the base-emitter impedance (11) . Accordingly, it is proposed that nonlinearities be inserted into the collector region and collector-base junction. The increased nonlinearity of the collector-base capacitance as a function of collector base voltage can be used to compensate for nonlinearities present in the base emitter junction. By creating a base-collector capacitance that varies more strongly as a function of applied voltage, the base collector capacitance function contributes a distortion component that cancels the distortion component contributed by the base emitter junction.
Specifically, the collector- base junction can be engineered to compensate for base- emitter nonlinearities by fabricating a device with a nonuniformly doped collector region and specific collector-base junction doping level. It is preferable that the doping concentration in the collector region vary as a function of distance from the base collector junction that is inversely proportional to the distance from the base collector junction.
The base collector capacitance (10) can be generally represented by the following relationship:
Chr(Vnh)= C,
where C
j0 is the zero bias depletion capacitance of the collector base junction, V
10 is the built in potential of the collector base junction, and m is a parameter based upon the doping. All three terms are constants based upon the collector region doping profile. The collector-base capacitance (10) as a function of collector-base voltage (V
cb) can therefore be modified by adapting the C,
0, V
:0 and/or m terms to achieve a desired result.
In order to simulate different phenomenon using the general collector base capacitance equation above, two Gummel-Poon 16 finger, 3 x 20 micron HBT devices in parallel were used to simulate a 32 finger device. The parameters and model used are published in a technical paper entitled "A Novel Extraction Method For Accurate Determination of HBT Large Signal Model Parameters" by Wu, Fukada, and Yun out of the 1995 IEEE MTT-S Digest the contents of which are hereby incorporated by reference. All parameters used in the model are identical to those disclosed in the paper except for Ree which was 0.54 ohms. The bias conditions and source and load impedances for the 32-finger simulation were: V
c = 4.2v V
b = 1.47V
ZB = 4.9 - jO.9 ohms Z* = 7.5 + j 1.7 ohms With specific reference to Figures 3 - 5 of the drawings, three different simulation cases show the relative significance of varying each one of the three terms in the variable collector base capacitor (10) on the device linearity. Simulating the output power amplitude, phase and gain as a function of input power yields the following results at 1.88 GHz input signal frequency. With reference to Figure 3 varying m from 0.5 to 1, it was noted that as m increased, some phase distortion cancellation occurred. The phase distortion cancellation was incomplete in that it did not overcompensate within the varied range. With reference to Figure 4, varying Cjo from 2.13pF to 4.63pF, it was noted that the phase distortion cancellation effect was strong, and the overall gain of the device was lower. With reference to Figure 5, varying Vo from 1.5v to 0.5v, it was noted that the 3dB compression point of the device occurred at lower power levels, and the phase distortion shifted from some cancellation to over compensation over the V,0 range.
By fabricating a bipolar device according to specific doping parameters, therefore, a desired amount of nonlinearity can be designed into the collector region and collector base junction while taking other performance parameters into account . The preferred embodiment is designed to primarily minimize phase distortion and secondarily minimize amplitude distortion. Specifically, m is selected to be greater than 1/2 and substantially similar to 1.0. VDO is selected to fall within the range of 1.0 to 1.5v specifically 1.29v. As a consequence of the materials used and doping concentration, Cjo is equal to approximately 2.67pF.
In a preferred embodiment, a GaAs HBT is fabricated with a hyperabrupt collector-base junction. A hyperabrupt junction diode is known in the art and has a doping profile that yields the value of m=l . A speci ic doping profile for an HBT having a hyperabrupt collector base junction is illustrated in Figure 6 of the drawings which yields a V.a of 1.29v and a CJO of 2.67pF. A most general form of a collector region doping profile according to the teachings of the present invention would have an infinite doping concentration at the base- collector junction and decreasing concentration as a function of distance from the base collector junction in a continuously varying inverse proportional relationship. As a practical matter, a piece wise linear approximation in steps of 100 Angstroms is used yielding the following profile for a three inch diameter wafer of semi-insulating GaAs HBT devices:
Layer Description Dopant Composition Concentration Thickness No. (cm)"3 (A)
20 n+GaAs Silicon >5.0el8 750
19 nAlxGaι-xAs Silicon x=0.3 to 0 5.0el7 300
18 nAlxGaι-xAs Silicon x=0.3 5.0el7 1200
17 nAlχGaι-xAs Silicon x=0 to 0.3 5.0el7 300
16 p GaAs Carbon 3.0el9 IOOO
15 i GaAs Silicon 1.0 to 5el5 100
14 n GaAs Silicon 4.0el7 200
13 n GaAs Silicon 4.6el6 to 2.0el7 100
12 n GaAs Silicon 2.6el6 to 4.6el6 100
11 n GaAs Silicon l.βelβ to 2.6elβ 100
10 n GaAs Silicon 1.4el6 to l.βelβ 100
9 n GaAs Silicon l.lelβ to 1.4elβ 100
8 n GaAs Silicon 9.5elβ to l.lelβ 100
7 n GaAs Silicon 8.2el5 to 9.5el5 100
6 n GaAs Silicon 7.2el5 to 8.2el5 100
5 n GaAs Silicon 6.4el5 to 7.2el5 100
4 n GaAs Silicon 1.6el5 to 6.4el5 2900
3 n GaAs Silicon 8.9el4 to 1.6el5 2900
2 n GaAs Silicon 6.4el4 to 8.9el4 2900
1 n+GaAs Silicon 5.0el8 6000
With specific reference to Figure 7 of the drawings, the base collector capacitance (10) as a function of collector base voltage (Vcb) for the hyperabrupt doping profile shows a strong nonlinear inverse relationship between the collector base voltage and the collector base capacitance when compared to the same relationship for a conventional device. It is this nonlinear relationship that permits cancellation of the base-emitter nonlinearities to render a device with improved linearity. Figure 8 of the drawings illustrates the comparative results of a conventional device as compared to a simulated device according to
the preferred embodiment. Of particular note in Figure 8 is the output phase differential which is shown as having some cancellation at a power level where a conventional device has significant distortion. Phase distortion for the device with a nonuniform doping level increases at higher input power levels than in the conventional device.
Accordingly, there is shown a bipolar device having a collector region (27) arranged to compensate for device junction nonlinearities in order to render the overall device more linear. The preferred embodiment described is for a GaAs HBT device. The teachings, however, can apply to Silicon bipolar junction transistors, Silicon Germanium HBTs and BJTs , and Indium Phosphide/Indium GaAs HBTs having appropriate collector region doping profiles.
Advantageously, a bipolar transistor fabricated according to the teachings of the present invention exhibits relatively high gain and has a fabrication process that is compatible with a varactor diode that exhibits a desirably high quality factor as well as a strong nonlinear capacitance as a function of applied voltage. A high performance VCO circuit is made possible by a combination of the bipolar transistor device (20) as previously described and a hyperabrupt junction varactor diode (21) having the same voltage- capacitance relationship as the base-collector junction of the transistor (20) . Advantageously, the amplification of the bipolar transistor device having a nonuniformly doped collector region is relatively high. Because contacts (22) for the devices (20,21) are made to the base and collector layers of the bipolar transistor as part of the fabrication process, no additional process steps are required to fabricate the transistor (20) according to the teachings of the present invention and a hyperabrupt tuning diode (21) using the same process on the same chip. Accordingly,
in view of the present teachings, it is possible to integrate the bipolar transistor device (20) having advantageously high gain with a varactor device (21) having an advantageously strong nonlinear capacitance- voltage relationship and a relatively high quality factor. This integration results in a smaller, more economical monolithic microwave IC ("MMIC") that is easier to package.
With specific reference to Figure 9 of the drawings, there is shown a relationship of the inverse of the capacitance of the GaAs hyperabrupt juction diode (21) fabricated according to the teachings of the present invention. The diode (21) has an anode region (17) , a cathode region (18) , and an anode cathode junction. Figure 9 of the drawings shows the capacitance of the diode (21) as a function of applied reverse bias voltage, that is the cathode (18) has a positive voltage applied relative to the anode (17) . In the GaAs hyperabrupt diode (21) , the capacitance follows the relationship:
Ccb (Vcb) =0.98/ (1+Vcb/1.47) fF/ (μm2) where Vcb is the voltage applied to the varactor diode (21) in units of volts. The quality factor of the GaAs hyperabrupt varactor diode (21) is estimated at approximately 1000 at 50MHz.
With specific reference to Figure 10 of the drawings, there is shown a cross sectional view of a MMIC (23) comprising the GaAs HBT (20) having a hyperabrupt base-collector junction adjacent the hyperabrupt varactor diode (21) . The n+ (24) , base (26) and collector (25) , regions of the GaAs HBT (20) and the n-t- (24) , anode (17) , and cathode (18) respectively, of the hyperabrupt varactor diode (21) are made by identical process steps. Specifically, the layers 1-16 described in Table I. As one of ordinary skill in the art will appreciate, fabrication of the integrated transistor and hyperabrupt varactor diode (21) comprises
processing the base, collector, and emitter regions, etching off the emitter layer of the varactor diode (21) during the emitter mesa process to leave the anode (17) and cathode (18) regions, and contacting of the anode layer (17) using the standard base contact process. Specifically the layers 17-20 described in Table I of the GaAs HBT are removed.
With specific reference to Figure 11 of the drawings, there is shown a circuit schematic of a VCO according to the teachings of the present invention in which the GaAs MMIC (23) comprising the HBT (20) , the varactor (21) , and some passive circuitry is used in combination with a resonator (29) and supporting circuitry implemented as a glass microwave integrated circuit ("GMIC") (30) to create a VCO circuit.
The GaAs MMIC (23) comprises the HBT (20) having a nonuniformly doped collector region as previously described. The base (100) and emitter (200) are interconnected through a first splitter capacitor (40) having a value of 4.25pF. The emitter (200) is interconnected to reference potential (6) through a second splitter capacitor (41) having a value of 5pF, and a DC return comprising an emitter RF choke circuit and two 22ohm resistors (39) in parallel. The emitter RF choke circuit comprises an emitter choke inductor
(42) having a value of 4.3nH interconnected in series between the emitter (200) and an emitter choke capacitor
(43) having a value of 11.5pF. The emitter choke capacitor (43) is connected in parallel with the two 22ohm parallel resistors (39) . A positive feedback capacitor (44) interconnects the base (100) to reference potential and has a value of 0.25pF and operates to maximize the oscillations excited in the HBT (20) . A 3.3VDC bias voltage is applied to a top of resistive voltage divider comprising first and second voltage divider resistors (45,46). The 3.3VDC bias voltage is presented to the circuit through bias port (38) .
Approximately 1.8V of the 3.3V bias is dropped across the first voltage divider resistor (45) , the other side of which is connected to the base (100) to maintain a DC voltage differential between the collector (300) and the base (100) , and maintaining the HBT (20) at bias conditions appropriate for the VCO circuit operation. A 17.5pF bias voltage choke capacitor (47), implemented on the GMIC (30) and interconnected to the MMIC (23) , minimizes RF energy that may leak through to the collector (300) and base (100) of the HBT (20) . An inductor-capacitor tank circuit comprising tank inductor (48) in series with a 20pF RF block capacitor (50) and a parallel combination of shunt tank capacitor (49) and varactor (21) is connected to base (100) of HBT (20) . The tank circuit establishes the frequency of oscillation of the VCO by tuning the capacitance of varactor (21) over a tuning range. In the disclosed embodiment, a reverse biased tuning voltage over a 0- 2.8VDC tuning range is applied directly to the tank capacitor (49) /varactor (21) combination through a tuning port (46) . The 0-2.8VDC tuning range represents a 6.5pF to 2.2pF capacitance tuning range for the varactor (21) . A reverse signal series inductor (31) and a reverse signal shunt capacitor (32) connected at the input of the tuning port (46) , have a value of 15.2nH and 17.5pF respectively. The reverse signal series inductor (31) operates as a short circuit for the DC tuning signal in a forward path and as an open circuit in a reverse path to isolate the tuning port (46) from any RF leakage from the base (100) of the HBT (20) . Similarly, the reverse signal shunt capacitor (32) operates as an open circuit for the DC tuning signal in a forward path and as a short circuit in a reverse path to further isolate the tuning port (46) from RF leakage by shorting any RF energy that passes through the reverse signal series inductor (31) . The oscillating signal present at the base (100) of the HBT
(20) is presented to output port (36) through coupling capacitor (37) which has a nominal value of 0.75pF. Advantageously, due to the relatively high gain of the HBT (20) in the disclosed embodiment, the oscillating signal may be coupled to the output port (36) with a relatively small valued coupling capacitor which serves to decouple the transistor noise from the tank circuit (48,49,50). Three interconnects, bias interconnect (33), output interconnect (34), and varactor interconnect (35) , connect the GaAs MMIC (23) to the GMIC (30) to create the VCO circuit.
With specific reference to Figure 12 of the drawings, there is shown an assembly drawing showing the resonator (29) implemented on a glass microwave integrated circuit ("GMIC") adjacent the GaAs MMIC amplifier/tuning circuit disposed on an SOIC-8 lead frame. Three internal wirebonds interconnect the GMIC resonator with the GaAs MMIC at the interconnects (33,34,35) shown in Figure 11 of the drawings. Three external wirebonds interconnect the GMIC resonator to leads (14) of a lead frame (15) on which the GMIC (30) and MMIC (23) are mounted. The three leads that are wirebonded to the GMIC (30) permit presentation of the bias and tuning voltages to the bias port (38) and tuning port (46), respectively, and presentation of the oscillating signal to one of the external leads (14) through output port (36) . The remaining wirebonds interconnect circuit reference points to a die attach paddle (16) of the SOIC-8 lead frame (15) . Other advantages of the invention are apparent from the detailed description by way of example, and from accompanying drawings, and from the spirit and scope of the appended claims.