WO1997044821A1 - Metal electronic package with peripherally attached leads - Google Patents

Metal electronic package with peripherally attached leads Download PDF

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Publication number
WO1997044821A1
WO1997044821A1 PCT/US1997/007249 US9707249W WO9744821A1 WO 1997044821 A1 WO1997044821 A1 WO 1997044821A1 US 9707249 W US9707249 W US 9707249W WO 9744821 A1 WO9744821 A1 WO 9744821A1
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WO
WIPO (PCT)
Prior art keywords
electronic package
package assembly
external leads
sidewalls
dielectric layer
Prior art date
Application number
PCT/US1997/007249
Other languages
French (fr)
Inventor
Deepak Mahulikar
Arvind Parthasarathi
Paul R. Hoffman
Jeffrey S. Braden
Original Assignee
Olin Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olin Corporation filed Critical Olin Corporation
Publication of WO1997044821A1 publication Critical patent/WO1997044821A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16151—Cap comprising an aperture, e.g. for pressure control, encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to metal packages for housing one or more integrated circuit devices. More particularly, circuitry formed on a surface of the package base electrically interconnects the integrated circuit device to a plurality of peripheral external leads.
  • An adhesively sealed metal package is disclosed in U.S. Patent No. 4,939,316 to Mahulikar et al.
  • This package has a metallic base and a cover.
  • a leadframe is disposed between the base and the cover and adhesively bonded to both.
  • the leadframe may include a centrally positioned die attach paddle with an integrated circuit device bonded to the paddle. Bond wires electrically interconnect the device to the leadframe.
  • An advantage of metal packages over molded plastic packages such as quad flat packs (QFPs) or ceramic packages such as ceramic dual in line packages (CERDIPs) is improved thermal conduction.
  • the metal package removes heat generated during the operation of the device more efficiently than either a plastic or a ceramic package.
  • the improved heat dissipation is due to both the improved thermal conduction of the metallic components and the ability of the components to disperse heat laterally along all surfaces of the package.
  • the improved thermal dissipation permits encapsulation of more complex and higher power integrated circuit devices than is possible with plastic or ceramic packages.
  • An objective of electronic package design is to minimize both the thickness of the electronic package and the package footprint.
  • the footprint is the area on a printed circuit board occupied by the body of the package and the external leads that interconnect the package to the printed circuit board.
  • the leads In a quad flat pack, either metal or plastic, the leads extend outwardly from the body of the package increasing the package footprint.
  • One way to minimize the increase in the package footprint is to use J-shaped leads that extend along the sidewalls of the package and then curl beneath the package base.
  • J-shaped leads are effective when the package base is formed from an electrically non-conductive material such as a ceramic or plastic.
  • the leads are also effective when the package base is an electrically conductive material having surfaces coated with an electrically non-conductive material, such as an aluminum alloy base coated with an anodic film.
  • J-shaped leads are less effective when the metallic base component has one or more electrically conductive sidewalls that have the potential to electrically short circuit the leads.
  • Another approach to reduce the package footprint is to replace the leads with a plurality of solder balls formed on a surface of the package base.
  • This package known as a ball grid array, is disclosed in International Application Seria.1 No. PCT/US95/08305, published on February 1, 1996.
  • One metal ball grid array package has an aluminum alloy base that is coated with an anodic film.
  • a semiconductor device is mounted on a central portion of the base. Electrically conductive circuit traces extend outward from this central region and terminate in an array of ball attach pads. The semiconductor device is electrically interconnected to the inner terminations of the circuit traces while solder balls are mounted to the outer terminations.
  • the package includes, in one embodiment, peripherally attached, generally C- shaped metallic leads that are electrically isolated from the package sidewalls by an electrically insulating material.
  • the external leads are a single row of peripherally attached solder balls that may be in either a straight line arrangement or a staggered arrangement.
  • the metal electronic packages of the invention have a smaller footprint than achieved with a conventional quad flat pack.
  • the packages do not require a separate metal cover and are thinner and lower weight than conventional packages.
  • the metal packages are particularly amenable to high volume, low cost, manufacture.
  • an electronic package assembly has a metallic substrate with first and second opposing surfaces separated by (N) sidewalls.
  • a dielectric layer coats the first and second surfaces and up to (N) sidewalls.
  • Circuit traces are formed on the dielectric layer on the first surfaces.
  • the circuit traces have first ends that are electrically interconnected to a semiconductor device and opposing second ends that terminate at a perimeter of the metallic substrate. External leads are bonded to the second ends and extend beyond the sidewalls and terminate proximate to the second surface of the metallic substrate.
  • An electrically insulating material is disposed between the metallic leads and respective sidewalls.
  • Circuit traces are formed on the dielectric film.
  • the circuit traces have first ends that are electrically interconnected to a semiconductor device and opposing second ends that terminate at a perimeter of the metallic substrate. Electrical interconnects are bonded to the second ends.
  • Figure 1 illustrates in top planar view a panel for the manufacture of a plurality of metal electronic package substrates.
  • Figure 2 illustrates in cross-sectional representation external C-shaped leads in accordance with an embodiment of the invention.
  • Figure 3 illustrates in cross-sectional representation external C-shaped leads in accordance with another embodiment of the invention.
  • Figure 4 illustrates in cross-sectional representation peripheral solder balls in accordance with an embodiment of the invention.
  • Figure 5 illustrates in planar view a peripheral row of staggered solder balls.
  • Figure 6 illustrates peripherally attached external leads in accordance with an embodiment of the invention.
  • Figure 7 illustrates external leads attached to circuit traces in accordance with an embodiment of the invention.
  • Figure 8 illustrates external leads attached to circuit traces in accordance with another embodiment of the invention.
  • Figure 1 illustrates a panel 10 used to form a plurality of metal package substrates 12-20.
  • the panel 10 is formed from a thermally conductive, electrically conductive, material such as copper aluminum or an alloy thereof. Aluminum alloys of the 3000, 5000 and 6000 series as designated by the Aluminum Association, Inc. are most preferred.
  • 3000 series alloys contain up to about 1.5% by weight manganese, along with other alloying elements.
  • a most preferred 3000 series aluminum alloy is aluminum alloy 3003 having a nominal composition, by weight, of 0.12% copper, 1.2% manganese and the balance aluminum.
  • 5000 series alloys contain magnesium and usually chromium as well.
  • Preferred aluminum alloys of the 5000 series include aluminum alloy 5086 (nominal composition by weight, 0.20%-0>7% manganese, 3.5%-4.5% magnesium and the balance aluminum); 5252 (nominal composition by weight, 2.2%-2.8% magnesium, and the balance aluminum); 5657 (nominal composition by weight, 0.6%-1.0% magnesium, the balance aluminum) ; and 5457 (nominal composition by weight, 0.08%-1.2% magnesium, 0.15%-0.45% manganese and the balance aluminum) .
  • 6000 series alloys contain silicon and magnesium in approximate proportions to form magnesium suicide.
  • a most preferred aluminum alloy of the 6000 series is aluminum alloy 6061 (nominal composition by weight, 0.4%-0.8% silicon, 0.15%-0.4% copper, 0.8%-1.2% magnesium, 0.04%-0.35% chromium and the balance aluminum) .
  • the panel 10 is coated with a dielectric layer.
  • the dielectric layer may be an anodic film. Preferred anodic films are formed by integral color anodization as disclosed in U.S. Patent No. 5,066,368 to Pasqualoni et al.
  • the dielectric layer is typically a polymer film, such as a thin film of epoxy.
  • the dielectric film has a thickness of under 10 microns to maximize the conduction of heat to the metallic substrate.
  • the thickness of the dielectric film is under five microns. The minimum effective thickness is that dielectric film thickness that electrically isolates circuit traces formed on the dielectric film from the underlying metallic substrate.
  • Circuit traces 22 are formed on each of the metal substrates 12-20.
  • the circuit traces 22 have first ends 24 and opposing second ends 26. The opposing second ends terminate adjacent to, or preferably at, a perimeter 28 of the individual metallic substrates 12-20.
  • the panel 10 is singulated by cutting or dicing the panel 10 (along dotted lines 30) to form a plurality of individual metallic substrates 12-20.
  • both the panel 10 and individual metallic substrates may be of any desired size and the number metallic substrates formed from a panel may be of any desired quantity.
  • Figure 1 illustrates the individual metallic substrates as square with four sidewalls
  • the substrates may be any shape and the actual number (N) of sidewalls is variable.
  • each singulated metallic substrate may have two (substrates 12, 14, 18 and 20) three (substrates 13, 15, 17 and 19) or four (substrate 16) electrically conductive sidewalls.
  • FIG. 2 illustrates in cross-sectional representation an external lead 32 for use with a singulated metallic substrate 12 (substrate 12 was arbitrarily picked, any singulated metallic substrate is equally amenable to the invention) .
  • the metallic substrate 12 has a metal core 34 having a first surface 36 and a second surface 38.
  • a dielectric layer 42 is formed on the first surface 36 and on the second surface 38. As described above, typical dielectric layers 42 include anodic films and polymer films. Circuit traces 44 are formed on the dielectric layer 42.
  • the circuit traces 22 are bonded to the dielectric layer 42 such as with a polymer adhesive 46 and formed into circuit traces by photolithography.
  • the metallized circuit traces 22 are deposited directly on the dielectric layer 42 such as by vapor deposition, screen printing or direct writing.
  • the external lead 32 is typically an electrically conductive, high strength, copper alloy such as copper alloy 194 (nominal composition by weight: 2.3% iron, 0.03% phosphorous, 0.12% zinc and the balance copper) or copper alloy C7025 (nominal composition by weight of 3.0% nickel, 0.65% silicon, 0.15% magnesium and the balance copper) .
  • the external lead 32 is bonded to an outer end 26 of a circuit trace 22.
  • the bond 48 is any electrically conductive joint such as a silver- filled epoxy polymer or a low melting temperature solder such as a lead/tin alloy. Thermal compression and thermosonic welding may also be utilized.
  • the external lead 32 extends beyond the sidewall 40 and terminates proximate to the second surface 38.
  • an electrically insulating material 50 is disposed between the metallic lead 32 and the sidewall 40.
  • the electrically insulating material may be formed on the sidewall 40 and constitute a layer of a non- conductive polymer such as an epoxy.
  • this epoxy layer has a thickness between 0.013 mm and 0.13 mm (0.0005 inch and 0.005 inch) and preferably, the epoxy thickness is from 0.025 mm and 0.076 mm (0.001 to 0.003 inch).
  • the electrically insulating material 50' is mounted on the external lead 32 and may constitute a dielectric material 52 bonded by an adhesive 54 to the external lead 32.
  • An exemplary material for the dielectric layer 52 is a polyimide tape having a thickness between 0.025 mm and 0.13 mm (0.001 inch and 0.005 inch) .
  • the epoxies illustrated in Figure 2 may also coat the central portion of the external lead 32 in the configuration illustrated in Figure 3.
  • the external lead 32 is generally C-shaped and has the electrically insulating material adjacent to a central portion of the lead to electrically isolate the lead from an exposed edge of a sidewall 40.
  • a further advantage of the embodiments illustrated in Figures 2 and 3 is that the convex surface 56, that surface of the external lead 32 that is not adjacent to the sidewall 40, may be electrically conductive along the entire length.
  • the semiconductor package may then be mounted either vertically by attaching a mid-portion of the convex portion of the external lead to the printed circuit board or in conventional J-lead fashion by mounting to an end 62 of the external lead 32 proximate to the second surface 38 to the printed circuit board.
  • the leads may also have the shape of an inverted "L" (as shown by reference numeral 57 in Figure 6) .
  • the inverted L-shape is particularly suited for attachment to the through holes of a printed circuit board and provides socketability.
  • An electronic package 70 has a metallic substrate 72 that is typically copper, aluminum or an alloy thereof as described above.
  • a dielectric layer 74 is formed on at least that surface 76 of the metallic substrate 72 that will receive circuit traces 22. Suitable materials for the dielectric are anodic films and polymer layers.
  • the dielectric layer 74 has a thickness of under 10 microns to minimize the thermal insulative effect of the dielectric layer. Preferably, the thickness of the dielectric layer 74 is under about 5 microns and most preferably, the thickness is from about 1 to about 3 microns.
  • Circuit traces 22 are deposited on the dielectric layer 74 optionally with an intervening adhesive layer 46 as described above.
  • the circuit traces 22 have a first end 24 that is electrically interconnected to a semiconductor device 78 such as by wire bonds 80.
  • the opposing second ends 26 of the circuit traces 22 terminate adjacent to, or preferably at, a perimeter 82 of the metallic substrate 72.
  • a single row of electrical interconnects 84, in the form of solder balls, solder columns, or any other suitable shape, are bonded to the second ends 26.
  • the bonding pattern of the package 70 would simulate that of a package having external J or C-shaped leads without the requirement that the external leads extend along the sidewalls of the package.
  • a higher density of leads, that still simulates a J-shape lead configuration, is a staggered row of solder balls 84 as illustrated in planar view in Figure 5. While there are two rows of solder balls, the centers of each ball is offset from each adjacent solder ball relative to a midpoint of the package as indicated by dashed lines 86.
  • the electronic package 90 illustrated in cross- sectional representation in Figure 6 replaces the solder balls with preformed external leads 32.
  • a first end 91 of the external leads 32 is electrically interconnected to circuit traces 22 by an electrically conductive joint 48.
  • An opposing second end 92 of the external leads 32 either extends away from the package 90 in a gull wing configuration or extends under the package in a C- shaped configuration.
  • the electronic package 100 illustrated in Figure 7 has external leads 32 bonded to a circuit trace 22 by an electrically conductive joint 48. Suitable electrically conductive joining materials include low temperature solders, conductive polymers, brazes and welds.
  • a semiconductor device 78 is bonded to the package substrate 72 by a die attach 102. The semiconductor device 78 is then electrically interconnected to either the circuit traces 22 or to inner lead ends 91 of the metallic lead 32 or a combination thereof. Wire bonds 80 are attached either before or after the leads 32 of a leadframe are attached. If before leadframe attachment, the use of aluminum base (aluminum or aluminum alloy) bond wires with wedge bonds to the external leads is facilitated because metallic substrate is readily rotatable on an automated bonder.
  • Encapsulation of the package 100 may be by a polymer 104 such as an epoxy or a silicone.
  • a window frame 106 bonded to the metallic leads 32 is useful to define the cavity to be encapsulated by the polymer 104.
  • a discrete cover 107 may be bonded to the metallic leads 32 to encapsulate the semiconductor device 78.
  • this assembly includes a vent hole 108 that is subsequently sealed with either a polymer or metallic plug.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

There is disclosed a package for housing an integrated circuit device having a metallic base component (12). The base component (12) is coated with a dielectric layer (42) and conductive circuit traces (22) are formed on this dielectric layer (42). External leads (32) are electrically interconnected (48) to an outer end (26) of the circuit traces (22) adjacent to the perimeter (28) of the metallic substrate (12). The external leads (32) extend along sidewalls (40) of the metallic substrate (12) terminating proximate to the opposing side (38) of the substrate (12). An electrically insulating material (50) is disposed between the external leads (32) and the sidewalls (40) of the metal substrate (12) providing electrical isolation. In a second embodiment of the invention, a single row of solder balls is disposed about the periphery of the metallic substrate and bonded to the outer ends of the circuit traces.

Description

METAL ELECTRONIC PACKAGE WITH PERIPHERALLY ATTACHED LEADS
The present invention relates to metal packages for housing one or more integrated circuit devices. More particularly, circuitry formed on a surface of the package base electrically interconnects the integrated circuit device to a plurality of peripheral external leads.
An adhesively sealed metal package is disclosed in U.S. Patent No. 4,939,316 to Mahulikar et al. This package has a metallic base and a cover. A leadframe is disposed between the base and the cover and adhesively bonded to both. The leadframe may include a centrally positioned die attach paddle with an integrated circuit device bonded to the paddle. Bond wires electrically interconnect the device to the leadframe.
An advantage of metal packages over molded plastic packages such as quad flat packs (QFPs) or ceramic packages such as ceramic dual in line packages (CERDIPs) is improved thermal conduction. The metal package removes heat generated during the operation of the device more efficiently than either a plastic or a ceramic package. The improved heat dissipation is due to both the improved thermal conduction of the metallic components and the ability of the components to disperse heat laterally along all surfaces of the package. The improved thermal dissipation permits encapsulation of more complex and higher power integrated circuit devices than is possible with plastic or ceramic packages. An objective of electronic package design is to minimize both the thickness of the electronic package and the package footprint. The footprint is the area on a printed circuit board occupied by the body of the package and the external leads that interconnect the package to the printed circuit board. In a quad flat pack, either metal or plastic, the leads extend outwardly from the body of the package increasing the package footprint. One way to minimize the increase in the package footprint is to use J-shaped leads that extend along the sidewalls of the package and then curl beneath the package base. Such a package arrangement is disclosed in U.S. Patent No. 4,711,700 to Cusack. J-shaped leads are effective when the package base is formed from an electrically non-conductive material such as a ceramic or plastic. The leads are also effective when the package base is an electrically conductive material having surfaces coated with an electrically non-conductive material, such as an aluminum alloy base coated with an anodic film. However, J-shaped leads are less effective when the metallic base component has one or more electrically conductive sidewalls that have the potential to electrically short circuit the leads. Another approach to reduce the package footprint is to replace the leads with a plurality of solder balls formed on a surface of the package base. This package, known as a ball grid array, is disclosed in International Application Seria.1 No. PCT/US95/08305, published on February 1, 1996. One metal ball grid array package has an aluminum alloy base that is coated with an anodic film. A semiconductor device is mounted on a central portion of the base. Electrically conductive circuit traces extend outward from this central region and terminate in an array of ball attach pads. The semiconductor device is electrically interconnected to the inner terminations of the circuit traces while solder balls are mounted to the outer terminations.
While the solder balls reduce the footprint of the package, the array of solder balls presents a different pattern for electrical interconnection to a printed circuit board requiring re-design of circuit traces formed on the printed circuit board. There remains, therefore, a need for peripherally attached leads for use with metal electronic packages that do not require re-design of the circuit traces on a printed circuit board and are amenable to metal substrates having electrically conductive sidewalls. Accordingly, it is an object of the invention to provide a peripherally attached metal electronic package having a footprint that is similar to that of a standard quad flat pack. It is a feature of the invention that the package includes, in one embodiment, peripherally attached, generally C- shaped metallic leads that are electrically isolated from the package sidewalls by an electrically insulating material. It is a feature of another embodiment of the invention that the external leads are a single row of peripherally attached solder balls that may be in either a straight line arrangement or a staggered arrangement. Among the advantages of the invention are that the metal electronic packages of the invention have a smaller footprint than achieved with a conventional quad flat pack. The packages do not require a separate metal cover and are thinner and lower weight than conventional packages. The metal packages are particularly amenable to high volume, low cost, manufacture.
In accordance with one embodiment of the invention, there is provided an electronic package assembly. The package assembly has a metallic substrate with first and second opposing surfaces separated by (N) sidewalls. A dielectric layer coats the first and second surfaces and up to (N) sidewalls. Circuit traces are formed on the dielectric layer on the first surfaces. The circuit traces have first ends that are electrically interconnected to a semiconductor device and opposing second ends that terminate at a perimeter of the metallic substrate. External leads are bonded to the second ends and extend beyond the sidewalls and terminate proximate to the second surface of the metallic substrate. An electrically insulating material is disposed between the metallic leads and respective sidewalls.
In accordance with another embodiment of the invention, there is provided a metallic substrate coated with a dielectric film that has a thickness of less than five microns. Circuit traces are formed on the dielectric film. The circuit traces have first ends that are electrically interconnected to a semiconductor device and opposing second ends that terminate at a perimeter of the metallic substrate. Electrical interconnects are bonded to the second ends.
The above stated objects, features and advantages will become more apparent from the specification and drawings that follow.
Figure 1 illustrates in top planar view a panel for the manufacture of a plurality of metal electronic package substrates.
Figure 2 illustrates in cross-sectional representation external C-shaped leads in accordance with an embodiment of the invention.
Figure 3 illustrates in cross-sectional representation external C-shaped leads in accordance with another embodiment of the invention. Figure 4 illustrates in cross-sectional representation peripheral solder balls in accordance with an embodiment of the invention.
Figure 5 illustrates in planar view a peripheral row of staggered solder balls. Figure 6 illustrates peripherally attached external leads in accordance with an embodiment of the invention.
Figure 7 illustrates external leads attached to circuit traces in accordance with an embodiment of the invention.
Figure 8 illustrates external leads attached to circuit traces in accordance with another embodiment of the invention.
Figure 1 illustrates a panel 10 used to form a plurality of metal package substrates 12-20. The panel 10 is formed from a thermally conductive, electrically conductive, material such as copper aluminum or an alloy thereof. Aluminum alloys of the 3000, 5000 and 6000 series as designated by the Aluminum Association, Inc. are most preferred.
3000 series alloys contain up to about 1.5% by weight manganese, along with other alloying elements. A most preferred 3000 series aluminum alloy is aluminum alloy 3003 having a nominal composition, by weight, of 0.12% copper, 1.2% manganese and the balance aluminum.
5000 series alloys contain magnesium and usually chromium as well. Preferred aluminum alloys of the 5000 series include aluminum alloy 5086 (nominal composition by weight, 0.20%-0>7% manganese, 3.5%-4.5% magnesium and the balance aluminum); 5252 (nominal composition by weight, 2.2%-2.8% magnesium, and the balance aluminum); 5657 (nominal composition by weight, 0.6%-1.0% magnesium, the balance aluminum) ; and 5457 (nominal composition by weight, 0.08%-1.2% magnesium, 0.15%-0.45% manganese and the balance aluminum) . 6000 series alloys contain silicon and magnesium in approximate proportions to form magnesium suicide. A most preferred aluminum alloy of the 6000 series is aluminum alloy 6061 (nominal composition by weight, 0.4%-0.8% silicon, 0.15%-0.4% copper, 0.8%-1.2% magnesium, 0.04%-0.35% chromium and the balance aluminum) .
The panel 10 is coated with a dielectric layer. When the panel 10 is formed from aluminum or an aluminum alloy, the dielectric layer may be an anodic film. Preferred anodic films are formed by integral color anodization as disclosed in U.S. Patent No. 5,066,368 to Pasqualoni et al. When the panel 10 is formed from copper or a copper base alloy, the dielectric layer is typically a polymer film, such as a thin film of epoxy. The dielectric film has a thickness of under 10 microns to maximize the conduction of heat to the metallic substrate. Preferably, the thickness of the dielectric film is under five microns. The minimum effective thickness is that dielectric film thickness that electrically isolates circuit traces formed on the dielectric film from the underlying metallic substrate.
Circuit traces 22 are formed on each of the metal substrates 12-20. The circuit traces 22 have first ends 24 and opposing second ends 26. The opposing second ends terminate adjacent to, or preferably at, a perimeter 28 of the individual metallic substrates 12-20. Subsequent to forming the circuit traces 22, the panel 10 is singulated by cutting or dicing the panel 10 (along dotted lines 30) to form a plurality of individual metallic substrates 12-20.
While Figure 1 is singulated to nine individual metallic substrates, both the panel 10 and individual metallic substrates may be of any desired size and the number metallic substrates formed from a panel may be of any desired quantity.
While Figure 1 illustrates the individual metallic substrates as square with four sidewalls, the substrates may be any shape and the actual number (N) of sidewalls is variable.
Since singulation occurs subsequent to deposition of the dielectric layer, the sidewalls of the individual metallic substrates formed along dotted line 30 during singulation are not coated with the dielectric layer and are electrically conductive and only up to (N-2) of the sidewalls will be coated with the dielectric layer. For the panel 10, each singulated metallic substrate may have two (substrates 12, 14, 18 and 20) three (substrates 13, 15, 17 and 19) or four (substrate 16) electrically conductive sidewalls.
Figure 2 illustrates in cross-sectional representation an external lead 32 for use with a singulated metallic substrate 12 (substrate 12 was arbitrarily picked, any singulated metallic substrate is equally amenable to the invention) . The metallic substrate 12 has a metal core 34 having a first surface 36 and a second surface 38.
Sidewalls 40 separate the first surface 36 from the second surface 38. A dielectric layer 42 is formed on the first surface 36 and on the second surface 38. As described above, typical dielectric layers 42 include anodic films and polymer films. Circuit traces 44 are formed on the dielectric layer 42.
In one embodiment, the circuit traces 22 are bonded to the dielectric layer 42 such as with a polymer adhesive 46 and formed into circuit traces by photolithography. Alternatively, as illustrated in Figure 3, the metallized circuit traces 22 are deposited directly on the dielectric layer 42 such as by vapor deposition, screen printing or direct writing. With reference back to Figure 2, the external lead 32 is typically an electrically conductive, high strength, copper alloy such as copper alloy 194 (nominal composition by weight: 2.3% iron, 0.03% phosphorous, 0.12% zinc and the balance copper) or copper alloy C7025 (nominal composition by weight of 3.0% nickel, 0.65% silicon, 0.15% magnesium and the balance copper) . The external lead 32 is bonded to an outer end 26 of a circuit trace 22. The bond 48 is any electrically conductive joint such as a silver- filled epoxy polymer or a low melting temperature solder such as a lead/tin alloy. Thermal compression and thermosonic welding may also be utilized.
The external lead 32 extends beyond the sidewall 40 and terminates proximate to the second surface 38. To prevent the external lead 32 from contacting an electrically conductive sidewall 40, an electrically insulating material 50 is disposed between the metallic lead 32 and the sidewall 40. The electrically insulating material may be formed on the sidewall 40 and constitute a layer of a non- conductive polymer such as an epoxy. Typically, this epoxy layer has a thickness between 0.013 mm and 0.13 mm (0.0005 inch and 0.005 inch) and preferably, the epoxy thickness is from 0.025 mm and 0.076 mm (0.001 to 0.003 inch). Alternatively, as illustrated in Figure 3, the electrically insulating material 50' is mounted on the external lead 32 and may constitute a dielectric material 52 bonded by an adhesive 54 to the external lead 32. An exemplary material for the dielectric layer 52 is a polyimide tape having a thickness between 0.025 mm and 0.13 mm (0.001 inch and 0.005 inch) . The epoxies illustrated in Figure 2 may also coat the central portion of the external lead 32 in the configuration illustrated in Figure 3.
As illustrated in both Figures 2 and 3, the external lead 32 is generally C-shaped and has the electrically insulating material adjacent to a central portion of the lead to electrically isolate the lead from an exposed edge of a sidewall 40.
A further advantage of the embodiments illustrated in Figures 2 and 3 is that the convex surface 56, that surface of the external lead 32 that is not adjacent to the sidewall 40, may be electrically conductive along the entire length. The semiconductor package may then be mounted either vertically by attaching a mid-portion of the convex portion of the external lead to the printed circuit board or in conventional J-lead fashion by mounting to an end 62 of the external lead 32 proximate to the second surface 38 to the printed circuit board. The leads may also have the shape of an inverted "L" (as shown by reference numeral 57 in Figure 6) . The inverted L-shape is particularly suited for attachment to the through holes of a printed circuit board and provides socketability. Ball grid array packaging technology having a bonding pattern similar to that of J-shaped leads is illustrated in cross-sectional representation in Figure 4. An electronic package 70 has a metallic substrate 72 that is typically copper, aluminum or an alloy thereof as described above. A dielectric layer 74 is formed on at least that surface 76 of the metallic substrate 72 that will receive circuit traces 22. Suitable materials for the dielectric are anodic films and polymer layers. The dielectric layer 74 has a thickness of under 10 microns to minimize the thermal insulative effect of the dielectric layer. Preferably, the thickness of the dielectric layer 74 is under about 5 microns and most preferably, the thickness is from about 1 to about 3 microns.
Circuit traces 22 are deposited on the dielectric layer 74 optionally with an intervening adhesive layer 46 as described above. The circuit traces 22 have a first end 24 that is electrically interconnected to a semiconductor device 78 such as by wire bonds 80. The opposing second ends 26 of the circuit traces 22 terminate adjacent to, or preferably at, a perimeter 82 of the metallic substrate 72. A single row of electrical interconnects 84, in the form of solder balls, solder columns, or any other suitable shape, are bonded to the second ends 26. Since there is provided only a single row of solder balls 84 bonded along the perimeter 82 of the metallic substrate 72, the bonding pattern of the package 70 would simulate that of a package having external J or C-shaped leads without the requirement that the external leads extend along the sidewalls of the package. A higher density of leads, that still simulates a J-shape lead configuration, is a staggered row of solder balls 84 as illustrated in planar view in Figure 5. While there are two rows of solder balls, the centers of each ball is offset from each adjacent solder ball relative to a midpoint of the package as indicated by dashed lines 86.
The electronic package 90 illustrated in cross- sectional representation in Figure 6 replaces the solder balls with preformed external leads 32. A first end 91 of the external leads 32 is electrically interconnected to circuit traces 22 by an electrically conductive joint 48. An opposing second end 92 of the external leads 32 either extends away from the package 90 in a gull wing configuration or extends under the package in a C- shaped configuration.
The electronic package 100 illustrated in Figure 7 has external leads 32 bonded to a circuit trace 22 by an electrically conductive joint 48. Suitable electrically conductive joining materials include low temperature solders, conductive polymers, brazes and welds. A semiconductor device 78 is bonded to the package substrate 72 by a die attach 102. The semiconductor device 78 is then electrically interconnected to either the circuit traces 22 or to inner lead ends 91 of the metallic lead 32 or a combination thereof. Wire bonds 80 are attached either before or after the leads 32 of a leadframe are attached. If before leadframe attachment, the use of aluminum base (aluminum or aluminum alloy) bond wires with wedge bonds to the external leads is facilitated because metallic substrate is readily rotatable on an automated bonder. Aluminum wedge bonds are preferred because a lead pitch smaller than the pitch obtainable with a ball-type wire bond is possible. Encapsulation of the package 100 may be by a polymer 104 such as an epoxy or a silicone. A window frame 106 bonded to the metallic leads 32 is useful to define the cavity to be encapsulated by the polymer 104.
Alternatively, as illustrated in Figure 8, a discrete cover 107 may be bonded to the metallic leads 32 to encapsulate the semiconductor device 78. Generally, this assembly includes a vent hole 108 that is subsequently sealed with either a polymer or metallic plug.
It is apparent that there has been provided in accordance with this invention, semiconductor packages having a reduced footprint that fully satisfy the objects, means and advantages set forth hereinbefore. While the invention has been described in combination with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications and variations as fall within the spirit and broad scope of the claims.

Claims

IN THE CLAIMS :
1. An electronic package assembly, characterized by: a metallic substrate (12) having first (36) and second (38) opposing surfaces separated by (N) sidewalls (40) ; a dielectric layer (42) formed on said first (36) and second (38) surfaces and up to (N) sidewalls (40) ; circuit traces (22) formed on said dielectric layer (42) on said first surface (36), said circuit traces (22) having first ends (24) electrically interconnected (80) to a semiconductor device (78) and opposing second ends (26) terminating adjacent to a perimeter (28) of said metallic substrate (12); external leads (32) bonded to said second ends (26) and extending beyond said sidewalls (40) and terminating proximate to said second surface (38) ; and an electrically insulating (50, 52) material disposed between said external leads (32) and respective sidewalls (40) .
2. The electronic package assembly of claim 1 characterized in that said dielectric layer (42) is formed on up to (N-2) of said respective sidewalls (40) . 3. The electronic package assembly of claim 2 characterized in that said external leads (32) extend along respective sidewalls (40) that are free of said dielectric layer (42) .
4. The electronic package assembly of claim 3 characterized in that said external leads (32) are generally C-shaped and terminate proximate to said second surface (38) .
5. The electronic package assembly of claim 4 characterized in that said electrically insulating material (50) is bonded to said respective sidewalls (40) .
6. The electronic package assembly of claim 4 characterized in that said electrically insulating material (52) is bonded (54) to said external leads (32) .
7. The electronic package assembly of claim 3 characterized in that said external leads (32) are generally L-shaped (57) and terminate beyond said second surface (38) .
8. An electronic package assembly (70, 100), characterized by: a metallic substrate (72) ; a dielectric layer (74) having a thickness of less than about 5 microns formed on a surface of said metallic substrate (72); circuit traces (22) formed on said dielectric layer (74) , said circuit traces (22) having first ends (24) electrically interconnected (80) to a semiconductor device (78) and opposing second ends (26) terminating at a perimeter (82) of said metallic substrate (72); and electrical interconnects (84) bonded to said second ends (26) .
9. The electronic package assembly (70) of claim 8 characterized in that said electrical interconnects (84) are a single row of peripherally attached solder balls.
10. The electronic package assembly (100) of claim 9 characterized in that said electrical interconnects are peripherally attached external leads (32) .
11. The electronic package assembly (100) of claim 10 characterized in that said external leads (32 ι are gull wing shaped.
12. The electronic package assembly (100) of claim 10 characterized in that said external leads (32) are C-shaped. AMENDED CLAIMS
[received by the International Bureau on 23 September 1997 (23.09.97); original claims 1-6, 8 and 10 amended; remaining claims unchanged (3 pages)]
1. An electronic package assembly, characterized by: a metallic substrate (12) having first (36) and second (38) opposing surfaces having (N) sidewalls (40); a dielectric layer (42) formed on said first (36) and second (38) surfaces and up to said (N) sidewalls (40); circuit traces (22) formed on said dielectric layer (42) on said first surface (36), said circuit traces (22) having first ends (24) electrically interconnected (80) to a semiconductor device (78) and opposing second ends (26) terminating adjacent to a perimeter (28) of said metallic substrate (12); external leads (32) bonded to said second ends (26) and extending beyond said sidewalls (40) and terminating proximate to said second surface (38); and an insulating (50,52) material disposed between said external leads (32) and said sidewalls (40).
2. The electronic package assembly of claim 1 characterized in that said dielectric layer (42) is formed on up to (N-2) of said sidewalls (40).
3. The electronic package assembly of claim 2 characterized in that said external leads (32) extend along said sidewalls (40) that are free of said dielectric layer (42).
4. The electronic package assembly of claim 3 characterized in that external leads (32) are generally C-shaped and terminate proximate to said second surface (38).
5. The electronic package assembly of claim 4 characterized in that said insulating material (50) is bonded to said sidewalls (40).
6. The electronic package assembly of claim 4 characterized in that said insulating material (52) is bonded (54) to said external leads (32).
7. The electronic package assembly of claim 3 characterized in that said external leads (32) are generally L-shaped (57) and terminate beyond said second surface (38).
8. An electronic package assembly (70, 100), characterized by: a metallic substrate (72) having first (36) and second (38) opposing surfaces having (N) sidewalls (40); a dielectric layer (74) formed on said first (36) and second (38) opposing surfaces and up to N-2 sidewalls (40); circuit traces (22) formed on said dielectric layer (74), said circuit traces (22) having first ends (24) electrically interconnected (80) to a semiconductor device (78) and opposing second ends (24) terminating at a perimeter (82) of said metallic substrate (72); and electrical interconnects (84) bonded to said second ends (26).
9. The electronic package assembly (70) of claim 8 characterized in that said electrical interconnects (84) are a single row of peripherally attached solder balls.
10. The electronic package assembly (70) of claim 8 characterized in that said electrical interconnects are peripherally attached external leads (32).
11. The electronic package assembly (100) of claim 10, characterized in that said external leads (32) are gull winged shaped.
12. The electronic package assembly (100) of claim 10 characterized in that said external leads (32) are C-shaped.
STATEMENT UNDER ARTICLE 19
In reference to the above-identified International patent application, this is the response to the PCT International Search Report (Under PCT Article 18 and Rules 43 and 44) mailed 20 August 1997 having a statutory period for response set to expire on 22 October 1997. Applicants enclose herewith replacement pages 14, 15 and 16 to replace pages 14-16 originally filed with this international application.
As a result of this amendment:
The following claims are unchanged: 7, 9, 11 and 12.
The following claims have been canceled: none.
The following claims are amended: 1-6, 8 and 10.
The following claims are new: none. Entry of this amendment and issuance of a favorable written opinion is respectfully solicited. If the authorized Officer has any questions, she is invited to contact Applicants' agent at the telephone number listed below.
PCT/US1997/007249 1996-05-22 1997-05-02 Metal electronic package with peripherally attached leads WO1997044821A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65160296A 1996-05-22 1996-05-22
US651,602 1996-05-22

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698660A (en) * 1982-03-30 1987-10-06 Fujitsu Limited Resin-molded semiconductor device
US4873615A (en) * 1986-10-09 1989-10-10 Amp Incorporated Semiconductor chip carrier system
US5404273A (en) * 1993-03-23 1995-04-04 Shinko Electric Industries Co., Ltd. Semiconductor-device package and semiconductor device
US5559316A (en) * 1993-09-25 1996-09-24 Nec Corporation Plastic-molded semiconductor device containing a semiconductor pellet mounted on a lead frame

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698660A (en) * 1982-03-30 1987-10-06 Fujitsu Limited Resin-molded semiconductor device
US4873615A (en) * 1986-10-09 1989-10-10 Amp Incorporated Semiconductor chip carrier system
US5404273A (en) * 1993-03-23 1995-04-04 Shinko Electric Industries Co., Ltd. Semiconductor-device package and semiconductor device
US5559316A (en) * 1993-09-25 1996-09-24 Nec Corporation Plastic-molded semiconductor device containing a semiconductor pellet mounted on a lead frame

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