WO1997033320A1 - Trenched dmos transistor with lightly doped tub - Google Patents

Trenched dmos transistor with lightly doped tub Download PDF

Info

Publication number
WO1997033320A1
WO1997033320A1 PCT/US1997/002974 US9702974W WO9733320A1 WO 1997033320 A1 WO1997033320 A1 WO 1997033320A1 US 9702974 W US9702974 W US 9702974W WO 9733320 A1 WO9733320 A1 WO 9733320A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
tub
transistor structure
conductivity type
principal surface
Prior art date
Application number
PCT/US1997/002974
Other languages
French (fr)
Inventor
Fwu-Iuan Hshieh
Lih-Ying Ching
Hoang Tran
Mike F. Chang
Original Assignee
Siliconix Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Incorporated filed Critical Siliconix Incorporated
Priority to EP97908734A priority Critical patent/EP0885460B1/en
Priority to AU20570/97A priority patent/AU2057097A/en
Priority to DE69735349T priority patent/DE69735349T2/en
Publication of WO1997033320A1 publication Critical patent/WO1997033320A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Definitions

  • This invention relates to integrated circuit structures and power transistor structures and more particularly to a DMOSFET with reduced on-resistance.
  • the gate electrode is a conductive material, typically polycrystalline silicon
  • the trenched structure increases transistor density, i.e. reduces the surface area consumed by the polysilicon gate electrode of each transistor.
  • transistor are used in lower voltage applications where a transistor includes a large number (thousands) of cells. Each cell is defined by a source region diffused into the substrate and by the gate electrode trenches.
  • the use of the trenches advantageously also reduces the undesirable parasitic JFET (junction field transistor) region which typically is present between adjacent transistors.
  • This resistance is also called the R,, ⁇ ,, (drain-source on-resistance) and is the resistance when the transistor is in its conductive state. It is desirable to minimize the on-resistance.
  • the breakdown voltage of a MOSFET must be maximized. Breakdown voltage is the maximum sustainable voltage above which destructive breakdown occurs at the bottom of the trench into the underlying drain region, due to an excessive local electrical field.
  • trenched MOSFETs are fabricated so that a P+ doped deep body region extends deeper into the substrate than does the bottom of the trench.
  • the N+ doped substrate (drain) region 12 is overlain by an N- doped epitaxial layer 14.
  • Epitaxial layer 14 is a heavily doped P+ body region 18 which is surrounded by a more lightly doped P tub region 16.
  • This lightly doped P tub region 16 is a lightly dosed diffusion which is strongly driven in, to a depth of 2.5 to 5 ⁇ m.
  • the drain-source on-resistance of a DMOSFET is reduced by providing a lightly doped P tub region surrounding the P+ body region, in order to enhance avalanche breakdown. Therefore, the resistance of the underlying epitaxial layer (drift region) is decreased, to achieve overall reduced device on- resistance. At the same time, the desired breakdown voltage can be achieved.
  • the on- resistance is further reduced by adding a pre-initial oxidation implant, i.e. phosphorus for an N channel device or boron for a P channel device.
  • an N JFET or pinch region (or a P region for a P channel device) which is more heavily doped than the underlying the N- doped epitaxial layer (drift region) is formed around the trench bottom and overlying the drift region.
  • the on-resistance is reduced by increasing doping concentration at the areas where the parasitic JFET would form, i.e. immediately underneath and at the bottom corners of the trench.
  • Figure 1 shows a cross section of a prior art planar DMOSFET transistor having a P tub surrounding the body region.
  • Figure 2 shows a cross section of a trenched DMOSFET in accordance with the present invention.
  • FIGS 3A through 3E show steps fabricating the transistor of Figure 2.
  • DMOSFET in accordance with the present invention. It is to be understood that this cross-section is dawn conventionally showing a portion of several cells of a typical transistor which may include thousands of such cells. However, a single cell transistor is also possible. Also while the present disclosure is directed to a transistor having a negatively (N) doped substrate, a positively (P) doped body region and an N doped source region, it is to be understood that complementary devices are also possible, wherein each dopant is reversed in terms of conductivity type.
  • the cross-sections shown here are not drawn to scale, but are intended to be illustrative. While the various transistor doped regions are shown here conventionally delineated by lines, this is illustrative rather than representative. In the figures, identical reference numbers used in various figures denote similar or identical structures. Also, the various parameters disclosed for junction depths, thicknesses, widths, doping concentrations, dosages and implantation energies are illustrative rather than limiting. Various materials may be used for the positive and negative type dopants. While the substances conventionally used for these doping types may be used, this is not limiting.
  • Figure 2 therefore shows a cross-section of one cell, with small portions of adjoining cells, of the present transistor which includes a drain region 40 which is N+ doped so as to have a resistivity of 1 to 10 milliohm»cm and being of conventional thickness.
  • a conventional metallized drain electrode (not shown) is formed on the bottom surface of drain region 40 as an electrical contact thereto.
  • Grown on the drain region 40 (substrate) is an N- doped epitaxial layer, the N- doped portions of which are designated 42. It is understood that region 42 may be formed other than by epitaxy.
  • N- drift region 42 has a resistivity of 0.7 to 1.0 milliohm»cm.
  • the epitaxial layer has a total thickness of 8 to 12 ⁇ m.
  • a P doped tub 46 is formed in the upper portion of the semiconductor body.
  • a typical doping level of P tub region is l X 10 16 to 1 X l ⁇ ,7 /cm 3 . Thus, this is a relatively lightly doped region.
  • a typical junction depth for the P tub 46 is 3 ⁇ m; a typical range is 2 to 4 ⁇ m.
  • Formed inside the P doped tub 46 is the P+ doped body region 48.
  • a typical doping level of the body region 48 is 1 X 10 ,8 /cm 3 to 5 X 10 ,8 /cm 3 . Included as part of the P+ doped body region 48 is a lower P+ deep body portion at the lower portion of the body region.
  • a typical junction depth of the P+ body region is 2.5 ⁇ m so as to be approximately 0.5 ⁇ m shallower than the surrounding P doped tub region 46.
  • Penetrating downward from the principal surface of the semiconductor body is a set of trenches; one such trench 50 is illustrated.
  • Trench 50 is lined, as are the others, by a gate oxide layer 54 which is typically 0.05 to 0.07 ⁇ m thick, and each trench is conventionally filled with a conductive doped polysilicon gate electrode gate 52.
  • the P+ body region extends 0.5 ⁇ m below the bottom of the trench 50.
  • An additional region of the transistor of Figure 2 (which is optional in accordance with the present invention) is N doped region 58 which underlies the trench 50 and also extends along the lower portion of the side walls of trench 50. Region 58 is called a JFET or pinch region.
  • N doped region 58 advantageously further reduces the on-resistance of this transistor by creating a more heavily doped area at the lower side walls and bottom of the trench, compared to the underlying epitaxial drift region 42. Thus, this further reduces on- resistance by increasing the doping concentration in this region, which is typically where the parasitic JFET would form.
  • a typical doping concentration of N doped region 58 is 1 X 10 15 /cm 3 . This doping concentration is optimized to maximize the trade-off between breakdown voltage and on-resistance.
  • a typical thickness of N region 58 is about 0.5 ⁇ m.
  • N+ doped source regions 56 are N+ doped source regions 56 having a typical junction depth of 0.5 ⁇ m.
  • a typical doping level of the N+ source regions 56 is about 6 X 10 ,9 /cm 3 at the principal surface.
  • each conductive gate electrode 52 Insulating the upper portion of each conductive gate electrode 52 i ⁇ a BPSG (boro-phosphosilicate glass) insulating layer 60 which is conventional and which is overlain by a body-source metalized layer 62. It is to be understood that the depiction herein is only of a small portion of the active part of the transistor. Each transistor active part is surrounded by a termination at the principal surface of the semiconductor body, the termination typically including doped regions and sometimes a trench. Conventional terminations are suitable for use in accordance with the present invention, and hence the termination is not illustrated or further described herein.
  • a typical width of each trench is 0.8 to 1.0 ⁇ m.
  • a typical cell pitch is 10 ⁇ m but this is only illustrative.
  • the cells may be of any one of various configurations.
  • Figure 3a One begins at showing of Figure 3a with an N+ doped substrate 40 conventionally fabricated to have a resistivity in the range of l to 10 milliohm»cm.
  • An N- doped epitaxial layer 42 is then grown thereon having a resistivity in the range of 0.7 to 1.0 milliohm»cm and a thickness of 6 to 11 ⁇ m.
  • the upper portion of epitaxial layer 42 is then more heavily doped using an N type blanket implant to a final doping level of e.g. I X 10 l5 /cm 3 .
  • This implantation step is optional, but if used is optimized to maximize the trade-off between breakdown voltage and on-resistance.
  • a conventional masking layer is deposited and patterned to define the remaining portion 68.
  • This mask layer 68 which is used to mask off subsequent the P type implant which forms the P tub regions 46.
  • This P implant results in a final P doping concentration in the range of 10 16 to 10 ,7 /cm 3 , after a relatively long diffusion takes place at high temperature in order to drive in this P tub diffusion to a junction of 2 to 4 ⁇ m.
  • This same step also drives in the previous N implant, which forms region 58 to a depth of 1 to 3 ⁇ m.
  • a P+ implant forms the P+ regions 48.
  • this may be a boron nitride or boron diffusion.
  • This P+ implant results in a final doping concentration of l to 5 X lO'Vcm 3 .
  • the P tub region 46 surrounds (i.e. has a junction depth deeper than) the P+ region 48 after all drive in steps are completed.
  • the principal surface of the semiconductor body has a conventional active mask layer formed thereon and patterned.
  • This active mask may be oxide or other suitable material.
  • This active mask defines the active portion of the transistor and hence masks off the transistor termination. It is to be understood that in the embodiments depicted herein only the active portion is shown, with the termination being outside the area of the drawing.
  • a trench mask layer is then formed and patterned (not shown) .
  • the trenches 50 are then etched anisotropically.
  • the trenches are then subject to a sacrificial oxide step to smooth their sidewalls and bottoms.
  • the gate oxide layer 54 is then grown conventionally to a thickness of 0.05 to 0.07 ⁇ m.
  • a layer of polysilicon 52 is then formed on the principal surface of the semiconductive body and filling all the trenches.
  • the polysilicon layer 52 is then doped to achieve maximum conductivity with an N type dopant (this step is not shown) .
  • a gate mask layer (polymask) is formed over the entire surface of the polysilicon, and patterned. The gate mask layer is then used to etch away the polysilicon except from the trenches while also leaving contact fingers on the principal surface connecting the gate electrodes in the various trenches (not shown) .
  • a source blocking mask 74 is formed on the principal surface of the substrate to define the regions where the source regions are to be formed. This masking layer 74 is conventionally patterned and then an N+ implant is carried out to define the N+ source regions 56.
  • the N+ source implant, the dopant being arsenic conventionally, results in a doping concentration of about 6 X 10 19 /cm 3 .
  • the N+ source mask layer 74 is then stripped.
  • a layer of boro-phosphosilicate glass (BPSG) is conventionally deposited to a thickness of 1 to 1.5 ⁇ m and doped.
  • a BPSG mask layer is then formed and patterned over the BPSG layer and then the BPSG mask layer is used to etch the BPSG, defining the BPSG regions 60 of Figure 2 insulating the top side of each conductive gate electrode 52.
  • the BPSG mask layer is stripped, and a source-body metal layer is deposited and masked to define the source-body metallization contacts 62 of Figure 2.
  • a passivation layer is formed and a pad mask is formed and patterned and use to define the pad contacts through the passivation layer (not shown) .
  • the formation of the metal layer 62 has a corresponding step to form the contact to drain region 40 (not shown) on the back side of the substrate. This completes the transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A trenched DMOS transistor has significantly reduced on-resistance. A lightly doped P tub (46) is formed surrounding the P+ body region (48) in order to enhance avalanche breakdown. Thus the epitaxial layer (42) resistivity can be decreased to reduce device on-resistance, while the desired breakdown voltage is also achieved. The on-resistance is further reduced by adding a pre-initial oxidation implant, i.e. phosphorous for an N channel device or boron for a P channel device. This forms a more heavily doped JFET or pinch region (58) at the bottom of the trench (50) and in the upper portion of the drift region (42). This NJFET region (58) (which is P doped for a P channel device) is more heavily doped than the underlying epitaxial layer (42) and surrounds the trench bottom, thus reducing on-resistance by increasing local doping concentration where otherwise a parasitic JFET would be present.

Description

TRENCHED DMOS TRANSISTOR WITH LIGHTLY DOPED TUB
BACKGROUND OF THE INVENTION Field of the Invention This invention relates to integrated circuit structures and power transistor structures and more particularly to a DMOSFET with reduced on-resistance.
Description of the Prior Art Power MOSFET (metal oxide semiconductor field effect transistor) devices are widely known for applications such as automobiles, electrical systems, power supplies and power management. In a trenched DMOS transistor, the gate electrode is a conductive material, typically polycrystalline silicon
(polysilicon) located in a trench in a transistor substrate, where the side walls and bottom of the trench are insulated with silicon dioxide. The trenched structure increases transistor density, i.e. reduces the surface area consumed by the polysilicon gate electrode of each transistor. Typically such transistor are used in lower voltage applications where a transistor includes a large number (thousands) of cells. Each cell is defined by a source region diffused into the substrate and by the gate electrode trenches.
The use of the trenches advantageously also reduces the undesirable parasitic JFET (junction field transistor) region which typically is present between adjacent transistors. This resistance is also called the R,,^,, (drain-source on-resistance) and is the resistance when the transistor is in its conductive state. It is desirable to minimize the on-resistance. At the same time, the breakdown voltage of a MOSFET must be maximized. Breakdown voltage is the maximum sustainable voltage above which destructive breakdown occurs at the bottom of the trench into the underlying drain region, due to an excessive local electrical field. Typically trenched MOSFETs are fabricated so that a P+ doped deep body region extends deeper into the substrate than does the bottom of the trench. Thus rather than having destructive breakdown at the trench bottom or corners, instead a non¬ destructive avalanche breakdown occurs from the lowest portion of this P+ deep body region into the underlying drain region. However, it is desirable to even further reduce on-resistance while maintaining a sufficiently high level of breakdown voltage.
U.S. Patent No. 5,304,831 issued April 19, 1994, to Hamza Yilmaz and commonly owned, incorporated herein by reference in its entirety, discloses in the context of a planar (non-trenched) MOSFET the realization of a reduced drain-source on-resistance. The disclosed structure with a shallow P body region, P tub, and P+ diffusions results in reduced channel resistance and reduced JFET resistance. Present Figure 1 is a redrawn version of Figure
17a from that patent. The reference numbers have been changed and the topside interconnect structure simplified in present Figure 1 to emphasize the relevant aspects. The N+ doped substrate (drain) region 12 is overlain by an N- doped epitaxial layer 14. Epitaxial layer 14 is a heavily doped P+ body region 18 which is surrounded by a more lightly doped P tub region 16. This lightly doped P tub region 16 is a lightly dosed diffusion which is strongly driven in, to a depth of 2.5 to 5 μm.
The remainder of the structure of Figure 1 is conventional, including the N+ doped source regions 20, the gate oxide layer 22, the gate electrode 24, and insulating layer 26 over the gate electrode, BPSG layer 28, and a passivation layer 32.
There is still a need for improved (reduced) drain-source on resistance for trenched DMOS transistors.
SUMMARY The drain-source on-resistance of a DMOSFET is reduced by providing a lightly doped P tub region surrounding the P+ body region, in order to enhance avalanche breakdown. Therefore, the resistance of the underlying epitaxial layer (drift region) is decreased, to achieve overall reduced device on- resistance. At the same time, the desired breakdown voltage can be achieved. In another embodiment the on- resistance is further reduced by adding a pre-initial oxidation implant, i.e. phosphorus for an N channel device or boron for a P channel device. By providing this additional implant, an N JFET or pinch region (or a P region for a P channel device) which is more heavily doped than the underlying the N- doped epitaxial layer (drift region) is formed around the trench bottom and overlying the drift region. Thus, the on-resistance is reduced by increasing doping concentration at the areas where the parasitic JFET would form, i.e. immediately underneath and at the bottom corners of the trench.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shows a cross section of a prior art planar DMOSFET transistor having a P tub surrounding the body region.
Figure 2 shows a cross section of a trenched DMOSFET in accordance with the present invention.
Figures 3A through 3E show steps fabricating the transistor of Figure 2.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 2 shows in cross-section a transistor
(DMOSFET) in accordance with the present invention. It is to be understood that this cross-section is dawn conventionally showing a portion of several cells of a typical transistor which may include thousands of such cells. However, a single cell transistor is also possible. Also while the present disclosure is directed to a transistor having a negatively (N) doped substrate, a positively (P) doped body region and an N doped source region, it is to be understood that complementary devices are also possible, wherein each dopant is reversed in terms of conductivity type.
Also, the cross-sections shown here are not drawn to scale, but are intended to be illustrative. While the various transistor doped regions are shown here conventionally delineated by lines, this is illustrative rather than representative. In the figures, identical reference numbers used in various figures denote similar or identical structures. Also, the various parameters disclosed for junction depths, thicknesses, widths, doping concentrations, dosages and implantation energies are illustrative rather than limiting. Various materials may be used for the positive and negative type dopants. While the substances conventionally used for these doping types may be used, this is not limiting. Figure 2 therefore shows a cross-section of one cell, with small portions of adjoining cells, of the present transistor which includes a drain region 40 which is N+ doped so as to have a resistivity of 1 to 10 milliohm»cm and being of conventional thickness. A conventional metallized drain electrode (not shown) is formed on the bottom surface of drain region 40 as an electrical contact thereto. Grown on the drain region 40 (substrate) is an N- doped epitaxial layer, the N- doped portions of which are designated 42. It is understood that region 42 may be formed other than by epitaxy. N- drift region 42 has a resistivity of 0.7 to 1.0 milliohm»cm. The epitaxial layer has a total thickness of 8 to 12 μm.
A P doped tub 46 is formed in the upper portion of the semiconductor body. A typical doping level of P tub region is l X 1016 to 1 X lθ,7/cm3. Thus, this is a relatively lightly doped region. A typical junction depth for the P tub 46 is 3 μm; a typical range is 2 to 4 μm. Formed inside the P doped tub 46 is the P+ doped body region 48. A typical doping level of the body region 48 is 1 X 10,8/cm3 to 5 X 10,8/cm3. Included as part of the P+ doped body region 48 is a lower P+ deep body portion at the lower portion of the body region. A typical junction depth of the P+ body region is 2.5 μm so as to be approximately 0.5 μm shallower than the surrounding P doped tub region 46.
Penetrating downward from the principal surface of the semiconductor body is a set of trenches; one such trench 50 is illustrated. Trench 50 is lined, as are the others, by a gate oxide layer 54 which is typically 0.05 to 0.07 μm thick, and each trench is conventionally filled with a conductive doped polysilicon gate electrode gate 52. Typically the P+ body region extends 0.5 μm below the bottom of the trench 50. An additional region of the transistor of Figure 2 (which is optional in accordance with the present invention) is N doped region 58 which underlies the trench 50 and also extends along the lower portion of the side walls of trench 50. Region 58 is called a JFET or pinch region.
N doped region 58 advantageously further reduces the on-resistance of this transistor by creating a more heavily doped area at the lower side walls and bottom of the trench, compared to the underlying epitaxial drift region 42. Thus, this further reduces on- resistance by increasing the doping concentration in this region, which is typically where the parasitic JFET would form. A typical doping concentration of N doped region 58 is 1 X 1015/cm3. This doping concentration is optimized to maximize the trade-off between breakdown voltage and on-resistance. A typical thickness of N region 58 is about 0.5 μm. (This is the thickness between the floor of trench 50 and the uppermost portion of the underlying drift region 42.) Formed in the upper portion of the transistor are N+ doped source regions 56 having a typical junction depth of 0.5 μm. A typical doping level of the N+ source regions 56 is about 6 X 10,9/cm3 at the principal surface.
Insulating the upper portion of each conductive gate electrode 52 iε a BPSG (boro-phosphosilicate glass) insulating layer 60 which is conventional and which is overlain by a body-source metalized layer 62. It is to be understood that the depiction herein is only of a small portion of the active part of the transistor. Each transistor active part is surrounded by a termination at the principal surface of the semiconductor body, the termination typically including doped regions and sometimes a trench. Conventional terminations are suitable for use in accordance with the present invention, and hence the termination is not illustrated or further described herein.
A typical width of each trench is 0.8 to 1.0 μm. A typical cell pitch is 10 μm but this is only illustrative. The cells may be of any one of various configurations.
An exemplary process flow for fabricating the transistor of Figure 2 is described hereinafter. It is to be understood that this process flow is not the only way to fabricate this structure but is illustrative. Also, the various parameters provided herein may be varied and still result in a structure and process in accordance with the present invention.
One begins at showing of Figure 3a with an N+ doped substrate 40 conventionally fabricated to have a resistivity in the range of l to 10 milliohm»cm. An N- doped epitaxial layer 42 is then grown thereon having a resistivity in the range of 0.7 to 1.0 milliohm»cm and a thickness of 6 to 11 μm. As shown in Figure 3A, the upper portion of epitaxial layer 42 is then more heavily doped using an N type blanket implant to a final doping level of e.g. I X 10l5/cm3. (One of ordinary skill in the art can readily determine the requisite energy levels and dosages to achieve this and the other doping concentrations disclosed herein.) This implantation step is optional, but if used is optimized to maximize the trade-off between breakdown voltage and on-resistance.
Then in Figure 3B a conventional masking layer is deposited and patterned to define the remaining portion 68. This mask layer 68 which is used to mask off subsequent the P type implant which forms the P tub regions 46. This P implant results in a final P doping concentration in the range of 1016 to 10,7/cm3, after a relatively long diffusion takes place at high temperature in order to drive in this P tub diffusion to a junction of 2 to 4 μm. This same step also drives in the previous N implant, which forms region 58 to a depth of 1 to 3 μm.
Then as shown in Figure 3C, using the same masking layer 68, a P+ implant forms the P+ regions 48. Alternatively instead of a boron implant, this may be a boron nitride or boron diffusion. This P+ implant results in a final doping concentration of l to 5 X lO'Vcm3. As can be seen, the P tub region 46 surrounds (i.e. has a junction depth deeper than) the P+ region 48 after all drive in steps are completed.
The remainder of the steps to fabricate the transistor are conventional. In the next step the principal surface of the semiconductor body has a conventional active mask layer formed thereon and patterned. This active mask may be oxide or other suitable material. This active mask defines the active portion of the transistor and hence masks off the transistor termination. It is to be understood that in the embodiments depicted herein only the active portion is shown, with the termination being outside the area of the drawing.
A trench mask layer is then formed and patterned (not shown) . Using the trench mask as a pattern, the trenches 50 are then etched anisotropically. The trenches are then subject to a sacrificial oxide step to smooth their sidewalls and bottoms. The gate oxide layer 54 is then grown conventionally to a thickness of 0.05 to 0.07 μm. A layer of polysilicon 52 is then formed on the principal surface of the semiconductive body and filling all the trenches. The polysilicon layer 52 is then doped to achieve maximum conductivity with an N type dopant (this step is not shown) .
Then a gate mask layer (polymask) is formed over the entire surface of the polysilicon, and patterned. The gate mask layer is then used to etch away the polysilicon except from the trenches while also leaving contact fingers on the principal surface connecting the gate electrodes in the various trenches (not shown) . Then in Figure 3E a source blocking mask 74 is formed on the principal surface of the substrate to define the regions where the source regions are to be formed. This masking layer 74 is conventionally patterned and then an N+ implant is carried out to define the N+ source regions 56. The N+ source implant, the dopant being arsenic conventionally, results in a doping concentration of about 6 X 1019/cm3. The N+ source mask layer 74 is then stripped. The following steps are conventional to complete the transistor. A layer of boro-phosphosilicate glass (BPSG) is conventionally deposited to a thickness of 1 to 1.5 μm and doped. A BPSG mask layer is then formed and patterned over the BPSG layer and then the BPSG mask layer is used to etch the BPSG, defining the BPSG regions 60 of Figure 2 insulating the top side of each conductive gate electrode 52.
Then the BPSG mask layer is stripped, and a source-body metal layer is deposited and masked to define the source-body metallization contacts 62 of Figure 2. Then a passivation layer is formed and a pad mask is formed and patterned and use to define the pad contacts through the passivation layer (not shown) . It is to be understood that the formation of the metal layer 62 has a corresponding step to form the contact to drain region 40 (not shown) on the back side of the substrate. This completes the transistor.
This disclosure is intended to be illustrative and not limiting; further variations and modifications will be apparent to one skilled in the art in light of this disclosure and are intended to fall within the scope of the appended claims.

Claims

We claim:
1. A transistor structure comprising: a substrate of a first conductivity type; a drift region overlying the substrate and of the first conductivity type, being doped to a higher concentration than the substrate; a tub region of a second conductivity type opposite to the first, and extending from a principal surface of the transistor structure into the drift region; a body region of the second conductivity type in the tub region, and being doped to a higher concentration than the tub region, extending from the principal surface into the drift region to a depth less than that of the tub region; a conductive gate electrode extending from the principal surface to a lesser depth than that of the tub region; and a source region of the first conductivity type, and extending from the principal surface into the body region.
2. The transistor structure of Claim 1, wherein a depth of the tub region is about 0.5 μm greater than a depth of the body region.
3. The transistor structure of Claim 1, wherein a depth of the tub region from the principal surface is at least 2.5 μm.
4. The transistor structure of Claim 1, wherein a doping concentration of the body region is at least 10 times that of the tub region.
5. The transistor structure of Claim 1, wherein a doping concentration of the tub region is less than 1 X I017/ cm3 .
6. The transistor structure of Claim 1, further comprising a pinch region of the first conductivity type, and of a higher doping concentration than the drift region, and located adjacent a lower portion of the gate electrode.
7. The transistor structure of Claim 6, wherein the pinch region extends adjacent the sides and bottom of the gate electrode, and is spaced apart from the substrate by an intervening portion of the drift region.
8. The transistor structure of Claim 1, wherein the body region and the tub region each extend deeper from the principal surface than does the gate electrode.
9. The transistor structure of Claim 1, wherein the tub region laterally surrounds the body region.
10. A method of forming a transistor structure, comprising the steps of: providing a semiconductor substrate of a first conductivity type; forming a drift region of the first conductivity type and doped to a lesser concentration than the substrate, and overlying the substrate; forming a tub region of a second conductivity type opposite to the first conductivity type, and extending from a principal surface of the drift region into the drift region; forming a body region of the second conductivity type and of higher doping concentration than the tub region and extending from the principal surface and laterally surrounded by the tub region; forming a trench extending from the principal surface; forming a conductive gate electrode in the trench; and forming a source region of the first conductivity type extending from the principal surface into the body region.
11. The method of Claim 10, wherein the step of forming the tub region comprises: implanting ions of the second conductivity type; and diffusing the implanted ion to a depth of at least 2 μm from the principal surface.
12. The method of Claim 10, further comprising the step of forming a pinch region of the first conductivity type and of a higher doping concentration than the drift region, and located so as to be adjacent a lower portion of the gate electrode.
13. The transistor structure of Claim 10, wherein a depth of the tub region is about 0.5 μm greater than that of the body region.
14. The transistor structure of Claim 10, wherein a depth of the tub region is at least 2.5 μm.
15. The transistor structure of Claim 10, wherein a doping concentration of the body region is at least 10 times that of the tub region.
16. The transistor structure of Claim 10, wherein a doping concentration of the tub region is less than
1 X 10π/cm3.
17. The transistor structure of Claim 12, wherein the pinch region extends adjacent the sides and bottom of the gate electrode, and is spaced apart from the substrate by an intervening portion of the drift region.
18. The transistor structure of Claim 10, wherein the body region and the tub region each extend deeper than does the gate electrode.
AMENDED CLAIMS
[received by the International Bureau on 5 August 1997 (05.08.97); original claim 1 amended; remaining claims unchanged (1 page)]
1. A transistor structure comprising: a substrate of a first conductivity type; a drift region overlying the substrate and of the first conductivity type, being doped to a lower concentration than the substrate; a tub region of a second conductivity type opposite to the first, and extending from a principal surface of the transistor structure into the drift region; a body region of the second conductivity type in the tub region, and being doped to a higher concentration than the tub region, extending from the principal surface into the drift region to a depth less than that of the tub region; a conductive gate electrode extending from the principal surface to a lesser depth than that of the tub region; and a source region of the first conductivity type, and extending from the principal surface into the body region.
2. The transistor structure of Claim 1, wherein a depth of the tub region is about 0.5 μm greater than a depth of the body region.
3. The transistor structure of Claim l, wherein a depth of the tub region from the principal surface is at least 2.5 μm.
4. The transistor structure of Claim l, wherein a doping concentration of the body region is at least 10 times that of the tub region.
5. The transistor structure of Claim 1, wherein a' doping cσncSen'fcratiOn of the tub region is less than
PCT/US1997/002974 1996-03-06 1997-03-05 Trenched dmos transistor with lightly doped tub WO1997033320A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP97908734A EP0885460B1 (en) 1996-03-06 1997-03-05 Trenched dmos transistor with lightly doped tub
AU20570/97A AU2057097A (en) 1996-03-06 1997-03-05 Trenched dmos transistor with lightly doped tub
DE69735349T DE69735349T2 (en) 1996-03-06 1997-03-05 TRIANGLE DIGITIZED TRANSISTOR TRANSISTOR

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/610,563 1996-03-06
US08/610,563 US5821583A (en) 1996-03-06 1996-03-06 Trenched DMOS transistor with lightly doped tub

Publications (1)

Publication Number Publication Date
WO1997033320A1 true WO1997033320A1 (en) 1997-09-12

Family

ID=24445538

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/002974 WO1997033320A1 (en) 1996-03-06 1997-03-05 Trenched dmos transistor with lightly doped tub

Country Status (5)

Country Link
US (1) US5821583A (en)
EP (1) EP0885460B1 (en)
AU (1) AU2057097A (en)
DE (1) DE69735349T2 (en)
WO (1) WO1997033320A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2248159A2 (en) * 2008-02-14 2010-11-10 Maxpower Semiconductor, Inc. Semiconductor device structures and related processes
US8704295B1 (en) 2008-02-14 2014-04-22 Maxpower Semiconductor, Inc. Schottky and MOSFET+Schottky structures, devices, and methods

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000515684A (en) * 1996-07-19 2000-11-21 シリコニックス・インコーポレイテッド High density trench DMOS transistor with trench bottom implant region
KR100218260B1 (en) * 1997-01-14 1999-09-01 김덕중 Trench type mos transistor fabricating method
US6163052A (en) * 1997-04-04 2000-12-19 Advanced Micro Devices, Inc. Trench-gated vertical combination JFET and MOSFET devices
JP3219045B2 (en) * 1998-02-20 2001-10-15 日本電気株式会社 Manufacturing method of vertical MISFET
US6084264A (en) * 1998-11-25 2000-07-04 Siliconix Incorporated Trench MOSFET having improved breakdown and on-resistance characteristics
ATE457084T1 (en) 1998-12-18 2010-02-15 Infineon Technologies Ag FIELD EFFECT TRANSISTOR ARRANGEMENT WITH A TRENCH-SHAPED GATE ELECTRODE AND AN ADDITIONAL HIGHLY DOPED LAYER IN THE BODY AREA
DE19908809B4 (en) * 1999-03-01 2007-02-01 Infineon Technologies Ag Method for producing a MOS transistor structure with adjustable threshold voltage
US6472678B1 (en) * 2000-06-16 2002-10-29 General Semiconductor, Inc. Trench MOSFET with double-diffused body profile
US20060038223A1 (en) * 2001-07-03 2006-02-23 Siliconix Incorporated Trench MOSFET having drain-drift region comprising stack of implanted regions
US7291884B2 (en) * 2001-07-03 2007-11-06 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide
US7033876B2 (en) * 2001-07-03 2006-04-25 Siliconix Incorporated Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
US7009247B2 (en) * 2001-07-03 2006-03-07 Siliconix Incorporated Trench MIS device with thick oxide layer in bottom of gate contact trench
US20030151092A1 (en) * 2002-02-11 2003-08-14 Feng-Tso Chien Power mosfet device with reduced snap-back and being capable of increasing avalanche-breakdown current endurance, and method of manafacturing the same
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP3954541B2 (en) * 2003-08-05 2007-08-08 株式会社東芝 Semiconductor device and manufacturing method thereof
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
KR100624053B1 (en) * 2004-09-09 2006-09-15 라이톤 세미컨덕터 코퍼레이션 Power semiconductor device for preventing punchthrough and manufacturing method thereof
DE112006000832B4 (en) 2005-04-06 2018-09-27 Fairchild Semiconductor Corporation Trenched gate field effect transistors and methods of forming the same
CN102738239A (en) * 2005-05-26 2012-10-17 飞兆半导体公司 Trench-gate field effect transistors and methods of forming the same
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
US8174067B2 (en) 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US9685523B2 (en) * 2014-12-17 2017-06-20 Alpha And Omega Semiconductor Incorporated Diode structures with controlled injection efficiency for fast switching
JP5498431B2 (en) 2011-02-02 2014-05-21 ローム株式会社 Semiconductor device and manufacturing method thereof
US10861938B2 (en) * 2013-07-19 2020-12-08 Nissan Motor Co., Ltd. Semiconductor device and method of manufacturing the same
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
JP6584857B2 (en) * 2015-08-11 2019-10-02 株式会社東芝 Semiconductor device
JP7458217B2 (en) 2020-03-19 2024-03-29 株式会社東芝 Semiconductor device, semiconductor device manufacturing method, inverter circuit, drive device, vehicle, and elevator
CN116646391A (en) * 2023-07-26 2023-08-25 深圳市锐骏半导体股份有限公司 Trench power device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168331A (en) * 1991-01-31 1992-12-01 Siliconix Incorporated Power metal-oxide-semiconductor field effect transistor
US5304831A (en) * 1990-12-21 1994-04-19 Siliconix Incorporated Low on-resistance power MOS technology
US5410170A (en) * 1993-04-14 1995-04-25 Siliconix Incorporated DMOS power transistors with reduced number of contacts using integrated body-source connections
US5465000A (en) * 1992-03-20 1995-11-07 Siliconix Incorporated Threshold adjustment in vertical DMOS devices

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5658267A (en) * 1979-10-17 1981-05-21 Nippon Telegr & Teleph Corp <Ntt> Insulated gate type field-effect transistor
WO1982002981A1 (en) * 1981-02-23 1982-09-02 Inc Motorola Mos power transistor
US4893160A (en) * 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US4931408A (en) * 1989-10-13 1990-06-05 Siliconix Incorporated Method of fabricating a short-channel low voltage DMOS transistor
JP2504862B2 (en) * 1990-10-08 1996-06-05 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US5404040A (en) * 1990-12-21 1995-04-04 Siliconix Incorporated Structure and fabrication of power MOSFETs, including termination structures
US5910669A (en) * 1992-07-24 1999-06-08 Siliconix Incorporated Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof
US5558313A (en) * 1992-07-24 1996-09-24 Siliconix Inorporated Trench field effect transistor with reduced punch-through susceptibility and low RDSon
KR940004847A (en) * 1992-08-04 1994-03-16 리차드 제이. 컬 A method of forming an epitaxial double diffusion metal oxide (DMOS) transistor structure having a low threshold hold voltage
US5316959A (en) * 1992-08-12 1994-05-31 Siliconix, Incorporated Trenched DMOS transistor fabrication using six masks
US5341011A (en) * 1993-03-15 1994-08-23 Siliconix Incorporated Short channel trenched DMOS transistor
US5468982A (en) * 1994-06-03 1995-11-21 Siliconix Incorporated Trenched DMOS transistor with channel block at cell trench corners
US5486772A (en) * 1994-06-30 1996-01-23 Siliconix Incorporation Reliability test method for semiconductor trench devices
US5688725A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance
JPH08306914A (en) * 1995-04-27 1996-11-22 Nippondenso Co Ltd Semiconductor device and its manufacture
US5567634A (en) * 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
US5689128A (en) * 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304831A (en) * 1990-12-21 1994-04-19 Siliconix Incorporated Low on-resistance power MOS technology
US5168331A (en) * 1991-01-31 1992-12-01 Siliconix Incorporated Power metal-oxide-semiconductor field effect transistor
US5465000A (en) * 1992-03-20 1995-11-07 Siliconix Incorporated Threshold adjustment in vertical DMOS devices
US5410170A (en) * 1993-04-14 1995-04-25 Siliconix Incorporated DMOS power transistors with reduced number of contacts using integrated body-source connections

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0885460A4 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2248159A2 (en) * 2008-02-14 2010-11-10 Maxpower Semiconductor, Inc. Semiconductor device structures and related processes
EP2248159A4 (en) * 2008-02-14 2011-07-13 Maxpower Semiconductor Inc Semiconductor device structures and related processes
US8076719B2 (en) 2008-02-14 2011-12-13 Maxpower Semiconductor, Inc. Semiconductor device structures and related processes
US8466025B2 (en) 2008-02-14 2013-06-18 Maxpower Semiconductor, Inc. Semiconductor device structures and related processes
US8659076B2 (en) 2008-02-14 2014-02-25 Maxpower Semiconductor, Inc. Semiconductor device structures and related processes
US8704295B1 (en) 2008-02-14 2014-04-22 Maxpower Semiconductor, Inc. Schottky and MOSFET+Schottky structures, devices, and methods

Also Published As

Publication number Publication date
US5821583A (en) 1998-10-13
EP0885460B1 (en) 2006-03-01
DE69735349T2 (en) 2006-11-30
EP0885460A4 (en) 1999-05-12
AU2057097A (en) 1997-09-22
EP0885460A1 (en) 1998-12-23
DE69735349D1 (en) 2006-04-27

Similar Documents

Publication Publication Date Title
US5821583A (en) Trenched DMOS transistor with lightly doped tub
EP2043158B1 (en) Trench DMOS transistor with trench bottom implant
US5689128A (en) High density trenched DMOS transistor
KR100759937B1 (en) A trench mosfet device, and a method of forming such a trench mosfet device
EP0616372B1 (en) Short channel trenched DMOS transistor
US6566201B1 (en) Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
KR100305978B1 (en) Field-effect trench transistors with lightly doped epitaxial regions on the surface of transistors
US6657254B2 (en) Trench MOSFET device with improved on-resistance
US6750104B2 (en) High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching using an etchant gas that is also a doping source
EP1454352A1 (en) Method for forming trench mosfet device with low parasitic resistance
KR20030085577A (en) Double diffused field effect transistor having reduced on-resistance

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TM TR TT UA UG UZ VN YU AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1997908734

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 97531816

Format of ref document f/p: F

WWP Wipo information: published in national office

Ref document number: 1997908734

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: CA

WWG Wipo information: grant in national office

Ref document number: 1997908734

Country of ref document: EP